JPH07131302A - Register circuit - Google Patents

Abstract

PURPOSE:To shorten the set-up time of input data and the data output time by making the latch operation path of master part latch into one logical step and omitting the number of logical steps for the data output path of slave part latch. CONSTITUTION:Before a clock edge input, an ML1 is turned to the through state of turning on M1 and M2 and turning off M3 and M4 and since M5 and M6 are turned off, concerning an SL1, signals generated by flip-flops FF of IV3 and IV4 appear at the output. When a clock edge is inputted, C is changed from high to low and CB is changed from low to high, IN and INB are disconnected by the M1 and M2 and the respective outputs of inverters IV1 and IV2 are connected to opposite side inputs by the M3 and M4. Therefore, the latch state of holding data is provided by the FF configuration. Concerning the SL1, the M5 and M6 are turned on, and outputs LB and L of the master part are directly transmitted to an output driving circuit by this gate and outputted. An MFF output driving circuit simultaneously generates a differential output signal by directly turning on and off a bipolar for pull-up and a pull-down MOS FET with the same signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register circuit and a latch circuit, and more particularly to a register circuit composed of a master side latch circuit, a slave side latch circuit and an output driver circuit.

[0002]

2. Description of the Related Art A static type register circuit is generally composed of two latch circuits, a master section and a slave section, and the one shown in FIG. 5 is known. Note that this register circuit is shown in Japanese Patent Laid-Open No. 61-220199, but the reset function is omitted from the register circuit.

In this register circuit, data input IN
Goes through the master section latch ML51 and the slave section latch S
The output OUT and its anti-phase output OUTB are output through L51. It is the clock signal C and its anti-phase signal CB that control these latch circuits. Master latch ML5
1 is provided with a MOS field effect transistor (FET) M51 to which a clock C is gate-inputted as a transfer gate for switching operation, through which a data input IN enters an inverter IV51 and outputs a signal LB. LB
Becomes an inverted signal L through the inverter IV52, and further through the transfer gate M52 for CB control to IV51.
Connected to the input of. LB becomes the master latch output.
The slave latch SL51 has almost the same configuration as the master latch, and the signal passing through the CB control transfer gate M53 passes through the inverter IV53 to become the signal OUT. OUT is an inverted signal OUT by the inverter IV54.
It becomes B, and is further connected to the input of IV53 through the transfer gate M54 of C control. OUT becomes a slave latch output, and OUTB becomes a reverse phase output if necessary.

Next, the operation will be described. The register circuit transfers the input data to the output in response to the signal edges of the clock signals C and CB, that is, the transition of C from high to low and CB from low to high. Before the clock edge is input, the transfer gates M51 and M54 are on and M52 and M53 are off.
Therefore, the master section is in a through state in which an output is output according to an input signal, and the slave section is in a latch state in which an input signal is cut off by a transfer gate and data is held by a flip-flop composed of two inverters. When a clock edge is input, the master unit enters a latch state in which IN information is stored, the slave unit enters a through state, and the data stored in the master is output. When C goes from low to high and CB goes from high to low, the master part returns to the through state and the slave part returns to the latched state, but the stored data only moves from the master to the slave and the register output does not change. These timing charts are shown in FIG. The setup time and hold time of the input data are tS and tH as the timing at which the latch circuit of the master unit can normally latch the input data with respect to the clock edge (time = 0).
Further, the data output delay time from the clock edge due to the through change of the slave unit becomes tD.

[0005]

The setup time tS, the hold time tH, and the data output delay time tD described in the conventional example are the main characteristics of the register circuit. The smaller these are, the more secure the timing margin of the system including the register is. It is possible to achieve high performance. However, tS needs to enter a clock edge at C and CB when L changes from the IN input through the two stages of the inverters IV51 and 52. For tH, it is necessary to maintain the IN signal for the time until the transfer gate M51 is turned off at this edge. Further, tD requires a time for turning on the transfer gate M53 from the clock C input and outputting it through one stage of the inverter IV53 or two stages including the IV54.

As described above, the time tS + tH determined by the master unit and the time tD that comes in the slave unit cannot be easily realized, and it is one of the factors that limit the increase of the system clock frequency, that is, the operating speed. Is becoming.

[0007]

In order to solve the above problems, the present invention uses the same master section as the opposite phase differential input and realizes the number of logic circuit stages up to the latch by one stage, and the tS + tH time is reduced. We are trying to shorten it. Further, the data output path of the slave section is directly output only by the clock-controlled transfer gate in order to shorten the tD time. further,
An output drive circuit is provided to drive a large output load using a differential signal by directly connecting a bipolar transistor to the output.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. This circuit includes a master section latch ML1 to which data signals IN and INB of opposite phases are input and output signals L and LB thereof.
Of the slave section latch SL1 which receives as input, and outputs OUT and OUTB thereof are register output signals. In the master section latch circuit ML1, respective inputs IN and INB are input to the inverters IV1 and 2 via the transfer gates M1 and 2 formed by MOS • FETs, and the respective outputs become LB and L, and at the same time, LB and L are transfer gates. It is connected to the input terminals of the inverters IV2, 1 on the opposite phase side via M4, 3 respectively. The control signals (gate terminal input) of the transfer gate are clock signals C of M1 and M2.
M3 and M4 are the inverted signals CB. In the slave section latch circuit SL1, the respective inputs LB and L are control signals C.
Inverter I through transfer gates M5, 6 of B
It is connected to two terminals of a flip-flop composed of V3 and V4. This terminal is directly input to an output drive circuit composed of bipolar transistors L1 and 2 and MOS • FETs M7 and 8. The base input of the bipolar transistor and the gate input of the FET are made into opposite-phase signals, and the emitter and drain terminals are connected to form outputs OUT and OUTB. Each of the transfer gates M1 to M5 may have a transmission gate configuration from both N-channel and P-channel MOSFETs.

Next, the operation will be described. Before inputting a clock edge, ML1 is in a through state in which M1, 2 are on, M3, 4 are off, and SL1 is M5, 6 off, so IV
Signals from the 3 and 4 flip-flops appear at the output.
When a clock edge is input and C changes from high to low and CB changes from low to high, IN and INB are disconnected by M1 and M2, and the respective outputs of the inverters IV1 and IV are connected to the opposite inputs at M3 and M4. Therefore, a flip-flop structure is formed and a latch state for holding data is set. SL1 is M
When 5 and 6 are turned on, the outputs LB and L of the master section are directly transmitted to the output drive circuit by this gate and output. At this time M
Since it is necessary to invert the flip-flops of IV3 and 4 for the outputs of 5 and 6, it is necessary to make the transfer gate side sufficiently larger than the flip-flop side. The output drive circuit is a pull-down bipolar and a pull-down M on the opposite side.
Differential output signals are simultaneously generated by directly turning on and off the OS • FET with the same signal.

Next, the performance of this circuit will be described. Regarding the setup time tS for data input, the clock edge can be input when each inverter of ML1 is inverted. In other words, it becomes possible to latch by the operation of one stage of the inverter. This is because the two stages of the conventional serial inverter can be operated in parallel and simultaneously by the differential input signal. The hold time is the same as the conventional example because it is the time until the transfer gates M1 and 2 are turned off after the clock is input. Output delay time t from clock input
As for D, it is output as soon as the transfer gates M5 and 6 of SL1 are turned on, and is output through the output drive circuit. Since the differential signal is used, the output can be directly output, and the flip-flop circuit is separately provided in parallel operation. Therefore, unlike the conventional circuit, it is not necessary to feed back the signals of the inverters 1 and 2 to create a flip-flop, and the output delay time can be shortened.

A second embodiment of the present invention will be described with reference to the circuit diagram of FIG. This is because the output driving circuit portion (Q1, 2, M7, 8) of the slave side latch circuit of the first embodiment is omitted, and the output of the transfer gate is directly output OUTB, O.
It is a UT. The output is driven by a transfer gate, which does not have a large drive capability, but when the output load is light, the drive circuit itself works as a load, so it is possible to operate faster if omitted. Further, it also reduces the number of elements.

Next, a third embodiment of the present invention will be described with reference to the circuit diagram of FIG. This further strengthens the output drive circuit portion of the slave side latch circuit of the first embodiment. In other words, output reduction MOS-FET M33, 3
Although bipolar transistors Q32 and 34 having a source terminal of No. 4 input to the base and an output of the collector are added, the logical relationship in operation is the same as that of the conventional example. In this example, the output drive is performed entirely by bipolar transistors, so a very large drive capacity can be obtained, and at the same time, the MOS / F
Since ET only supplies the base current, the size can be reduced.

Here, specific characteristics will be described by using data according to the Bi-CMOS design rule of the 0.6 μm class. First, in the first embodiment, the data setup time t
The waveform when S is confirmed is shown in FIG. The clock edge input time is set to Ons and the data input is set to -0.5ns, and the input voltage change time is set to 1ns. From the figure, the output L of the master latch is about 0.3 ns after data input.
B and L are switched, and outputs OUTB and OUT of the slave side latch are switched about 0.4 ns after the clock input. Each waveform has a good balance of rising and falling. Immediately after switching between C and CB, there is noise on L and LB. This is due to the transfer gate being turned on.
This is because the transient charging / discharging current is supplied from the B terminal. However, the degree is small and there is no problem in circuit operation.
Similarly, the waveform at the time of confirming the data hold time tH is shown in FIG. The data input is set to -0.3 ns with respect to the clock. Even if the data is inverted 0.3 ns before the clock edge, L and LB retain the original data without being inverted if the data transmission of the first stage inverter of the master unit is insufficient. In the waveform, some inverter changes appear as noise, but this is not a problem. Therefore, the slave side holds the data as it is with respect to the clock edge. It can be seen that tS + tH, which is the sum of the setup and hold times, is the data definite time required for data acquisition, which is about 0.2 ns in this example. In the conventional example, about 0.4-
It is 0.5 ns, which is generally about 0.3 to 0.4 ns even when an ECL system circuit capable of high-speed operation is used (provided that a delay of tD does not occur). In this way, the characteristic of the data acquisition time is improved to about 1/2.

The data output delay time tD with respect to the output load is shown in FIG. The data shows the second and third examples and the conventional example, and shows the average value of the rise and fall of the output. Example 2 is faster when the load is small, but about 0.2
With a large load of pF or more, Example 3 having a high driving capability is faster. It can be seen that the speed is increased to 1/2 to 1/3 as compared with the conventional example.

Next, a fourth embodiment, which is an application example of this circuit, will be described with reference to FIG. In this example, the output driving circuit portion of the slave latch circuit SL1 of the first embodiment has a logical function. Two sets of register circuits (that is, the same as those of the second embodiment) in which the output drive circuit of the first embodiment is omitted are prepared, and respective outputs SO, SOB and S1, S are provided.
4 new output drive circuits SLD using 4 signals of 1B
The row selection 1/4 decoding operation is performed at.
The SLD connects two bipolar transistors Q41 and Q42 having base inputs by wired OR connection with a common emitter,
Two MOS-FETs with gate inputs, M41 and M42, are connected in series, and the emitter and drain connections are used as outputs. SO and SOB signals are input to Q41 and M41 in antiphase, respectively, and similarly, S1 and
Since S1B is input, 4 SLDs are combined.
The output of A0 to A3 is obtained.

In operation, Q41 and Q42 are low inputs and M4
Only the SLD of which 1 and 42 are high input output low, and the other outputs high. When a logic circuit is configured by the output signal of the register circuit, this logic circuit also serves as a register driving circuit, whereby the number of logic stages can be reduced and higher speed operation can be realized.

As another application example, since this register circuit is composed of two different latch circuits,
Each can also be used as a single latch circuit. Furthermore, by connecting the output drive circuit of the present invention, it becomes possible to easily drive a large load.

[0019]

As described above, the register circuit of the present invention realizes the latch operation path of the master section latch with one logic stage by using the differential signal as an input, and the data output path of the slave section latch. The number of logic stages is omitted and the output drive circuit is directly connected. This will set up the input data +
Hold time is about 1/2 of the conventional one, and data output time is 1
The value can be reduced to / 2 to 1/3, and the effect of significant characteristic improvement was obtained.

[Brief description of drawings]

FIG. 1 is a register circuit connection diagram showing a first embodiment of the present invention.

FIG. 2 is a connection diagram of a slave circuit of a register circuit showing a second embodiment of the present invention.

FIG. 3 is a slave circuit latch circuit connection diagram of a register circuit showing a third embodiment of the present invention.

FIG. 4 is a connection diagram of a register circuit + logic decoder circuit showing a fourth embodiment of the present invention.

FIG. 5 is a connection diagram of a register circuit showing a conventional example.

FIG. 6 is a timing chart of a general register circuit.

FIG. 7 is a setup operation confirmation waveform in the register circuit according to the first embodiment of the present invention.

FIG. 8 is a hold operation confirmation waveform in the register circuit according to the first embodiment of the present invention.

FIG. 9 is a data output time characteristic with respect to an output load in the register circuits of the second and third embodiments of the present invention and the conventional example.

[Explanation of symbols]

 IN, I0, I1, to B input signal L, L0, L1, to B master section latch output OUT, S0, S1, to B register circuit output A0 to 3 decoder circuit output ML1 to 51 master section latch SL1 to 51 slave section Latch SLD output drive circuit IV1 to 54 inverter L1 to 42 bipolar transistor M1 to 54 MOS field effect transistor

Claims (4)

[Claims] 1. A register circuit in which a master-side latch circuit and a slave-side latch circuit that receive a differential data signal are connected in series, wherein the master-side latch circuit passes the differential data signal through a first transfer gate, respectively. Two first transfer logic circuits for receiving and two second transfer gates for transmitting the output of one first inverter logic circuit to the input of the other inverter logic circuit,
The slave-side latch circuit has a flip-flop circuit that receives the true complementary output of the master-side latch circuit via a third transfer gate, and a signal for controlling ON / OFF of the first to third transfer gates. A register circuit characterized by using a clock signal and its reverse phase signal as a signal. 2. A drive circuit for receiving the output of the slave side latch circuit is further provided, and the drive circuit includes a first bipolar transistor for receiving a true complementary output of the slave side latch circuit, and each first bipolar transistor. 2. The register circuit according to claim 1, further comprising a field effect transistor connected in series with each other and receiving an output on the opposite phase side of the true complementary output. 3. The register circuit according to claim 2, further comprising a second bipolar transistor having a base connected to a source of the field effect transistor. 4. The drive circuit further comprises a third bipolar transistor, the third transistor being the first bipolar transistor.
4. The register circuit according to claim 2, wherein a wired OR type logic circuit is configured with the bipolar transistor.