WO2021258801A1 - Clock circuit system, computing chip, hash board, and data processing device - Google Patents

Abstract

A clock circuit system, a computing chip, a hash board, and a data processing device. The clock circuit system comprises a primary clock circuit and a local clock circuit. The primary clock circuit comprises multiple cascaded clock drive circuits, and each clock drive circuit comprises one or more delay elements that delay clock signals. The local clock circuit comprises a first input end coupled to a first port of the primary clock circuit; a second input end coupled to a second port of the primary clock circuit; and a logic gate element. At least one delay element of the primary clock circuit is present between the first port and the second port. In the present disclosure, pulse signals having good performance can be generated by using a simplified clock circuit system.

Description

Clock circuit system, computing chip, computing power board and data processing equipment

Cross-references to related applications

This application is based on the application with the CN application number 202010572765.8 and the filing date of June 22, 2020, and claims its priority. The disclosure of the CN application is hereby incorporated into this application as a whole.

Technical field

The present disclosure relates to the field of electronic circuits, and more specifically to a clock circuit system, and a computing chip, a computing power board, and a data processing device using the clock circuit system.

Background technique

The use of pipeline structure is a common method of chip design. Using the pipeline structure can effectively improve the efficiency/throughput rate of performing data processing tasks. In the field of general-purpose CPUs, it is usually a pipeline related to instruction execution, so the processing time of the pipelines at all levels in the pipeline structure is not exactly the same. However, in many fields that rely on pure hardware computing (such as virtual digital currency computing, artificial intelligence (AI) computing, etc.), strict timing requirements are usually imposed. For example, the time of each stage of the pipeline needs to be precisely controlled to be consistent. Therefore, in these fields, a clock circuit system used to provide a clock signal for a pipeline structure often has a specific structure and function.

Summary of the invention

The embodiments of the present disclosure aim to use a simplified clock circuit system to generate a pulse signal with good performance, and the pulse signal can be used in a pipeline structure for performing computationally intensive data processing tasks.

According to a first aspect of the present disclosure, there is provided a clock circuit system including a main clock circuit and one or more local clock circuits. The master clock circuit includes a plurality of cascaded clock driving circuits, each clock driving circuit includes one or more delay elements that delay a clock signal, and the master clock circuit is configured to drive a clock signal along the plurality of clocks. Drive circuit propagation. Each of the one or more local clock circuits is associated with a corresponding clock drive circuit in the master clock circuit, and includes: a first input terminal coupled to a first terminal of the master clock circuit A port to draw a first clock signal from the main clock circuit; a second input terminal, coupled to a second port of the main clock circuit to draw a second clock signal from the main clock circuit; and a logic gate element, coupled It is connected to the first input terminal and the second input terminal, and is configured to generate a pulse signal based on the first clock signal and the second clock signal. Wherein, the second port is located downstream of the first port in the main clock circuit, and the corresponding clock driving circuit of the main clock circuit exists between the first port and the second port At least one delay element in.

According to the first aspect of the present disclosure, the local clock circuit further includes one or more additional delay elements that delay the second clock signal, and the one or more additional delay elements are provided between the logic gate element and the logic gate element. Between the second input terminal.

According to this first aspect of the present disclosure, the local clock circuit has one of the following various configurations: a first configuration in which the first port and the second port associated with the local clock circuit Located in the same stage of the clock driving circuit of the main clock circuit; a second configuration, wherein the first port and the second port associated with the local clock circuit are located in two adjacent stages of the main clock circuit In a clock driving circuit; or a third configuration, wherein there is at least one level of clock driving circuit of the master clock circuit between the first port and the second port associated with the local clock circuit.

According to this first aspect of the present disclosure, the one or more local clock circuits include a first local clock circuit and a second local clock circuit, and the one or more local clock circuits include a first local clock circuit and a second local clock circuit. A clock circuit, the first local clock circuit and the second local clock circuit each have a different configuration among the first configuration, the second configuration, and the third configuration.

According to the first aspect of the present disclosure, no delay element is provided between the logic gate element and the first input terminal and the second input terminal of the local clock circuit.

According to the first aspect of the present disclosure, the logic gate element is selected from one of an AND gate, a NAND gate, an OR gate, and a NOR gate; and the selection of the logic gate element is determined based on at least the following的: the type and number of the at least one delay element between the first port and the second port; the type and number of the delay element between the logic gate element and the second input terminal; and / Or the type of pulse signal required.

According to this first aspect of the present disclosure, the one or more delay elements include at least one of a buffer and an inverter.

According to this first aspect of the present disclosure, the local clock circuit is coupled to a corresponding one-stage pipeline circuit in a pipeline structure for performing data processing tasks to provide the pulse signal to the corresponding one-stage pipeline circuit.

According to the first aspect of the present disclosure, the pulse signal is provided to one or more sets of registers in the corresponding one-stage pipeline circuit, and the output terminal of the local clock circuit is connected to the one or more sets of registers. There are additional buffers or inverters between each set of registers.

According to this first aspect of the present disclosure, the register is a latch-type register that can be triggered by a high-level pulse or a low-level pulse of the pulse signal.

According to this first aspect of the present disclosure, the data processing task includes executing a hash algorithm or executing an AI calculation.

According to this first aspect of the present disclosure, the hash algorithm includes the SHA-256 algorithm.

According to a second aspect of the present disclosure, a computing chip is disclosed. The computing chip includes any clock circuit system as described herein.

According to a third aspect of the present disclosure, a computing power board is disclosed, which includes the computing chip as described herein.

According to a fourth aspect of the present disclosure, a data processing device is disclosed, the data processing device including the hashrate board as described herein.

According to various aspects of the present disclosure, a pulse signal with good performance can be generated with a simplified clock circuit system and lower power consumption. Through the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, other features and advantages of the present disclosure will become clear.

Description of the drawings

The drawings constituting a part of the specification describe the embodiments of the present disclosure, and together with the specification, serve to explain the principle of the present disclosure.

With reference to the accompanying drawings, the present disclosure can be understood more clearly according to the following detailed description, in which:

Fig. 1 shows a block diagram of a system according to an embodiment of the present disclosure;

Fig. 2 shows an exemplary configuration of a clock circuit system;

FIG. 3 shows an example of generating a pulse signal based on a first clock signal and a second clock signal that have a delay between each other;

4A-4D show exemplary configurations of an improved clock circuit system;

Figure 5 shows an exemplary configuration of a further improved clock circuit system;

Figure 6 shows a schematic diagram of a pipeline structure that can be used to implement the SHA-256 algorithm;

Fig. 7 shows a schematic block diagram of a computing chip according to an embodiment of the present disclosure;

FIG. 8 shows a schematic block diagram of a computing power board according to an embodiment of the present disclosure; and

Fig. 9 shows a schematic block diagram of a digital currency mining machine according to an embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to denote the same parts or parts with the same functions, and repetitive descriptions thereof are omitted. In this specification, similar reference numerals and letters are used to indicate similar items. Therefore, once a certain item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

For ease of understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not indicate the actual position, size, range, etc. Therefore, the disclosed content is not limited to the position, size, range, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components.

detailed description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that unless specifically stated otherwise, the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

The following description of at least one exemplary embodiment is actually only illustrative, and in no way serves as any limitation to the present disclosure and its application or use. That is to say, the circuits and methods for implementing the hash algorithm in this document are shown in an exemplary manner to illustrate different embodiments of the circuits or methods in the present disclosure, and are not intended to be limiting. Those skilled in the art will understand that they only illustrate exemplary ways that can be used to implement the present disclosure, rather than exhaustive ways.

The technologies, methods, and equipment known to those of ordinary skill in the relevant fields may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be regarded as part of the authorization specification.

When performing computationally intensive data processing tasks such as virtual digital currency calculations and artificial intelligence (AI) calculations, computing hardware often needs to run for a long time. For example, in order to obtain digital currency efficiently, a data processing device such as a digital currency mining machine needs to perform a large number of hash operations without interruption. Such computing hardware consumes power significantly and brings corresponding costs, such as electricity costs. The power consumption ratio is defined as the power consumed per unit of computing power of computing hardware, and it is one of the important performance indicators for measuring computing hardware. When the computing hardware includes or is implemented as a computing chip, the power consumption ratio can be reduced by reducing the number of components used by the computing chip. Advantageously, the chip area of the computing chip can also be reduced.

FIG. 1 shows a block diagram of a system 100 according to an embodiment of the present disclosure. The system 100 may include a clock circuit system 1000, a clock source 2000, and a pipeline structure 3000. The clock circuit system 1000 may be coupled with the clock source 2000 and the pipeline structure 3000.

In the system 100, the clock source 2000 does not separately provide a separate clock signal for each stage of the pipeline circuit of the pipeline structure 3000, but provides the initial clock signal to the clock circuit system 1000, and the clock circuit system 1000 is used for the pipeline structure 3000. Each stage of pipeline circuit provides a corresponding clock signal. To this end, the clock circuit system 1000 may be designed to include multiple stages of clock driving circuits, and each stage of the clock driving circuit may provide a clock signal for an associated one-stage pipeline circuit. Such a multi-level clock driving circuit of the clock circuit system 1000 may be called a master clock circuit, or also called a "master clock tree". The main clock circuit can be extended with the extension of the pipeline circuits at all levels of the pipeline structure.

Specifically, in the example of FIG. 1, the main clock circuit of the clock circuit system 1000 may include a plurality of clock driving circuits 1100, 1200, and 1300 connected in series. The initial clock signal provided by the clock source 2000 may be provided to the first-stage clock driving circuit 1100. The output clock signal of the first-stage clock driving circuit 1100 may be provided to the second-stage clock driving circuit 1200. The output clock signal of the second stage clock driving circuit 1200 may be provided to the third stage clock driving circuit 1300. The clock drive circuit of the subsequent stage generates a new clock signal in response to receiving the clock signal of the clock drive circuit of the previous stage. The clock signal generated by each stage of the clock driving circuit can be provided to the associated stage of pipeline circuit. In this way, the master clock circuit enables the clock signal derived from the same initial clock signal to propagate tens or hundreds of stages along the clock driving circuit of each stage, thus being a pipeline structure containing tens or even hundreds of pipeline circuits. Each stage of pipeline circuit provides a corresponding clock signal. As shown in FIG. 1, the clock driving circuits 1100, 1200, and 1300 can respectively provide corresponding clock signals for the pipeline circuits 3100, 3200, and 3300 in the pipeline structure 3000.

In order to realize the function of driving and propagating the clock signal, each stage of the clock driving circuit of the main clock circuit may be configured to include one or more circuit elements connected in series. In each stage of the clock drive circuit, the clock signal can propagate through these circuit elements in turn. As shown in FIG. 1, the clock driving circuit 1100 may include circuit elements 1110, 1120, and 1130 connected in series in sequence, the clock driving circuit 1200 may include circuit elements 1210, 1220, and 1230 connected in series in sequence, and the clock driving circuit 1300 may include circuit elements connected in series in sequence. Circuit elements 1310, 1320, 1330. These circuit elements may be active elements. Active components can compensate for the power of the input signal, so that the amplitude of the clock signal propagating through the clock driving circuit can be maintained.

Typical active components used in clock drive circuits may include inverters and buffers. Those skilled in the art know that the output signal of the inverter has an opposite level and phase relative to the input signal of the inverter. That is, in response to an input signal at a high level, the output signal of the inverter will be at a low level; and in response to an input signal at a low level, the output signal of the inverter will be at a high level. Unlike an inverter, the output signal of the buffer has the same level and phase relative to the input signal of the buffer. According to requirements, the circuit elements 1110, 1120, and 1130 in the clock driving circuit 1100 may all be inverters, all buffers, or any combination of inverters and buffers. Preferably, the clock driving circuit 1200 and the clock driving circuit 1300 should have the same configuration as the clock driving circuit 1100, which can maintain the consistency of the clock driving circuits at all levels, thereby helping to ensure the clock signals provided by the clock driving circuits at all levels. Precise timing.

Note that the input-output response of actual circuit elements (for example, inverters and buffers) will not be ideal. For example, the response (output signal) of each circuit element will have a certain delay relative to the stimulus (input signal). Therefore, each of the circuit elements 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, and 1330 in the clock driving circuit delays the clock signal passing through the circuit element. These circuit elements can also be referred to as delay elements. The delay characteristics of circuit elements can be used to generate specific signals, which will be described further below.

In many scenarios, the clock signal directly output by the clock driving circuit of the master clock circuit cannot be directly used in the pipeline circuit. For example, the clock signal propagating along the main clock circuit is usually a square wave signal (for example, a square wave with a 50% duty cycle), and the pipeline circuit may use a latch type (Latch) register. The latch type register needs to be triggered by a pulse signal. The pulse signal is a signal that only has a short-term high-level state (or a short-term low-level state) in each clock cycle. The square wave signal output by the main clock circuit is not suitable for being directly used to trigger the latch-type register in the pipeline circuit. In this case, the clock signal output by the clock driving circuit of each stage of the main clock circuit needs to be preprocessed before being provided to the pipeline circuit.

In order to preprocess the clock signal output by the clock driving circuit of the master clock circuit, the clock circuit system 1000 may further include local clock circuits 4100, 4200, and 4300. Each local clock circuit can be associated with a corresponding clock driving circuit, and with a corresponding pipeline circuit. Unlike the clock driving circuits in the master clock circuit that are connected in series, each local clock circuit can be coupled between the corresponding clock driving circuit and the corresponding pipeline circuit. For example, the local clock circuit 4100 can be coupled between the clock driving circuit 1100 and the pipeline circuit 3100, the local clock circuit 4200 can be coupled between the clock driving circuit 1200 and the pipeline circuit 3200, and the local clock circuit 4300 can be coupled between the clock driving circuit. Between the circuit 1300 and the pipeline circuit 3300. The local clock circuit may draw the clock signal from the corresponding clock driving circuit, preprocess the clock signal to generate an appropriate signal (for example, a pulse signal), and provide the generated appropriate signal to the corresponding pipeline circuit. A specific example of the configuration of the local clock circuit is described in detail below in conjunction with FIG. 2, and an improved embodiment regarding the configuration of the local clock circuit is further described in conjunction with FIGS. 4A-4D and FIG. 5.

It should be noted that the structure of the system 100 shown in FIG. 1 is only exemplary. For example, although the pipeline structure 3000 in FIG. 1 includes 3-stage pipeline circuits, the pipeline structure according to an embodiment of the present disclosure may include more or fewer pipeline circuits, such as 2 stages, 10 stages, 50 stages, or more than 100 stages. Clock drive circuit. Accordingly, the master clock circuit according to the embodiment of the present disclosure is not limited to include 3 clock driving circuits, but may include more or fewer clock driving circuits, such as 2, 10, 50, or more than 100 clocks. Drive circuit. In FIG. 1, a box with an ellipsis indicates an additional module 1400 that receives the output clock signal of the clock driving circuit 1300. The additional module 1400 may represent a plurality of clock driving circuits not specifically shown or may represent a tail load element. If the additional module 1400 represents multiple clock drive circuits not specifically shown, each of the multiple clock drive circuits will also include multiple circuit elements connected in series, and may also have an associated local clock circuit .

In addition, the border of the clock circuit system 1000 in FIG. 1 is shown with a dashed line, which means that the border shown in FIG. 1 is only exemplary. For example, in an alternative embodiment, the clock source 2000 may be part of the clock circuitry 1000. In another alternative embodiment, the local clock circuits 4100, 4200, 4300 may be located inside the corresponding one-stage pipeline circuit. However, from a functional point of view, such a local clock circuit can still be regarded as a part of the clock circuit system 1000.

FIG. 2 shows an exemplary configuration of the clock circuit system 1000. Compared with FIG. 1, FIG. 2 enlarges the size of the local clock circuit 4200 to specifically show the configuration of the local clock circuit 4200. As shown in FIG. 2, the local clock circuit 4200 may include one or more delay elements 4221, 4222, 4223 and a logic gate element 4230. Each of the delay elements 4221, 4222, 4223 may be an inverter or a buffer. The input 4211 of the local clock circuit 4200 may be coupled to the clock driving circuit 1200 associated with the local clock circuit 4200 in the main clock circuit, so as to receive the clock signal output by the clock driving circuit 1200. The logic gate element 4230 may be a logic gate element having two input terminals. A first signal path and a second signal path may exist between the input terminal 4211 and the two input terminals of the logic gate element 4230. The delay elements 4221, 4222, 4223 may be provided on the second signal path. The clock signal received by the input terminal 4211 can be directly input to one input terminal of the logic gate element 4230 via the first signal path as the first clock signal, and can be used as the delay element 4221, 4222, 4223 on the second signal path. The second clock signal is input to the other input terminal of the logic gate element 4230. Due to the existence of the delay elements 4221, 4222, 4223, the second clock signal will have a certain delay relative to the first clock signal. The amount of this delay is associated with the delay elements 4221, 4222, 4223. The logic gate element 4230 can perform logic operations on the first clock signal and the second clock signal that are delayed between each other, thereby generating a pulse signal. The generated pulse signal may be provided to a corresponding pipeline circuit (for example, the pipeline circuit 3200 of FIG. 1).

FIG. 3 shows an example of generating the pulse signal PLS based on the first clock signal CLK1 and the second clock signal CLK2 that are delayed from each other. As shown in FIG. 3, both the first clock signal CLK1 and the second clock signal CLK2 may be square wave signals. Although both the first clock signal CLK1 and the second clock signal CLK2 come from the input 4211, due to the existence of the delay elements 4221, 4222, 4223, the second clock signal CLK2 and the first clock signal CLK1 can be inverted , And the delay of the second clock signal CLK2 relative to the first clock signal CLK1 is d. Two signals, CLK1 and CLK2, can be input to the logic gate element 4230. The logic gate element 4230 may be an AND gate (AND2). The AND gate performs a logical AND operation on CLK1 and CLK2 to obtain the signal PLS, that is, PLS=AND2 (CLK1, CLK2). The obtained PLS is a high-level pulse signal with a pulse width of d. A high-level pulse signal refers to a signal with a short-term high-level state.

The phase difference and delay between the first clock signal CLK1 and the second clock signal CLK2 are related to the type and number of delay elements on the second signal path. If an odd number of inverters are provided on the second signal path, the obtained second clock signal CLK2 will have the opposite phase to the first clock signal CLK1. In addition, the delay of the second clock signal CLK2 relative to the first clock signal CLK1 depends on the sum of the delays of all delay elements provided on the second signal path. It should be understood that although FIG. 2 shows that the local clock circuit 4200 includes three delay elements, more or fewer delay elements may be used. The pulse width of the obtained pulse signal is associated with the delay between the two input signals, and therefore is also associated with the sum of the delays of all the delay elements provided on the second signal path.

It should be noted that although the PLS obtained in FIG. 3 is a high-level pulse signal, a different logic gate element (NAND2) can also be used to obtain a low-level pulse signal. A high-level pulse signal may be provided to a latch-type register that can be triggered by a high-level pulse, and a low-level pulse signal may be provided to a latch-type register that can be triggered by a low-level pulse.

It should also be noted that although FIG. 3 shows a situation where the first clock signal CLK1 and the second clock signal CLK2 are inverted, in other embodiments, the first clock signal CLK1 and the second clock signal CLK2 may also be In phase. The type of logic gate element can be selected accordingly, such as OR gate (OR2) or NOR gate (NOR2).

In addition, although the delay and pulse width shown in FIG. 3 are significant relative to the period width of the clock signal, this is only for the purpose of clarity. In an actual circuit, the delay caused by the delay element and the pulse width of the generated pulse signal may be smaller with respect to the period of the clock signal. For example, the delay caused by each delay element may be on the order of tens of picoseconds, and one clock cycle of the clock signal may be on the order of several nanoseconds.

Although the local clock circuit 4200 shown in FIG. 2 can generate the pulse signal required by the pipeline circuit, such a local clock circuit still has room for improvement. The local clock circuit 4200 requires necessary delay elements to be provided in the local clock circuit itself. These delay elements will occupy the chip area and increase the power consumption of the chip. In the case of pipeline circuits containing tens or hundreds of stages (correspondingly including tens or hundreds of local clock circuits), the number of delay elements used cannot be ignored. Moreover, when the available chip area is limited or the total power is limited, it may not be possible to provide enough delay elements in the local clock circuit. In this case, the delay d of the second clock signal CLK2 relative to the first clock signal CLK1 may be too small, which may cause the pulse width of the generated pulse signal to be too narrow. The trigger register requires a minimum pulse width, and a wide pulse width helps to trigger the register reliably. If the pulse width of the pulse signal generated by the local clock circuit is too narrow, it may not be able to effectively trigger the register in the pipeline circuit, which may cause the pipeline circuit to fail to perform data processing tasks correctly.

FIG. 4A shows an exemplary configuration of an improved clock circuit system 1000A according to an embodiment of the present disclosure. Similar to the clock circuit system 1000 described above, the clock circuit system 1000A may include a main clock circuit and one or more local clock circuits 4100, 4200, 4300. The master clock circuit may include multiple clock driving circuits 1100, 1200, and 1300 cascaded. The main clock circuit is configured to drive a clock signal to propagate along the plurality of clock drive circuits 1100, 1200, and 1300. Each clock driving circuit can each include one or more circuit elements 1110, 1120, 1130, 1210, 1220, 1230, 1310, 1320, 1330, these circuit elements can drive the propagation of the clock signal, and on the other hand also cause the clock signal Delay. Each of the local clock circuits 4100, 4200, and 4300 is respectively associated with a corresponding clock driving circuit in the main clock circuit. The local clock circuits 4100, 4200, 4300 of the clock circuit system 1000A may have a different configuration from the example of FIG. 2. The following description takes the local clock circuit 4200 as an example.

According to an embodiment of the present disclosure, the local clock circuit 4200 may have two different input terminals 4212 and 4213 that draw clock signals from the main clock circuit. The input terminal 4212 and the input terminal 4213 may be respectively coupled to the first port and the second port in the main clock circuit. The second port may be located downstream of the first port in the main clock circuit, and there is at least one circuit element in the clock driving circuit of the main clock circuit that can cause the clock signal delay between the first port and the second port. In this configuration, the second clock signal drawn by the input 4213 of the local clock circuit 4200 from the second port will have a delay relative to the first clock signal drawn by the input 4212 from the first port. This delay is caused by one or more circuit elements in the clock driving circuit in the master clock circuit, and does not depend on the delay element in the local clock circuit 4200.

As shown in FIG. 4A, the input terminal 4212 of the local clock circuit 4200 may be coupled to the output terminal (first port) of the second circuit element 1220 in the clock driving circuit 1200 to draw the first clock signal, and the local clock circuit 4200 The input terminal 4213 of may be coupled to the output terminal (second port) of the third circuit element 1230 in the clock driving circuit 1200 to draw the second clock signal. There is a circuit element 1230 between the first port and the second port. Since the circuit element 1230 itself is a delay element (inverter or buffer), the clock signal output by the output end of the circuit element 1230 (that is, the second clock signal drawn by the input end 4213) is relative to the output end of the circuit element 1220. The output clock signal (ie, the first clock signal drawn by the input terminal 4212) will have a certain delay.

According to an embodiment of the present disclosure, the local clock circuit 4200 may have a logic gate element 4230. The logic gate element 4230 can perform logic operations on each input signal. The first clock signal and the second clock signal drawn by the input terminals 4212 and 4213 may be provided to the logic gate element 4230. An input terminal of the logic gate element 4230 may be connected to the input terminal 4212 through a first signal path, thereby receiving the first clock signal. The other input terminal of the logic gate element 4230 may be connected to the input terminal 4213 through a second signal path, thereby receiving the second clock signal. The logic gate element 4230 may be configured to perform logic operations on the two input clock signals, thereby generating pulse signals, as discussed in relation to FIG. 3. One or more delay elements 4221, 4222, 4223 may be provided on the second signal path, so as to further delay the second clock signal on the second signal path. In this way, the delay between the two clock signals received by the two input terminals of the logic gate element 4230 includes not only the delay caused by the delay elements 4221, 4222, 4223 in the local clock circuit 4200, but also the delay caused by The delay caused by the circuit element 1230 in the clock driving circuit 1200. This increases the delay between the two clock signals received by the two input ends of the logic gate element 4230 without adding a delay element. Accordingly, the pulse width of the pulse signal generated by the logic gate element 4230 is increased, so that a better pulse signal can be provided to the pipeline circuit.

According to an embodiment of the present disclosure, the two input terminals 4212 and 4213 of the local clock circuit 4200 can be connected to any two other first port and second port on the clock driving circuit of the master clock circuit, as long as the first port and There is at least one circuit element in the clock driving circuit that can delay the clock signal between the second ports. The first port and the second port can have various configurations.

As an exemplary configuration, the first port and the second port respectively coupled to the two input terminals 4212 and 4213 of the local clock circuit 4200 may be located in the same level of clock driving circuit of the main clock circuit. Figure 4A shows an embodiment of this exemplary configuration. As an alternative embodiment, the input terminal 4212 of the local clock circuit 4200 may not be connected to the output terminal of the circuit element 1220, but to the output terminal of the circuit element 1210. In this case, the delay between the two clock signals received by the two input terminals of the logic gate element 4230 will further include the delay caused by the circuit element 1220, thereby further increasing the pulse width of the generated pulse signal.

As another exemplary configuration, the first port and the second port respectively coupled to the two input terminals 4212 and 4213 of the local clock circuit 4200 may be located in two adjacent stages of clock driving circuits of the main clock circuit. FIG. 4B shows an exemplary configuration of an improved clock circuit system 1000B. As shown in FIG. 4B, the input terminal 4212 of the local clock circuit 4200 may be connected to the output terminal (first port) of the circuit element 1220 of the clock driving circuit 1200, and the input terminal 4213 of the local clock circuit 4200 may be connected to an adjacent clock The output terminal (second port) of the circuit element 1310 of the driving circuit 1300.

As another exemplary configuration, there may be at least one level of clock driving circuit of the main clock circuit between the first port and the second port respectively coupled to the two input terminals 4212 and 4213 of the local clock circuit 4200. FIG. 4C shows an exemplary configuration of an improved clock circuit system 1000C. As shown in FIG. 4C, the input terminal 4212 of the local clock circuit 4200 may be connected to the output terminal (first port) of the clock driving circuit 1100, and the input terminal 4213 of the local clock circuit 4200 may be connected to the circuit element 1310 of the clock driving circuit 1300 The output terminal (the second port). The entire primary clock driving circuit 1200 exists between the first port and the second port. This situation can be advantageous because it can utilize the existing output port of the clock drive circuit without drawing the clock signal from the clock drive circuit, and will not affect the load inside the clock drive circuit of each stage.

According to an embodiment of the present disclosure, the positions of the first port and the second port can be determined based on the properties of the required pulse signal. The properties of pulse signals can include pulse width and signal type, and so on. For example, the number of circuit elements of the clock driving circuit that should exist between the first port and the second port can be determined based on the required pulse width of the pulse signal. When the required pulse width is relatively wide, the first port and the second port can be spaced far apart, so that there are more circuit elements that can cause delay between the two ports. When the type of pulse signal required is a high-level pulse signal, the position of the first port and the second port can be selected so that the number of inverters between the first port and the second port is the same as that of the local clock circuit. The sum of the number of inverters (if any) on the signal path is an odd number, so that the two clock signals input to the logic gate element are inverted (for example, the situation shown in FIG. 3).

In FIGS. 4A-4C, the delay elements 4221, 4222, 4223 are drawn with dashed boxes, which means that one or more of them may not be necessary. Since the delay of one or more circuit elements in the master clock circuit has been introduced, one or more of the one or more delay elements 4221, 4222, 4223 inside the local clock circuit 4200 can be removed. For example, in FIG. 4A, the elements 1230, 4221, 4222 can provide the delay originally provided by the elements 4221, 4222, 4223, so that the element 4223 can be removed while still satisfying one of the two clock signals input to the logic gate element 4230. Time delay requirements. As another example, the elements 1220, 1230, and 4221 may provide the delay originally provided by the elements 4221, 4222, 4223, thereby removing the elements 4222 and 4223. In some exemplary configurations, the delay elements inside the local clock circuit 4200 may be completely removed, as discussed below with respect to FIG. 4D.

FIG. 4D shows an exemplary configuration of an improved clock circuit system 1000D according to an embodiment of the present disclosure. In FIG. 4D, the input terminal 4212 of the local clock circuit 4200 may be coupled to the input terminal (first port) of the clock driving circuit 1200 to draw the first clock signal, and the input terminal 4213 of the local clock circuit 4200 may be coupled to the clock The output terminal (second port) of the third circuit element 1230 in the driving circuit 1200 is used to draw the second clock signal. In addition, there is no delay element between the logic gate element 4230 of the local clock circuit 4200 and the input terminals 4212 and 4213 of the local clock circuit 4200. In this example, the delay between the two clock signals received by the two input ends of the logic gate element 4230 can be completely provided by the elements 1210, 1220, and 1230 in the clock driving circuit 1200 of the master clock circuit, without having to be locally A delay element (for example, 4221, 4222, 4223) is provided in the clock circuit 4200. If the total delay of the circuit elements between the first port and the second port can provide a pulse signal of sufficient pulse width, the configuration shown in FIG. 4D can be preferably adopted, which can eliminate the delay element in the local clock circuit, thereby Minimize the area and power of the local clock circuit.

Compared with the example in FIG. 2, the advantages of the clock circuit systems 1000A-1000D exist in at least two aspects. On the one hand, without changing the arrangement of the delay element in the local clock circuit, a larger delay can be provided, thereby obtaining a pulse signal with a wider pulse width. On the other hand, under the condition that the required delay remains the same, it is allowed to reduce the number of delay elements in the local clock circuit or to remove them completely, which will significantly reduce power consumption, component cost and chip area.

FIG. 5 shows a schematic diagram of an improved clock circuit system 1000E according to an embodiment of the present disclosure. The configuration of FIG. 5 is similar to that of FIG. 4D. The difference is that the output of the logic gate element 4230 is not directly provided to the pipeline circuit, but can be provided to the additional circuit elements 4241 and 4242 first. The circuit elements 4241 and 4242 may be inverters or buffers. As described above, the circuit elements 4241 and 4242 as active elements can realize the function of driving signals, thereby maintaining the amplitude of the output signal. The circuit elements 4241 and 4242 may provide respective output signals to a corresponding set of elements (for example, registers). In the case where there are a large number of registers in the pipeline circuit, the configuration of FIG. 5 is advantageous. This is because the output signal provided by a single logic gate element 4230 may not be sufficient to drive a large number of registers, so it is necessary to use active circuit elements 4241 and 4242 to convert the output signal provided by a single logic gate element 4230 into multiple output signals.

It should be noted that although FIG. 5 shows two circuit elements 4241 and 4242 of the local clock circuit 4200, the local clock circuit 4200 may include more such circuit elements without limitation. Also, the local clock circuits 4100 and 4300 may each have similar circuit elements (not shown). Further, one or more local clock circuits of each clock circuit system in FIGS. 4A-4D may also have similar circuit elements.

In FIGS. 4A-4D and FIG. 5, the local clock circuit 4200 is used as an example for discussion, and the local clock circuits 4100 and 4300 adopt the same configuration as the local clock circuit 4200, and the specific details of the local clock circuits 4100 and 4300 are omitted. describe. However, it should be understood that each of the local clock circuits 4100, 4200, 4300 may adopt any of the various exemplary configurations described above without limitation. For example, the local clock circuit 4100 may adopt the configuration described with respect to FIG. 4A, the local clock circuit 4200 may adopt the configuration described with respect to FIG. 4B, and the local clock circuit 4300 may adopt the configuration described with respect to FIG. 4C. Other hybrid configurations are also possible.

According to an embodiment of the present disclosure, the logic gate element used by each local clock circuit may be one selected from an AND gate, a NAND gate, an OR gate, and a NOR gate. Those skilled in the art know that various devices and technologies can be used to implement logic gate elements without limitation.

According to the embodiments of the present disclosure, the type of the selected logic gate element can be determined based on multiple factors, including but not limited to: the circuit between the first port and the second port connected to the two input terminals of the local clock circuit The type (inverter or buffer), number and delay of the component; the type (inverter or buffer) of the delay element on the second signal path of the logic gate element, the number and the delay; what is required The type of pulse signal (high-level pulse trigger or low-level pulse trigger), etc. For example, if the sum of the number of inverters between the first port and the second port and the number of inverters on the second signal path is an odd number, an AND gate or a NAND gate can be selected. If the sum of the numbers is even, you can choose OR gate or NOR gate. A logic gate element can be realized by a combination of several logic gate elements. For example, there can be one inverter between the AND gate and the NAND gate, and the difference between the OR gate and the NOR gate can also be one inverter.

Various clock circuit systems 1000 according to embodiments of the present disclosure may be used in combination with the pipeline structure 3000. Driven by various clock signals provided by the clock circuit system 1000, the pipeline circuits at various levels of the pipeline structure 3000 can perform various data processing tasks. The data processing tasks here include, but are not limited to, data storage, data operations, and so on.

According to an embodiment of the present disclosure, the data processing tasks performed by the pipeline structure 3000 may include various computationally intensive tasks. Computing-intensive tasks require computing hardware to run for a long time, and a large number of pipeline circuits need to be implemented on computing chips to perform parallel computing, so they are sensitive to clock signal performance, power consumption, and chip area. Data processing tasks that can be used to advantage of the present disclosure include, but are not limited to, performing hash algorithm calculations or performing artificial intelligence (AI) calculations.

Hashing algorithm is an algorithm that takes variable-length data as input and produces fixed-length hash value as output. In the hash algorithm, input data of any length is filled so that the length of the filled data is an integer multiple of a certain fixed length (for example, 512 bits), that is, the filled data can be divided into a plurality of fixed lengths. Data block. The content of the stuffing bit includes the bit length information of the original data. Then the hash algorithm will perform calculations on each fixed-length data block, for example, multiple rounds of calculations including data expansion and\or compression. When all data blocks are used, the final fixed-length hash value is obtained.

The hash algorithm executed by the pipeline structure 3000 may be the SHA-256 algorithm. Since 1993, the American Institute of Standards and Technology has designed and released multiple versions of Secure Hash Algorithm SHA (Secure Hash Algorithm). SHA-256 is one of the secure hash algorithms with a hash length of 256 bits. . The SHA-256 algorithm is one of the hash algorithms commonly used in calculations associated with virtual encrypted digital currencies (for example, Bitcoin). For example, Bitcoin is a proof of work (POW) based on the SHA-256 algorithm. The core of using a data processing device (such as a mining machine) for bitcoin mining is to calculate the SHA-256 computing power based on the data processing device to obtain bitcoin rewards.

For hash algorithms that include multiple rounds of operations (for example, the SHA-256 algorithm), a pipeline structure with multiple operation stages can be used to implement high-speed operations. For example, when performing the SHA-256 algorithm, because each 512-bit data block needs to perform 64 rounds of repeated operations, a 64-stage pipeline structure can be used to operate 64 groups of data in parallel.

Figure 6 shows a schematic diagram of a pipeline structure 6000 that can be used to implement the SHA-256 algorithm. The pipeline structure 6000 may be a specific use case of the pipeline structure 3000 described above. In order to implement the SHA-256 algorithm, the pipeline structure 6000 can be a 32-stage, 64-stage, or 128-stage pipeline. As shown in FIG. 6, the t-th operation stage, the t+1-th operation stage, and the t+2th operation stage in the pipeline structure 6000 are divided by dashed lines. Each arithmetic stage can be realized by a corresponding one-stage pipeline circuit. Each operation level can also include operation logic. Each arithmetic stage may also include a plurality of registers A to H for storing intermediate values and a plurality of registers R0 to R15 for storing extended data, respectively. One or more of these registers may be latch type registers. In the process of executing the SHA-256 algorithm, the latch-type register in each pipeline circuit in the pipeline structure 6000 can be triggered based on the corresponding pulse signal provided by the clock circuit system described above, thereby updating the data stored therein . Depending on the type of the latch type register, the pulse signal provided by the clock circuit system may be a high-level pulse signal or a low-level pulse signal. Preferably, in order to be able to trigger multiple registers in each arithmetic stage, these registers can be divided into one or more groups, each of which can be composed of multiple circuit elements as shown in FIG. 5 (ie, circuit element 4241). And 4242) the output signal of the corresponding circuit element is triggered.

The clock circuit system according to the embodiments of the present disclosure may be included in various devices, including but not limited to computing chips, computing power boards, data processing devices (such as digital currency mining machines), and the like. Since the clock circuit system according to the embodiment of the present disclosure is adopted, these devices can obtain multiple clock signals with stable duty ratios at low cost and simple circuit structure, thereby ensuring that these devices perform specific computing tasks. Performance.

FIG. 7 shows a schematic block diagram of a computing chip 7000 according to an embodiment of the present disclosure. The computing chip 7000 may include a clock circuit system 7100, a clock source 7200, and a pipeline structure 7300. The clock circuit system 7100 may be a specific embodiment of the clock circuit system described above (for example, any one of 1000, 1000A, 1000B, 1000C, 1000D, and 1000E). The clock source 7200 may be a specific embodiment of the clock source 2000 described above. The pipeline structure 7300 may be a specific embodiment of the pipeline structure 3000 or 6000 described above. The clock circuitry 7100 can be coupled to the clock source 7200 and the pipeline structure 7300. The clock circuitry 7100 can receive the initial clock signal from the clock source 7200 and generate multiple clock signals accordingly. The multiple clock signals can be provided to the pipeline structure 7300 to perform specific computing tasks. The specific calculation task may be to execute the SHA-256 algorithm, for example. Accordingly, the computing chip 7000 may be configured as a Bitcoin chip. In FIG. 7, the clock source 7200 is shown as a dashed frame, indicating that the clock source 7200 may also be located outside the computing chip 7000.

FIG. 8 shows a schematic block diagram of a computing power board 8000 according to an embodiment of the present disclosure. The computing power board 8000 may include one or more computing chips 8100. The computing chip 8100 may be a specific embodiment of the computing chip 7000. Multiple computing chips 8100 can perform computing tasks in parallel.

FIG. 9 shows a schematic block diagram of a digital currency mining machine 9000 according to an embodiment of the present disclosure. The digital currency mining machine 9000 is an example of a data processing device according to an embodiment of the present disclosure. The digital currency mining machine 9000 can be configured to execute the SHA-256 algorithm to obtain proof of work (POW), and further obtain digital currency based on the proof of work. The digital currency can be Bitcoin. The digital currency mining machine 9000 may include one or more computing power boards 9100. The computing power board 9100 may be a specific embodiment of the computing power board 8000. Multiple computing power boards 9100 can perform computing tasks in parallel, for example, execute the SHA-256 algorithm.

In all the examples shown and discussed herein, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiment may have different values.

In the specification and claims, the words "front", "rear", "top", "bottom", "above", "below", etc., if they exist, are used for descriptive purposes and are not necessarily used To describe the same relative position. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can be used in other orientations different from those shown or otherwise described herein. Operation in orientation.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration" and not as a "model" to be accurately reproduced. Any implementation described exemplarily herein is not necessarily construed as being preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any expressed or implied theory given in the above technical field, background art, summary of the invention, or specific embodiments.

As used herein, the word "substantially" means to include any small changes caused by design or manufacturing defects, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows the difference between the perfect or ideal situation caused by parasitic effects, noise, and other practical considerations that may be present in the actual implementation.

The foregoing description may indicate elements or nodes or features that are "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is electrically, mechanically, logically, or otherwise directly connected (or Direct communication). Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature can be directly or indirectly connected to another element/node/feature mechanically, electrically, logically, or in other ways. Interaction is allowed, even if the two features may not be directly connected. In other words, "coupled" intends to include direct connection and indirect connection of elements or other features, including the connection of one or more intermediate elements.

It should also be understood that, when the term "including/comprising" is used in this text, it indicates that the specified features, wholes, steps, operations, units and/or components exist, but does not exclude the presence or addition of one or more other features, Whole, steps, operations, units and/or components and/or combinations thereof.

Those skilled in the art should realize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and the operations can be executed at least partially overlapping in time. Also, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, changes and replacements are also possible. Therefore, this specification and drawings should be regarded as illustrative rather than restrictive.

Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present disclosure. The various embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (15)

1. A clock circuit system, wherein the clock circuit system includes:

   A master clock circuit, the master clock circuit includes a plurality of cascaded clock driving circuits, each clock driving circuit includes one or more delay elements that delay a clock signal, the master clock circuit is configured to drive the clock signal edge Said multiple clock drive circuits propagate; and

   One or more local clock circuits, each of the one or more local clock circuits is associated with a corresponding clock drive circuit in the master clock circuit, and includes:

   A first input terminal, coupled to the first port of the main clock circuit to draw a first clock signal from the main clock circuit;

   A second input terminal, coupled to the second port of the main clock circuit to draw a second clock signal from the main clock circuit; and

   A logic gate element, coupled to the first input terminal and the second input terminal, and configured to generate a pulse signal based on the first clock signal and the second clock signal;

   Wherein, the second port is located downstream of the first port in the main clock circuit, and the corresponding clock driving circuit of the main clock circuit exists between the first port and the second port At least one delay element in.
2. The clock circuit system of claim 1, wherein the local clock circuit further comprises one or more additional delay elements that delay the second clock signal, and the one or more additional delay elements are provided in the logic Between the gate element and the second input terminal.
3. The clock circuit system according to claim 1, wherein the local clock circuit has one of the following configurations:

   A first configuration, wherein the first port and the second port associated with the local clock circuit are located in the same level of clock driving circuit of the master clock circuit;

   A second configuration, wherein the first port and the second port associated with the local clock circuit are located in two adjacent stages of clock drive circuits of the main clock circuit; or

   A third configuration, wherein there is at least one level of clock driving circuit of the master clock circuit between the first port and the second port associated with the local clock circuit.
4. The clock circuit system of claim 3, wherein the one or more local clock circuits include a first local clock circuit and a second local clock circuit, the first local clock circuit and the second local clock circuit Each has a different configuration among the first configuration, the second configuration, and the third configuration.
5. 3. The clock circuit system according to claim 1, wherein no delay element is provided between the logic gate element and the first input terminal and the second input terminal of the local clock circuit.
6. The clock circuit system of claim 1, wherein the logic gate element is selected from one of an AND gate, a NAND gate, an OR gate, and a NOR gate; and

   The selection of the logic gate element is determined based on at least the following items:

   The type and quantity of the at least one delay element between the first port and the second port;

   The type and number of delay elements between the logic gate element and the second input terminal; and/or

   The type of pulse signal required.
7. The clock circuit system of claim 1, wherein the one or more delay elements include at least one of a buffer and an inverter.
8. The clock circuit system of claim 1, wherein the local clock circuit is coupled to a corresponding one-stage pipeline circuit in a pipeline structure for performing data processing tasks to provide the pulse signal to the corresponding one Stage pipeline circuit.
9. The clock circuit system according to claim 8, wherein the pulse signal is provided to one or more sets of registers in the corresponding one-stage pipeline circuit, and the output terminal of the local clock circuit is connected to the one or more sets of registers. Additional buffers or inverters are arranged between each set of registers in the multiple sets of registers.
10. 9. The clock circuit system of claim 9, wherein the register is a latch-type register, and the latch-type register can be triggered by a high-level pulse or a low-level pulse of the pulse signal.
11. The clock circuit system of claim 8, wherein the data processing task includes executing a hash algorithm or executing artificial intelligence calculations.
12. The clock circuitry of claim 11, wherein the hash algorithm includes a SHA-256 algorithm.
13. A computing chip, wherein the computing chip includes the clock circuit system according to any one of claims 1-12.
14. A computing power board, wherein the computing power board comprises the computing chip according to claim 13.
15. A data processing device, wherein the data processing device comprises the computing power board according to claim 14.

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