CN212515800U

CN212515800U - Clock tree, hash engine, computing chip, force plate and encrypted currency mining machine

Info

Publication number: CN212515800U
Application number: CN202021413218.7U
Authority: CN
Inventors: 薛可; 范志军; 许超; 杨作兴
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2020-07-16
Filing date: 2020-07-16
Publication date: 2021-02-09
Anticipated expiration: 2030-07-16

Abstract

The present disclosure relates to a clock tree, a hash engine, a computing chip, a force plate, and an encrypted currency miner. The hash engine includes: an operation module configured to perform a hash operation on a received data block, the operation module including a plurality of operation stages arranged in a pipeline structure such that a digital signal based on the data block is sequentially transferred along the plurality of operation stages, each operation stage including a plurality of registers and a combinational logic module, an output terminal of a first group of registers being coupled to at least an input terminal of the combinational logic module of a current operation stage, an input terminal of a second group of registers being coupled to an output terminal of the combinational logic module of a previous operation stage; and a clock module configured to provide a clock signal to each of the operation stages, the clock module including a multi-stage clock driving circuit such that the clock signal from the clock source is sequentially transferred along the multi-stage clock driving circuit, wherein a transfer direction of the digital signal is the same as a transfer direction of the clock signal for the first group of registers and the second group of registers.

Description

Clock tree, hash engine, computing chip, force plate and encrypted currency mining machine

Technical Field

The present disclosure relates to circuits for performing hash algorithms, and more particularly to a circuit including a clock tree circuit, a hash engine, a computing chip, a force plate, and a cryptocurrency miner.

Background

The bitcoin system is the block chain system that was first proposed and is currently most widely recognized. One of the primary roles of bitcoin systems is to act as a decentralized public ledger, which can record a variety of financial transactions. This is called "decentralized" because the bitcoins are not issued by a single centralized monetary institution, but are generated by operations based on a particular algorithm. Bitcoin systems use distributed databases of nodes of a computer network to validate and record all transactions and use cryptographic designs to ensure security.

The current bitcoin protocol uses the secure Hash algorithm SHA (secure Hash Algorithm) -256. The SHA series of algorithms are published by the US institute of standards and technology, where SHA-256 is a secure hash algorithm with a hash length of 256 bits.

According to bitcoin protocol, a node that succeeds in determining a workload proof pow (proof of work) of a candidate block has the right to add the block to the blockchain and to generate a new crypto-currency unit as a reward. This process is referred to as "mining" and the nodes that execute the bitcoin algorithm are referred to as mining machines.

If an Application Specific Integrated Circuit (ASIC) is used to perform the mining process, i.e., an ASIC chip is used to perform the SHA-256 algorithm, the key to the design goal is to improve chip size, chip operating speed, and chip power consumption. The size of the chip determines the cost of the chip, the running speed of the chip determines the running speed of the mining machine, namely calculated force, and the power consumption of the chip determines the power consumption degree, namely the mining cost. In practical applications, the most important performance index for measuring the mining machine is the power consumed by a unit computing power, i.e., a power consumption computing power ratio. Therefore, for a bitcoin miner, it is most important to implement the SHA-256 algorithm with a lower power consumption computation ratio.

Therefore, there is a need for a circuit for implementing a hashing algorithm with a lower power consumption computation ratio.

SUMMERY OF THE UTILITY MODEL

According to a first aspect of the present disclosure, there is provided a hash engine comprising: an input module configured to receive a block of data; an arithmetic module configured to perform a hash operation on a received data block, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure such that a digital signal based on the data block passes along the plurality of arithmetic stages in sequence, each of the plurality of arithmetic stages comprising a plurality of registers and a combinational logic module, wherein in each current arithmetic stage, outputs of a first set of registers of the plurality of registers are coupled to at least inputs of the combinational logic module of the current arithmetic stage, and inputs of a second set of registers of the plurality of registers are coupled to outputs of the combinational logic module of a previous arithmetic stage; and a clock module configured to provide a clock signal to each of the plurality of operation stages, the clock module including a multi-stage clock driving circuit such that the clock signal from a clock source is sequentially transferred along the multi-stage clock driving circuit, wherein a transfer direction of the digital signal is the same as a transfer direction of the clock signal for the first group of registers and the second group of registers of the plurality of operation stages.

Further, in each current operation stage, a third group of registers of the plurality of registers has inputs coupled to outputs of corresponding registers in a previous operation stage and has outputs coupled to inputs of corresponding registers in a next operation stage, and wherein a transfer direction of the digital signal is opposite to a transfer direction of the clock signal for the third group of registers of the plurality of operation stages.

A hash engine according to the present disclosure may be used to perform the SHA-256 algorithm.

According to a second aspect of the present disclosure, there is provided a clock tree circuit comprising: a clock source for providing a basic clock signal; and a multi-stage clock driving circuit, wherein a basic clock signal from the clock source is sequentially transferred along the multi-stage clock driving circuit, each stage of the multi-stage clock driving circuit is used for providing a clock signal for each operation stage of a plurality of operation stages, wherein the operation stages are arranged in a pipeline structure to enable a digital signal based on a received data block to be sequentially transferred along the operation stages, each operation stage of the operation stages comprises a plurality of registers and a combinational logic module, wherein in each current operation stage, an output end of a first group of registers in the plurality of registers is at least coupled to an input end of the combinational logic module of the current operation stage, an input end of a second group of registers in the plurality of registers is coupled to an output end of the combinational logic module of a previous operation stage, and an input end of a third group of registers in the plurality of registers is coupled to an input end of a corresponding registered logic module of a previous operation stage An output of the multiplexer and an output of the multiplexer is coupled to an input of a corresponding register in a next operational stage, wherein for each operational stage of the plurality of operational stages the first set of registers and the second set of registers are passed in the same direction as the clock signal, and wherein for the third set of registers of the plurality of operational stages the direction of passage of the digital signal is opposite to the direction of passage of the clock signal.

According to a third aspect of the present disclosure, there is provided a computing chip comprising one or more hash engines as described above.

According to a fourth aspect of the present disclosure, there is provided an computing force plate comprising one or more computing chips as described above.

According to a fifth aspect of the present disclosure, there is provided a cryptocurrency miner including one or more computing plates as described above.

Other characteristic features and advantages of the present disclosure will become apparent from the following description with reference to the accompanying drawings.

Drawings

The drawings are included for illustrative purposes and serve only to provide examples of possible structures and arrangements of the inventive apparatus disclosed herein and methods of applying the same to computing devices. These drawings in no way limit any changes in form and detail that may be made to the embodiments by one skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements.

Fig. 1 is a schematic diagram of a SHA-256 hash engine according to an embodiment of the present disclosure.

FIG. 2A is a schematic diagram showing the driving of registers through a forward clock tree in a pipelined architecture.

FIG. 2B is a schematic diagram showing the driving of registers by an inverted clock tree in a pipelined architecture.

Fig. 3A and 3B are diagrams showing setup and hold times of registers.

Fig. 4 is a schematic diagram illustrating a clock tree structure according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram illustrating a hash engine employing the clock tree structure of fig. 4, according to an embodiment of the present disclosure.

Fig. 6 is a schematic diagram illustrating another hash engine employing the clock tree structure of fig. 4, in accordance with an embodiment of the present disclosure.

Fig. 7 is a schematic diagram illustrating a clock tree structure according to another embodiment of the present disclosure.

Fig. 8 is a schematic diagram illustrating a hash engine employing the clock tree structure of fig. 7, according to an embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the hash engine herein is shown by way of example to illustrate different embodiments of the circuit in the present disclosure and is not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of exemplary ways in which the present disclosure may be practiced and not exhaustive.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

The present disclosure presents a novel clock tree scheme that can be used in any cryptographic algorithm circuit with a pipeline architecture. For convenience of description, the SHA-256 hash algorithm circuit is taken as an example for illustration. It will be appreciated by those skilled in the art that SHA-256 is merely one example to which the clock tree scheme of the present disclosure may be applied, and that the present disclosure may also be applied to other cryptographic algorithm circuits having a pipelined structure.

Reference is now made to fig. 1, which is a schematic illustration of a SHA-256 hash engine according to an embodiment of the present disclosure. Those skilled in the art will appreciate that the following description of SHA-256 is provided for the purpose of more clearly presenting the inventive concepts of the present application and is not intended to be in any way limiting. Reference herein to SHA-256 includes any version of SHA-256 and variations and modifications thereof that are well known.

As shown in fig. 1, the hash engine 10 includes an input module 101, an operation module 102, and a clock module 103. The input module 101 is used to receive data blocks. The operation module 102 may perform a SHA-256 hash operation on the received data block. The clock module 103 is used for providing a required clock signal for the operation module 102.

As shown in fig. 1, the arithmetic module 102 includes a plurality of arithmetic stages arranged in a pipeline structure, a 1 st stage. N may be 32, 64, 128, etc. Each operational stage may include registers A-H and corresponding operational logic, register W₀～W₁₅And corresponding combinational logic and memory for storing the constant K. Register W₀～W₁₅Are often referred to as extension registers because they are configured to extend the input data block. Registers A-H are often referred to as packed registers because they are configured to pack expanded data into hash values.

As shown in fig. 1, in the register W₀～W₁₅In each stage of the register W₁～W₁₅Is supplied to the register W of the next stage₀～W₁₄As an input, the register W₀、W₁、W₉、W₁₄Is supplied as an input to combinational logic, the output of which is supplied to the register W of the next stage₁₅As an input. That is, the register W of each stage_o、W₁、W₉、W₁₄、W₁₅With preceding or current stageThe combination logic operation is related, and the other registers are not related to the combination logic operation of the previous stage or the current stage.

The clock module 103 may provide a clock signal to the operation module 102, and specifically, to each register in the operation module 102. Typically, the clock signal output by clock module 103 is derived from a single clock source. However, in chips like SHA-256, there are a large number of sequential devices such as registers. If a sequential device is directly driven by a single clock source signal, the driving load capability becomes a problem, and the delay caused by the excessively long wiring from the clock source to the register clock terminal becomes excessively large. Therefore, a clock tree architecture is usually adopted to provide clock signals, i.e. a buffer or an inverter is inserted between a clock source and a sequential device to form a clock distribution network. In a pipeline architecture, there are two clock tree structures, a forward clock tree and a reverse clock tree.

FIG. 2A is a schematic diagram showing the driving of registers through a forward clock tree in a pipelined architecture. As shown, each pipeline arithmetic stage 202-1.... 202-N is driven by a clock tree composed of a clock source 200 and a multi-stage clock driving circuit 201-1.... 201-N. Since the direction of the clock signal propagation (left to right) coincides with the data propagation direction of the pipeline (left to right), this clock tree is called a forward clock tree.

FIG. 2B is a schematic diagram showing the driving of registers by an inverted clock tree in a pipelined architecture. As shown, each pipeline arithmetic stage 202-N.... 202-1 is driven by a clock tree composed of a clock source 200 and a multi-stage clock driving circuit 201-1.... 201-N. Since the direction of propagation of the clock signal (from right to left) is opposite to the direction of propagation of the data of the pipeline (from left to right), this clock tree is called an inverted clock tree.

Regardless of the clock tree structure used, the Setup Time (Setup Time) and Hold Time (Hold Time) requirements of the registers should be met. Fig. 3A and 3B are diagrams showing setup and hold times of registers. Establishing a time T_setupRefers to the time that the data must remain stable before the clock edge arrives. If the time of establishment isNot meeting the requirements, then the data cannot be stably driven into the register at this clock edge. Hold time T_holdRefers to the time after which the data must remain stable after the clock edge arrives. If the hold time does not meet the requirements, then the data likewise cannot be stably driven into the register.

This is described in detail as a circuit common to digital circuit designs. As shown in fig. 3A, the circuit includes flip-

flops

301 and 303 and combinational logic 302. The data signal Q1 output by flip-flop 301 is passed through combinational logic 302 to the input of flip-flop 303, and the clock signal CLK controls flip-flop 303 to capture the data signal. In order for the data signal to be properly captured by flip-flop 303, the data signal should precede the clock edge by at least T_setupReaches the input of flip-flop 303 while holding at least T after the clock edge_holdTime of (d).

At the time of satisfying T_setupAnd T_holdThe range of the transmission delay of the intermediate combinational logic circuit can be determined. Assume a clock period of T_clkThe output delay of the flip-flop is T_coDelay of combinational logic is T_comb。

For T_setupThe following requirements are met:

T_clk-T_co-T_comb＞T_setup(formula 1)

Considering the worst case, i.e. the output delay of the flip-flop is the largest, and the delay of the combinational logic circuit is also the largest, the above equation 1 becomes:

T_clk-T_co-max-T_comb-max＞T_setup(formula 2)

For T_holdThe following requirements are met:

T_co+T_comb＞T_hold(formula 3)

In consideration of the worst case where the delay of the output of the flip-flop is minimized and the delay of the combinational logic circuit is also minimized, equation 3 above becomes

T_co-min+T_comb-min＞T_hold(formula 4)

In conjunction with the forward and reverse clock trees of FIGS. 2A and 2B, assume that the delay of each stage of the clock driving circuit is T_clklatencyThe above equations 2 and 4 become the following equations, respectively.

For a forward clock tree:

consider T_setup：

T_clk+T_clklatency-T_co-max-T_comb-maxTsetup (equation 5)

That is to say that the first and second electrodes,

T_clk＞T_setup+T_co-max+T_comb-max-T_clklatency(formula 6)

Consider T_hold：

T_co-min+T_comb-min＞T_hold+T_clklatency(formula 7)

That is to say that the first and second electrodes,

T_co-min+T_comb-min-T_clklatency＞T_hold(formula 8)

For a reverse clock tree:

consider T_setup：

T_clk-T_clklatency-T_co-max-T_comb-max＞T_setup(formula 9)

That is to say that the first and second electrodes,

T_clk＞T_setup+T_co-max+T_comb-max+T_clklatency(formula 10)

Consider T_hold：

T_co-min+T_comb-min＞T_hold-T_clklatency(formula 11)

That is to say that the first and second electrodes,

T_co-min+T_comb-min+T_clklatency＞T_hold(formula 12)

Comparing equation 6 with equation 10, we can see T of the forward clock tree_clkThe frequency of the chip can be faster correspondingly, and higher performance can be achieved.And T of the reverse clock tree_clkIt needs to be larger, i.e. the period is larger, so the frequency of the chip becomes slower and the performance is reduced.

However, comparing equation 8 and equation 12, it can be seen that the hold time of the flip-flop is less easily satisfied when the forward clock tree is used, and the hold time of the flip-flop is more easily satisfied when the reverse clock tree is used. Especially if the delay of the combinational logic between two flip-flops is small or even absent, i.e. T_comb-minAt 0, the hold time of the forward clock tree will be difficult to satisfy.

The synchronous sequential circuit works normally on the premise that the setup time and the hold time of the flip-flop are both satisfied. The retention time is a more important indicator and must be met. If the holding time is not satisfied, the chip cannot work normally. Therefore, in the prior art, a reverse clock tree is typically used to ensure that the hold time T is met_holdAnd (4) requiring. But this sacrifices the frequency of the chip resulting in reduced performance of the chip.

The present disclosure provides a novel clock tree scheme that can satisfy the hold time T_holdThe operating frequency of the chip is required to be increased so as to improve the performance of the chip.

Fig. 4 is a schematic diagram illustrating a clock tree structure according to an embodiment of the present disclosure. As shown in FIG. 4, the clock tree includes a clock source 400, a multi-stage clock driving circuit 401₁......401_M.., the first set of clock buffer circuits 402₁......402_M.., and a second set of clock buffer circuits 406₁...... 406_M....... The ith stage clock driving circuit is used for providing a clock for the ith operation stage of the pipeline. Where i and M are less than the total number of stages N of the pipeline.

Here, the ith operation stage is explained as an example. As shown in FIG. 4, the ith operation stage of the operation module includes a first type register 403_iRegister of the second type 404_iAnd a third type register 407_i. Registers of the first type 403_iIs connected to the combinational logic 405 of the ith operational stage in addition to the inputs of the corresponding registers of the (i + 1) th operational stage_iI.e. the first type register 403_iThe output of (c) needs to participate in the combinational logic operation. Second type of register 404_iIs connected to the combinational logic 405 of the i-1 th operational stage_i-1I.e. the second type register 404_iReceives the output of the combinational logic from the (i-1) th arithmetic stage. Registers of the first type 403_iAnd a second type of register 404_iAre related to combinational logic operations. And a third type register 407_iReceives the output of the corresponding register of the (i-1) th arithmetic stage and provides its output to the corresponding register of the (i + 1) th arithmetic stage, i.e. the third type register 407_iIndependent of the combinational logic operation of the i-1 th or ith arithmetic stage.

It should be noted that only one register of each type is shown here for simplicity of description. It will be understood by those skilled in the art that the number of registers of each type is not limited to one, but may be any number depending on the actual circuit configuration. Taking the SHA-256 circuit shown in FIG. 1 as an example, the first type register 403_iMay comprise W₀、W₁、W₉、W₁₄Register of the second type 404_iMay comprise W₁₅Register of the third type 407_iMay comprise W₂～W₈And W₁₀～W₁₃. It should be noted that such sorting of the registers of the SHA-256 circuit is merely an example, and a person skilled in the art may perform different sorting manners according to actual circumstances, as will be described below.

As shown in FIG. 4, according to an embodiment of the present disclosure, for registers 403 of a first type associated with combinational logic operations_iAnd a second type of register 404_iUsing a forward clock tree structure, i.e. registers 403 of the first type at the i-th arithmetic stage_iAnd a second type of register 404_iIs coupled to the clock buffer circuit 402_iAnd clock buffer circuit 402, and_iis coupled to the clock driving circuit 401_iTo the output terminal of (a).

For a third class of registers not associated with the i-1 st or ith stages of combinatorial logic operationStorage device 407_iUsing a reverse clock tree structure, i.e. registers 407 of the third type in the ith arithmetic stage_iIs coupled to the clock buffer circuit 406_iAnd clock buffer circuit 406_iIs coupled to the corresponding clock buffer circuit 406 of the (i + 1) th operational stage_i+1To the output terminal of (a). The corresponding clock buffer circuit 406_i+1Is also coupled to a corresponding register 407 of the (i + 1) th operational stage_i+1The clock terminal of (1). Corresponding register 407_i+1Register 407 referred to as the ith operation stage_iIs connected to that register 407 of the (i + 1) th operational stage_i+1. Take SHA-256 as an example, such as register W of the ith operation stage₅Is connected to the register W of the (i + 1) th operational stage₄Thus, the register W of the ith operation stage₅Is coupled to its corresponding clock buffer circuit 406_iAnd the clock buffer circuit 406_iIs coupled to the (i + 1) th operational stage for being a register W₄ Clock buffer circuit 406 providing clock signal_i+1To the output terminal of (a).

That is, for the third type of register, the register W of the ith operation stage_kThe input end of the clock buffer circuit for providing clock signals is coupled to the (i + 1) th operational stage for providing the register W_k-1An output of the clock buffer circuit providing a clock signal. And so on until the Mth operation stage, where it is the third type register 407_M Clock buffer circuit 406 providing clock signal_MIs coupled to the mth operational stage as a first type register 403_MAnd a second type of register 404_M Clock buffer circuit 402 for providing clock signals_MTo the output terminal of (a). Taking the SHA-256 circuit shown in FIG. 1 as an example, the register W of the M-1 th operation stage₂The input of the clock buffer circuit providing the clock signal should be coupled to the Mth operational stage for the register W₁An output of a clock buffer circuit providing a clock signal, and W₁Of registers of the first type, i.e. Mth operation stage, for register W₁Input end coupling of clock buffer circuit for providing clock signalTo the clock driving circuit 401_MThen at the Mth arithmetic stage, is register W₁ Clock buffer circuit 402 for providing clock signals_MThe output of (2) is again clocked by a clock buffer circuit 406_MThe latter being input to the M-1 st operational stage as a register W₂A clock buffer circuit for providing a clock signal.

According to the foregoing formula 8 and formula 12, since the first type register 403_iAnd a second type of register 404_iParticipating in combinational logic operations, T_comb-minIs not 0 and the delay time with respect to the clock signal is often large, so that T can be satisfied even if a forward clock tree is used_hold. And not the third type of register 407 of the combinational logic operation_iT can be satisfied due to the adoption of the reverse clock tree_hold. Meanwhile, the clock module integrally adopts a forward clock tree structure, so that the running frequency of the chip can be improved, and the performance of the chip can be improved.

Examples of applications of the above inventive concepts of the present disclosure are described below in conjunction with the circuit configuration of SHA-256.

Fig. 5 is a schematic diagram illustrating a hash engine employing the clock tree structure of fig. 4 in accordance with an embodiment of the present disclosure. Solid arrows in fig. 5 indicate the transfer direction of the clock signal, and dotted arrows indicate the transfer direction of the data. Note that unnecessary illustrations and descriptions are omitted herein to avoid obscuring the subject matter. For example, the hash engine of FIG. 5 omits the compression registers A-H, and only the extension register W is shown₀～W₁₅. Furthermore, for simplicity, fig. 5 shows only data transfer and clock transfer of a part of registers in each operation stage, and data transfer and clock transfer of other registers are omitted. Data transfer and clock transfer for each register in each arithmetic stage are readily contemplated by those skilled in the art in light of the teachings of this disclosure.

As shown in FIG. 5, the hash engine includes a plurality of operation stages, each operation stage including a plurality of registers W₀～W₁₅And are driven by respective clock driving circuits 501. According to the embodiment shown in FIG. 5, the hash engine as a whole employs a forward clockTree structure, and reverse clock tree structure is adopted locally. As previously described, the register W of each operational stage₀、W₁、W₉、W₁₄、W₁₅Is coupled to the master clock tree, while the remaining registers W_k(W₂～W₈And W₁₀～W₁₃) The clock of (1) is from W of the next operation stage_k-1Is transmitted. Fig. 5 omits a clock buffer circuit for convenience of explanation, and only solid arrows indicate transfer paths of clock signals of the registers. It will be appreciated by those skilled in the art and informed by the teachings of the present disclosure that the clock terminal of each register is coupled to the output terminal of the corresponding clock buffer circuit.

Register W for each operation stage₉In other words, it participates in combinational logic operations, thus receiving a clock signal from a forward clock tree, while register W is simultaneously present₉Also needs to be passed to the register W of the next operational stage₈Thus, the register W of the next operation stage₈The clock signal of (2) needs to be transferred to the register W of the current operation stage₉To meet the requirements of the reverse clock tree. Register W₁₄Similarly.

To this end, in the embodiment of FIG. 5, each operation stage is provided with the exception of the first to sixteenth registers W₀～W₁₅Besides, it also includes a seventeenth register W_{9_t}And an eighteenth register W_{14_t}。

Seventeenth register W_{9_t}Is coupled to the tenth register W₉Its output end is coupled to the ninth register W of the next operation stage₈And a clock signal terminal thereof is coupled to an output terminal of the clock buffer circuit for the seventeenth register. The register W for the seventeenth register_{9_t}Is coupled to the ninth register W for the next operational stage₈To the output of the clock buffer circuit. I.e. the seventeenth register W_{9_t}Is clocked by W of the next operational stage₈Is transmitted.

Eighteenth register W_{14_t}Is coupled to the fifteenth register W₁₄Its output end is coupled to the fourteenth register W of the next operation stage₁₃And a clock signal terminal thereof is coupled to an output terminal of the clock buffer circuit for the eighteenth register. The register W for the eighteenth register_{14_t}Is coupled to the fourteenth register W for the next operation stage₁₃To the output of the clock buffer circuit. I.e. the register W_{14_t}Is clocked by the register W of the next operational stage₁₃Is transmitted.

From the perspective of the overall pipeline, the register W of the ith arithmetic stage₀、W₁、W₉、W₁₄、W₁₅Is coupled to the master clock tree. Register W of ith operation stage_{9_t}Is clocked by the register W of the (i + 1) th operational stage₈Is transmitted. Register W of the i +1 th operation stage₈Is clocked by the register W of the (i + 2) th arithmetic stage₇Is transmitted. By analogy, register W of the i +7 th operation stage₂Is clocked by the register W of the (i + 8) th operational stage₁Is transmitted. Register W of ith operation stage₉Delivering a clock to a register W of an i-1 th arithmetic stage₁₀. By analogy, the register W of the i-4 th operation stage₁₃Delivering a clock to a register W of an i-5 th arithmetic stage_{14_t}。

By adding the seventeenth register W configured as above_{9_t}And an eighteenth register W_{14_t}The use of both a forward clock tree and a reverse clock tree for pipeline structures may be implemented to satisfy the T of a register_holdThe operating frequency of the chip is required to be increased so as to improve the performance of the chip.

Fig. 6 is a schematic diagram illustrating another hash engine employing the clock tree structure of fig. 4, in accordance with an embodiment of the present disclosure. It should be noted that the same portions as those in fig. 5 will not be described again, and only the portions different from those in fig. 5 will be described.

The clock edge is delayed by T in reverse at each stage due to the reverse clock tree_clklatencyTherefore, after a certain number of stages, according to equation 9, it may cause a parasitic signalT of memory_setupNot satisfying it. To this end, as shown in FIG. 6, each operation stage except the first to sixteenth registers W₀～W₁₅And a seventeenth register W_{9_t}And an eighteenth register W_{14_t}In addition, a nineteenth register W may be included_{6_t}Circuit arrangement and seventeenth register W_{9_t}And an eighteenth register W_{14_t}Similarly. I.e. the nineteenth register W of each operational stage_{6_t}Is coupled to the seventh register W of the current operational stage₆Its output end is coupled to the sixth register W of the next operation stage₅And its clock signal terminal is coupled to the input terminal for the register W_{6_t}To the output of the clock buffer circuit. The register W_{6_t}Is coupled to the sixth register W for the next operational stage₅To the output of the clock buffer circuit. I.e. the register W_{6_t}Is clocked by the register W of the next operational stage₅Is transmitted.

According to the embodiment shown in fig. 6, the hash engine employs a forward clock tree structure as a whole, and a reverse clock tree structure in part. Divide register W in each operation stage₀、W₁、W₉、W₁₄、W₁₅Is coupled to the outside of the main clock tree, W₆Is also coupled to the master clock tree. And the rest of the registers W_k(W₂～W₅、W₇～W₈And W₁₀～W₁₃) The clock of (1) is from W of the next operation stage_k-1Is transmitted.

From the perspective of the overall pipeline, the register W of the ith arithmetic stage₀、W₁、W₆、W₉、W₁₄、W₁₅Is coupled to the master clock tree. Register W_{6_t}Is clocked by the register W of the (i + 1) th operational stage₅Is transmitted. Register W of the i +1 th operation stage₅Is clocked by the register W of the (i + 2) th arithmetic stage₄Is transmitted. By analogy, register W of the i +4 th operation stage₂Is carried by the (i + 5) th clockRegister W of arithmetic stage₁Is transmitted. Register W of ith operation stage₆Delivering a clock to a register W of an i-1 th arithmetic stage₇. By analogy, the register W of the i-2 arithmetic stage₈Delivering a clock to a register W of an i-3 rd arithmetic stage_{9_t}. Register W of the i-3 rd operation stage₉Delivering a clock to a register W of an i-4 th arithmetic stage₁₀. And so on.

In the embodiment shown in FIG. 6, the nineteenth register W is added_{6_t}Thus from W₁To W_{9_t}The clock path of (2) is divided into two parts, and the clock path of each part is shortened relative to the whole reverse clock path, thereby satisfying the T of the register_setupAnd (4) requiring.

It will be appreciated by those skilled in the art that the specific insertion location of the nineteenth register is not limited to the location shown in FIG. 6, but may be at other locations as long as it is ensured that the T of the register is satisfied_setupThe method is required. The insertion position of the added register is typically chosen from W₁To W_{9_t}At a register in the middle portion of the clock path. For example, W may be₅And W₆Is inserted between W_{5_t}. Insert W_{5_t}Circuit arrangement of time and insertion W as described above_{6_t}The description is omitted here for the similarity.

Fig. 7 is a schematic diagram illustrating a clock tree structure according to another embodiment of the present disclosure. The forward clock tree portion of fig. 7 is the same as that shown in fig. 4 and therefore will not be described again here. Unlike the inverted clock tree portion shown in fig. 4, in the embodiment of fig. 7, the third type of register 407 of the ith operation stage_iBy a corresponding register 407 of the (i + 2) th arithmetic stage_i+2And is supplied to the third type register 407 of the ith operation stage_iIs also supplied to a corresponding third type register 407 of the (i + 1) th operational stage_i+1。

That is, the third type register 407 of the ith operation stage_iIs coupled to the output of the clock buffer circuit 406i, and the clock buffer circuit 406i_iIs coupled to the corresponding clock buffer circuit 406 of the (i + 2) th operational stage_i+2To the output terminal of (a). The corresponding clock buffer circuit 406_i+2Is also coupled to a corresponding register 407 of the (i + 2) th operational stage_i+2The clock terminal of (1). At the same time, the corresponding register 407 of the (i + 1) th operation stage_i+1Is also coupled to the clock buffer circuit 406_iTo the output terminal of (a).

As previously described with reference to FIG. 4, the corresponding register 407 of the (i + 1) th operational stage_i+1And a corresponding register 407 of the (i + 2) th operation stage_i+2Register 407 referred to as the ith operation stage_iTo which register 407 of the (i + 1) th arithmetic stage the output signal of (b) is passed_i+1And the register 407 of the (i + 2) th operation stage_i+2. Take SHA-256 as an example, such as register W of the ith operation stage₅Is passed to the register W of the (i + 1) th operation stage₄Register W of the i +1 th operation stage₄Is again passed to the register W of the (i + 2) th arithmetic stage₃Thus, the register W of the ith operation stage₅Is coupled to its corresponding clock buffer circuit 406_iAnd register W of the (i + 1) th operation stage₄Is also coupled to the clock buffer circuit 406_iAnd the clock buffer circuit 406_iIs coupled to the (i + 2) th operational stage for being a register W₃ Clock buffer circuit 406 providing clock signal_i+2To the output terminal of (a).

That is, the register W of the ith operation stage_kThe input end of the clock buffer circuit for providing clock signals is coupled to the (i + 2) th arithmetic stage and used for providing the register W_k-2An output of the clock buffer circuit providing a clock signal. And so on until the Mth operation stage, where it is the third type register 407_M Clock buffer circuit 406 providing clock signal_MIs coupled to the mth operational stage as a first type register 403_MAnd a second type of register 404_M Clock buffer circuit 402 for providing clock signals_MTo the output terminal of (a).

For example, SHA-256 is taken as an example of the register of the M-2 operation stageW₃The input of the clock buffer circuit providing the clock signal should be coupled to the Mth operational stage for the register W₁An output of a clock buffer circuit providing a clock signal, and W₁Of registers of the first type, i.e. Mth operation stage, for register W₁ Clock buffer circuit 402 for providing clock signals_MIs coupled to the clock driving circuit 401_MThen at the Mth arithmetic stage, is register W₁ Clock buffer circuit 402 for providing clock signals_MThe output of (2) is again clocked by a clock buffer circuit 406_MThe latter being input to the M-2 th arithmetic stage as a register W₃A clock buffer circuit for providing a clock signal. This will be described in detail below with reference to fig. 8.

In the same way, the clock module in the embodiment adopts the forward clock tree structure as a whole, so that the operating frequency of the chip can be improved, and the performance of the chip can be improved. Meanwhile, the reverse clock tree is adopted for the third kind of registers which do not participate in combinational logic operation, so that T can be met_holdAnd (4) requiring.

An application example of the clock tree structure of fig. 7 is described below in conjunction with the circuit structure of SHA-256.

Fig. 8 is a schematic diagram illustrating a hash engine employing the clock tree structure of fig. 7, according to an embodiment of the present disclosure. Also, solid arrows in fig. 8 indicate the transfer direction of the clock signal, and broken arrows indicate the transfer direction of the data. Furthermore, for simplicity, fig. 8 shows only data transfer and clock transfer of a part of registers in each operation stage, and data transfer and clock transfer of other registers are omitted. Data transfer and clock transfer for each register in each arithmetic stage will be readily apparent to those skilled in the art from the disclosure of fig. 8. For the same parts as fig. 5 and 6, detailed description will be omitted here.

As shown in FIG. 8, the hash engine includes a plurality of operation stages, each operation stage including a plurality of registers W₀～W₁₅. Furthermore, similar to the embodiment of FIG. 5, each arithmetic stage further includes a seventeenth register W_{9_t}And an eighteenth register W_{14_t}. These postsThe latches are driven by respective clock driving circuits 501. Eighteenth register W_{14_t}The configuration of (a) is the same as that of fig. 5. Seventeenth register W_{9_t}Is different from that of fig. 5.

According to the embodiment shown in fig. 8, the hash engine employs a forward clock tree structure as a whole, and a reverse clock tree structure in part. As previously described, the register W of each operational stage₀、W₁、W₉、W₁₄、W₁₅Is coupled to a master clock tree, register W₉To register W_{14_t}The clock transfer of (2) is the same as that of FIG. 5, the k-th register W_k-1(W₃、W₅、W₇) The clock of (1) is from W of the next operation stage_k-3Is transferred by the clock of (1), register W_k-2(W₂、W₄、W₆) Clock and register W of the previous operation stage_k-1The same clock. k is an even number and is more than or equal to 3 and less than or equal to 8. Register W₈Clock and register W of the previous operation stage_{9_t}The same clock.

From the perspective of the overall pipeline, the register W of the ith arithmetic stage_{9_t}Is coupled to register W₉Its output end is coupled to the ninth register W of the next operation stage₈With a clock signal terminal coupled to the output of the clock buffer circuit for the seventeenth register. The register W for the seventeenth register_{9_t}Is coupled to the eighth register W for the (i + 2) th operational stage₇To the output of the clock buffer circuit. That is, the register W of the ith operation stage_{9_t}By the register W of the (i + 2) th operation stage₇Is transmitted. Register W of the i +2 th operation stage₇Is clocked by the register W of the (i + 4) th operational stage₅Is transmitted. By analogy, register W of the i +6 th operation stage₃Is clocked by the register W of the (i + 8) th operational stage₁Is transmitted.

At the same time, register W of the i +1 th operation stage₈Is also coupled to a seventeenth register W for the ith arithmetic stage_{9_t}When (2) is in contact withAn output terminal of the clock buffer circuit. That is, the register W of the (i + 1) th operation stage₈Clock of and register W of the ith operation stage_{9_t}The same clock. Register W of the i +3 th operation stage₆Clock of (2) and register W of the (i + 2) th operation stage₇The same clock. By analogy, register W of the i +7 th operation stage₂Clock of (2) and register W of the (i + 6) th operation stage₃The same clock.

The embodiment of FIG. 8 satisfies the T of the register_holdAt the same time of requirement, because of the secondary W₁To W_{9_t}The number of stages of the reverse clock path is reduced by nearly half, so that the T of the register can be satisfied as well_setupAnd (4) requiring. Compared to the embodiment of fig. 6, the embodiment of fig. 8 does not require additional primary registers, so that the number of registers can be further reduced.

In embodiments according to the present disclosure, the aforementioned registers may include edge triggered registers, such as rising edge triggered registers and/or falling edge triggered registers. The register may comprise D flip-flops (DFFs) and/or latches (latches), which may for example be latches employing a pulse type clock signal.

According to an embodiment of the present disclosure, each of the aforementioned multi-stage clock driving circuits may include an odd number of inverters. For example, each stage of the clock driving circuit may include an inverter.

According to an embodiment of the present disclosure, a clock buffering circuit for a register employing a forward clock tree includes two clock buffers, and a clock buffering circuit for a register employing a backward clock tree includes one clock buffer.

Those skilled in the art will appreciate that while the concepts of the present disclosure have been described above in connection with one circuit configuration of SHA-256, the circuit configuration is not intended to constitute any limitation on the concepts of the present disclosure. The disclosed concept can be applied to any version of SHA-256 and variations and modifications thereof that are known and known. Even further, the disclosed concept can be applied in any computational circuit having a pipeline structure and including sequential devices.

According to embodiments of the present disclosure, the hash engine as described above may be implemented as a computing chip.

Those skilled in the art will appreciate that circuits and/or chips according to the present disclosure may be implemented in Hardware Description Languages (HDL) such as Verilog or VHDL. HDL descriptions can be synthesized for a library of cells designed for a given integrated circuit fabrication technology and can be modified for timing, power, and other reasons to obtain a final design database, which can be transferred to a factory for the production of integrated circuits by a semiconductor manufacturing system. Semiconductor manufacturing systems may produce integrated circuits by depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or modifying the dielectric constant with ultraviolet processing), and so forth. The integrated circuit may include transistors and may also include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between the transistors and the circuit elements.

According to an embodiment of the present disclosure, a computing chip as described above may be included in a force computing pad. In particular, the computing pad may include one or more computing chips. Multiple compute chips may perform computational tasks in parallel.

According to embodiments of the present disclosure, a computing force plate as described above may be included in a computing device, preferably for performing cryptographic currency mining. For example, the computing device may be a bitcoin miner. In particular, the cryptocurrency miner may include one or more computing plates. Multiple computing boards may perform computing tasks in parallel, such as executing the SHA-256 algorithm.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It will be further understood that the terms "comprises/comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.

While some specific embodiments of the present disclosure have been shown in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are intended to be illustrative only and are not limiting upon the scope of the present disclosure. It will be appreciated by those skilled in the art that the above-described embodiments may be modified without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A hash engine, the hash engine comprising:

an input module configured to receive a block of data;

an arithmetic module configured to perform a hash operation on a received data block, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure such that a digital signal based on the data block passes along the plurality of arithmetic stages in sequence, each of the plurality of arithmetic stages comprising a plurality of registers and a combinational logic module, wherein in each current arithmetic stage, outputs of a first set of registers of the plurality of registers are coupled to at least inputs of the combinational logic module of the current arithmetic stage, and inputs of a second set of registers of the plurality of registers are coupled to outputs of the combinational logic module of a previous arithmetic stage; and

a clock module configured to provide a clock signal to each of the plurality of operational stages, the clock module including a multi-stage clock driving circuit such that a clock signal from a clock source is sequentially passed along the multi-stage clock driving circuit, wherein a direction of passage of the digital signal is the same as a direction of passage of the clock signal for the first set of registers and the second set of registers of the plurality of operational stages.

2. The hash engine of claim 1, wherein in each current arithmetic stage, a third set of registers of the plurality of registers have inputs coupled to outputs of corresponding registers in a previous arithmetic stage and have outputs coupled to inputs of corresponding registers in a next arithmetic stage, and wherein for the third set of registers of the plurality of arithmetic stages, a direction of propagation of the digital signal is opposite to a direction of propagation of the clock signal.

3. The hash engine of claim 2, wherein the clock module further comprises a clock buffer circuit for each register of the plurality of registers, a clock signal terminal of each register coupled to an output terminal of the clock buffer circuit for each register, and wherein

An input of the clock buffer circuit for each register of the first and second sets of registers for each current operational stage is coupled to an output of the clock driver circuit for the current operational stage.

4. The hash engine of claim 3, wherein the plurality of registers of each current operational stage further comprises one or more additional registers, an input of one of the one or more additional registers being coupled to an output of a particular register of the first set of registers of the current operational stage, an output thereof being coupled to an input of a register of a next operational stage corresponding to the particular register, and a clock signal terminal thereof being coupled to an output of a clock buffer circuit for the one additional register.

5. The hash engine of claim 4, in which the hash engine is configured to perform the SHA-256 algorithm, and the plurality of registers of each current operation stage comprise at least first to sixteenth registers (W)₀......W₁₅) The first set of registers includes first, second, tenth and fifteenth registers (W)₀、W₁、W₉、W₁₄) And said second set of registers comprises a sixteenth register (W)₁₅)，

The one or more attachmentsThe add register comprises a seventeenth register (W)_{9_t}) And an eighteenth register (W)_{14_t}) Wherein:

seventeenth register (W)_{9_t}) Is coupled to the tenth register (W) of the current operational stage₉) Its output terminal is coupled to the ninth register (W) of the next operation stage₈) And its clock signal end is coupled to the output of the clock buffer circuit for the seventeenth register, an

Eighteenth register (W)_{14_t}) Is coupled to the fifteenth register (W) of the current operational stage₁₄) Its output end is coupled to the fourteenth register (W) of the next operation stage₁₃) And a clock signal terminal thereof is coupled to an output terminal of the clock buffer circuit for the eighteenth register.

6. The hash engine of claim 5, in which the third set of registers comprises third to ninth registers (Wt)₂......W₈) And eleventh to fourteenth registers (W)₁₀......W₁₃)。

7. Hash engine as claimed in claim 6, characterized in that the third to ninth register (W) for each arithmetic stage₂......W₈) For the kth register (W)_k-1) Is coupled to the (k-1) th register (W) for the next operational stage_k-2) Wherein k is an integer and 3 is equal to or greater than k and equal to or less than 9, and wherein

Said for the seventeenth register (W)_{9_t}) Is coupled to a ninth register (W) for a next operation stage₈) To the output of the clock buffer circuit.

8. Hash engine as claimed in claim 6, characterized in that the third to eighth register (W) for each arithmetic stage₂......W₇) For the kth register (W)_k-1) Clock buffer ofThe input of the flushing circuit is coupled to the (k-2) th register (W) for the next operational stage_k-3) The k-1 th register (W) of each operation stage_k-2) Is coupled to the k-th register (W) for the previous operation stage_k-1) Wherein k is an even number and is more than or equal to 3 and less than or equal to 8,

for the seventeenth register (W)_{9_t}) Is coupled to an eighth register (W) for the next operational stage₇) And an output terminal of the clock buffer circuit, and

ninth register of each operation stage (W)₈) Is coupled to a seventeenth register (W) for a previous operation stage_{9_t}) To the output of the clock buffer circuit.

9. The hash engine of claim 5, in which the third set of registers comprises third to sixth registers (Wo)₂......W₅) Eighth to ninth registers (W)₇、W₈) And eleventh to fourteenth registers (W)₁₀......W₁₃)，

The one or more additional registers further include a nineteenth register (W)_{6_t}) Having its input coupled to the seventh register (W) of the current operational stage₆) Its output terminal is coupled to the sixth register (W) of the next operation stage₅) And its clock signal end is coupled to the output of the clock buffer circuit for the nineteenth register (W)_{6_t}) Is coupled to a sixth register (W) for the next operational stage₅) At the output of the clock buffer circuit of (a),

seventh register (W) for each current operation stage₆) Is coupled to the output of the clock driving circuit for the current operational stage, and wherein

The third to sixth registers (W) for each current operation stage₂......W₅) And eighth to ninth registersDevice (W)₇、W₈) For the kth register (W)_k-1) Is coupled to the (k-1) th register (W) for the next operational stage_k-2) K is an integer and is more than or equal to 3 and less than or equal to 6 or more than or equal to 8 and less than or equal to 9.

10. The hash engine of claim 5, in which the third set of registers comprises third to fifth registers (Wo)₂......W₄) Seventh to ninth registers (W)₆......W₈) And eleventh to fourteenth registers (W)₁₀......W₁₃)，

The one or more additional registers further include a twentieth register (W)_{5_t}) With its input coupled to the sixth register (W) of the current operational stage₅) Its output terminal is coupled to the fifth register (W) of the next operation stage₄) And its clock signal end is coupled to the output of the clock buffer circuit for the twentieth register (W)_{5_t}) Is coupled to a fifth register (W) for the next operational stage₄) At the output of the clock buffer circuit of (a),

sixth register (W) for each current operation stage₅) Is coupled to the output of the clock driving circuit for the current operational stage, and wherein

The third to fifth registers (W) for each operation stage₂......W₄) And seventh to ninth registers (W)₆......W₈) For the kth register (W)_k-1) Is coupled to the (k-1) th register (W) for the next operational stage_k-2) K is an integer and is more than or equal to 3 and less than or equal to 5 or more than or equal to 7 and less than or equal to 9.

11. Hash engine according to one of claims 6 to 10, characterized in that the eleventh to fourteenth register (W) for each arithmetic stage₁₀......W₁₃) For the jth register (W)_j-1) Is coupled to the j-1 th register (W) for the next operational stage_j-2) Wherein j is an integer and j is 11. ltoreq. j.ltoreq.14, and wherein

Said for eighteenth register (W)_{14_t}) Is coupled to a fourteenth register (W) for the next operational stage₁₃) To the output of the clock buffer circuit.

12. The hash engine of claim 3, in which each stage of the multi-stage clock driving circuit comprises an odd number of inverters.

13. The hash engine of claim 3, wherein the clock buffer circuitry for each register of the first set of registers and the second set of registers comprises two clock buffers, and the clock buffer circuitry for each register of the third set of registers comprises one clock buffer.

14. A clock tree, the clock tree comprising:

a clock source for providing a basic clock signal; and

a multi-stage clock driving circuit along which a basic clock signal from the clock source is sequentially transferred, each stage of the multi-stage clock driving circuit for providing a clock signal for each of a plurality of operation stages,

wherein the plurality of operational stages are arranged in a pipeline structure such that digital signals based on received data blocks are sequentially passed along the plurality of operational stages, each of the plurality of operational stages comprising a plurality of registers and a combinational logic module, wherein in each current operational stage, outputs of a first group of registers of the plurality of registers are coupled to at least an input of the combinational logic module of the current operational stage, inputs of a second group of registers of the plurality of registers are coupled to an output of the combinational logic module of a previous operational stage, and inputs of a third group of registers of the plurality of registers are coupled to outputs of respective registers of the previous operational stage and outputs thereof are coupled to inputs of respective registers of a next operational stage,

wherein a transfer direction of the digital signal is the same as a transfer direction of the clock signal for the first and second sets of registers of the plurality of operation stages, an

Wherein a transfer direction of the digital signal is opposite to a transfer direction of the clock signal for the third set of registers of the plurality of arithmetic stages.

15. A computing chip comprising one or more hash engines as claimed in any of claims 1 to 13.

16. An algorithm board comprising one or more computing chips as claimed in claim 15.

17. A cryptocurrency miner, comprising one or more force plates as claimed in claim 16.