CN212515799U - Clock tree, hash engine, computing chip, force plate and encrypted currency mining machine - Google Patents

Abstract

The present disclosure relates to a clock tree, a hash engine, a computing chip, a force plate, and an encrypted currency miner. The hash engine includes: an input module configured to receive a block of data; an arithmetic module configured to perform a hash operation on a received data block, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure such that a digital signal based on the data block passes along the plurality of arithmetic stages in sequence, each of the plurality of arithmetic stages comprising a plurality of registers and a combinational logic module; and a clock module configured to provide a clock signal to each of the plurality of operation stages, the clock module including a multi-stage clock driving circuit to cause a clock signal from a clock source to sequentially pass along the multi-stage clock driving circuit, wherein a passing direction of the digital signal is the same as a passing direction of the clock signal for the plurality of registers of each of the plurality of operation stages.

Description

Clock tree, hash engine, computing chip, force plate and encrypted currency mining machine

Technical Field

The present disclosure relates to circuits for performing hash algorithms, and more particularly to a circuit including a clock tree circuit, a hash engine, a computing chip, a force plate, and a cryptocurrency miner.

Background

The bitcoin system is the block chain system that was first proposed and is currently most widely recognized. One of the primary roles of bitcoin systems is to act as a decentralized public ledger, which can record a variety of financial transactions. This is called "decentralized" because the bitcoins are not issued by a single centralized monetary institution, but are generated by operations based on a particular algorithm. Bitcoin systems use distributed databases of nodes of a computer network to validate and record all transactions and use cryptographic designs to ensure security.

The current bitcoin protocol uses the secure Hash algorithm SHA (secure Hash Algorithm) -256. The SHA series of algorithms are published by the US institute of standards and technology, where SHA-256 is a secure hash algorithm with a hash length of 256 bits.

According to bitcoin protocol, a node that succeeds in determining a workload proof pow (proof of work) of a candidate block has the right to add the block to the blockchain and to generate a new crypto-currency unit as a reward. This process is referred to as "mining" and the nodes that execute the bitcoin algorithm are referred to as mining machines.

If an Application Specific Integrated Circuit (ASIC) is used to perform the mining process, i.e., an ASIC chip is used to perform the SHA-256 algorithm, the key to the design goal is to improve chip size, chip operating speed, and chip power consumption. The size of the chip determines the cost of the chip, the running speed of the chip determines the running speed of the mining machine, namely calculated force, and the power consumption of the chip determines the power consumption degree, namely the mining cost. In practical applications, the most important performance index for measuring the mining machine is the power consumed by a unit computing power, i.e., a power consumption computing power ratio. Therefore, for a bitcoin miner, it is most important to implement the SHA-256 algorithm with a lower power consumption computation ratio.

Therefore, there is a need for a circuit for implementing a hashing algorithm with a lower power consumption computation ratio.

SUMMERY OF THE UTILITY MODEL

According to a first aspect of the present disclosure, there is provided a hash engine comprising: an input module configured to receive a block of data; an arithmetic module configured to perform a hash operation on a received data block, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure such that a digital signal based on the data block passes along the plurality of arithmetic stages in sequence, each of the plurality of arithmetic stages comprising a plurality of registers and a combinational logic module; and a clock module configured to provide a clock signal to each of the plurality of operation stages, the clock module including a multi-stage clock driving circuit to cause a clock signal from a clock source to sequentially pass along the multi-stage clock driving circuit, wherein a passing direction of the digital signal is the same as a passing direction of the clock signal for the plurality of registers of each of the plurality of operation stages.

Further, in each current operational stage, an output of each register of a first set of registers of the plurality of registers is coupled to at least an input of the combinational logic module of the current operational stage, an input of each register of a second set of registers of the plurality of registers is coupled to an output of the combinational logic module of the previous operational stage, and an input of each register of a third set of registers of the plurality of registers is coupled to an output of a corresponding register of the previous operational stage and an output thereof is coupled to an input of a corresponding register of the next operational stage.

The clock module further includes a clock buffer circuit for each of the plurality of registers, a clock signal terminal of each register being coupled to an output terminal of the corresponding clock buffer circuit, an input terminal of the clock buffer circuit for each of the second set of registers of each current operational stage and the first set of registers being coupled to an output terminal of the clock driving circuit for the current operational stage, and a clock signal terminal of each of the second set of registers of each current operational stage and a clock signal terminal of a corresponding register of a previous operational stage being coupled to an output terminal of the same clock buffer circuit.

The clock signal terminal of each register in the first part of registers in the third group of registers of each current operation stage and the clock signal terminal of the corresponding register in the previous operation stage are coupled to the output terminal of the same clock buffer circuit, and the input terminal of the clock buffer circuit for each register in the second part of registers in the third group of registers of each current operation stage is coupled to the output terminal of the clock buffer circuit for the corresponding register of the previous n operation stages, where n is an integer and 2 ≦ n ≦ 4.

The plurality of registers of each current operational stage further includes one or more additional registers, an output of one of the one or more additional registers being coupled to an input of a particular register of the first set of registers of the current operational stage, an input thereof being coupled to an output of a corresponding register of a previous operational stage corresponding to the particular register, and a clock signal terminal thereof being coupled to an output of a clock buffer circuit for the corresponding register of the previous operational stage corresponding to the particular register.

A hash engine according to the present disclosure may be used to perform the SHA-256 algorithm.

According to a second aspect of the present disclosure, there is provided a clock tree circuit comprising: a clock source for providing a basic clock signal; and a multi-stage clock driving circuit along which a basic clock signal from the clock source is sequentially transferred, each stage of the multi-stage clock driving circuit for providing a clock signal for each of a plurality of operation stages arranged in a pipeline structure such that a digital signal based on a received data block is sequentially transferred along the plurality of operation stages, each of the plurality of operation stages including a plurality of registers and a combinational logic block; and a plurality of clock buffer circuits for receiving signals from the multi-stage clock driving circuit and providing a clock signal to each of the plurality of registers, wherein a clock signal terminal of each register is coupled to an output terminal of the corresponding clock buffer circuit, wherein for the plurality of registers of each of the plurality of operation stages, a transfer direction of the digital signal is the same as a transfer direction of the clock signal, wherein in each current operation stage, an output terminal of each register of a first group of the plurality of registers is coupled to at least an input terminal of a combinational logic block of the current operation stage, an input terminal of each register of a second group of the plurality of registers is coupled to an output terminal of a combinational logic block of a previous operation stage, and an input terminal of each register of a third group of the plurality of registers is coupled to an output terminal of a corresponding register of the previous operation stage And having its output coupled to the input of a corresponding register in a next operational stage, wherein the input of the clock buffer circuit for each of the second set of registers of each current operational stage and the first portion of registers of the first set of registers is coupled to the output of the clock driver circuit for the current operational stage, the clock signal terminal of each of the second portion of registers of the first set of registers of each current operational stage and the clock signal terminal of a corresponding register of a previous operational stage are coupled to the output of the same clock buffer circuit, the clock signal terminal of each of the first portion of registers of the third set of registers of each current operational stage and the clock signal terminal of a corresponding register of a previous operational stage are coupled to the output of the same clock buffer circuit, and the clock signal terminal for each of the second portion of registers of the third set of registers of each current operational stage is coupled to the input of the clock buffer circuit, and the clock signal terminal for each of the second portion of registers of the third set of registers of each current operational The input terminal of the clock buffer circuit is coupled to the output terminal of the clock buffer circuit for the corresponding register of the first n operational stages, wherein i is an integer and n is greater than or equal to 2 and less than or equal to 4.

According to a third aspect of the present disclosure, there is provided a computing chip comprising one or more hash engines as described above.

According to a fourth aspect of the present disclosure, there is provided an computing force plate comprising one or more computing chips as described above.

According to a fifth aspect of the present disclosure, there is provided a cryptocurrency miner including one or more computing plates as described above.

Other characteristic features and advantages of the present disclosure will become apparent from the following description with reference to the accompanying drawings.

Drawings

The drawings are included for illustrative purposes and serve only to provide examples of possible structures and arrangements of the inventive apparatus disclosed herein and methods of applying the same to computing devices. These drawings in no way limit any changes in form and detail that may be made to the embodiments by one skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements.

Fig. 1 is a schematic diagram of a SHA-256 hash engine according to an embodiment of the present disclosure.

FIG. 2A is a schematic diagram showing the driving of registers through a forward clock tree in a pipelined architecture.

FIG. 2B is a schematic diagram showing the driving of registers by an inverted clock tree in a pipelined architecture.

Fig. 3A and 3B are diagrams showing setup and hold times of registers.

Fig. 4 is a schematic diagram illustrating a clock tree structure according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram illustrating a hash engine employing the clock tree structure of fig. 4, according to an embodiment of the present disclosure.

FIG. 6 is a diagram illustrating an exemplary clock path of the hash engine of FIG. 5.

Fig. 7 is a schematic diagram illustrating an exemplary clock path of a hash engine employing the clock tree structure of fig. 4, according to another embodiment of the present disclosure.

FIG. 8 is a diagram illustrating an exemplary clock path of a hash engine employing the clock tree structure of FIG. 4 according to yet another embodiment of the present disclosure.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the hash engine herein is shown by way of example to illustrate different embodiments of the circuit in the present disclosure and is not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of exemplary ways in which the present disclosure may be practiced and not exhaustive.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

The present disclosure presents a novel clock tree scheme that can be used in any cryptographic algorithm circuit with a pipeline architecture. For convenience of description, the SHA-256 hash algorithm circuit is taken as an example for illustration. It will be appreciated by those skilled in the art that SHA-256 is merely one example to which the clock tree scheme of the present disclosure may be applied, and that the present disclosure may also be applied to other cryptographic algorithm circuits having a pipelined structure.

Reference is now made to fig. 1, which is a schematic illustration of a SHA-256 hash engine according to an embodiment of the present disclosure. Those skilled in the art will appreciate that the following description of SHA-256 is provided for the purpose of more clearly presenting the inventive concepts of the present application and is not intended to be in any way limiting. Reference herein to SHA-256 includes any version of SHA-256 and variations and modifications thereof that are well known.

As shown in fig. 1, the hash engine 10 includes an input module 101, an operation module 102, and a clock module 103. The input module 101 is used to receive data blocks. The operation module 102 may perform a SHA-256 hash operation on the received data block. The clock module 103 is used for providing a required clock signal for the operation module 102.

As shown in fig. 1, the arithmetic module 102 includes a plurality of arithmetic stages arranged in a pipeline structure, a 1 st stage. N may be 32, 64, 128, etc. Each operational stage may include registers A-H and corresponding operational logic, register W₀～W₁₅And corresponding combinational logic and memory for storing the constant K. Register with a plurality of registersW₀～W₁₅Are often referred to as extension registers because they are configured to extend the input data block. Registers A-H are often referred to as packed registers because they are configured to pack expanded data into hash values.

As shown in fig. 1, in the register W₀～W₁₅In each stage of the register W₁～W₁₅Is supplied to the register W of the next stage₀～W₁₄As an input, the register W₀、W₁、W₉、W₁₄Is supplied as an input to combinational logic, the output of which is supplied to the register W of the next stage₁₅As an input. That is, the register W of each stage₀、W₁、W₉、W₁₄、W₁₅The other registers are independent of the combinational logic operation of the previous stage or the current stage.

The clock module 103 may provide a clock signal to the operation module 102, and specifically, to each register in the operation module 102. Typically, the clock signal output by clock module 103 is derived from a single clock source. However, in chips like SHA-256, there are a large number of sequential devices such as registers. If a sequential device is directly driven by a single clock source signal, the driving load capability becomes a problem, and the delay caused by the excessively long wiring from the clock source to the register clock terminal becomes excessively large. Therefore, a clock tree architecture is usually adopted to provide clock signals, i.e. a buffer or an inverter is inserted between a clock source and a sequential device to form a clock distribution network. In a pipeline architecture, there are two clock tree structures, a forward clock tree and a reverse clock tree.

FIG. 2A is a schematic diagram showing the driving of registers through a forward clock tree in a pipelined architecture. As shown, each pipeline arithmetic stage 202-1.... 202-N is driven by a clock tree composed of a clock source 200 and a multi-stage clock driving circuit 201-1.... 201-N. Since the direction of the clock signal propagation (left to right) coincides with the data propagation direction of the pipeline (left to right), this clock tree is called a forward clock tree.

FIG. 2B is a schematic diagram showing the driving of registers by an inverted clock tree in a pipelined architecture. As shown, each pipeline arithmetic stage 202-N.... 202-1 is driven by a clock tree composed of a clock source 200 and a multi-stage clock driving circuit 201-1.... 201-N. Since the direction of propagation of the clock signal (from right to left) is opposite to the direction of propagation of the data of the pipeline (from left to right), this clock tree is called an inverted clock tree.

Regardless of the clock tree structure used, the Setup Time (Setup Time) and Hold Time (Hold Time) requirements of the registers should be met. Fig. 3A and 3B are diagrams showing setup and hold times of registers. Establishing a time T_setupRefers to the time that the data must remain stable before the clock edge arrives. If the setup time does not meet the requirements, then the data cannot be stably driven into the register at this clock edge. Hold time T_holdRefers to the time after which the data must remain stable after the clock edge arrives. If the hold time does not meet the requirements, then the data likewise cannot be stably driven into the register.

This is described in detail as a circuit common to digital circuit designs. As shown in fig. 3A, the circuit includes flip- flops 301 and 303 and combinational logic 302. The data signal Q1 output by flip-flop 301 is passed through combinational logic 302 to the input of flip-flop 303, and the clock signal CLK controls flip-flop 303 to capture the data signal. In order for the data signal to be properly captured by flip-flop 303, the data signal should precede the clock edge by at least T_setupReaches the input of flip-flop 303 while holding at least T after the clock edge_holdTime of (d).

At the time of satisfying T_setupAnd T_holdThe range of the transmission delay of the intermediate combinational logic circuit can be determined. Assume a clock period of T_clkThe output delay of the flip-flop is T_coDelay of combinational logic is T_comb。

For T_setupThe following requirements are met:

T_clk-T_co-T_comb＞T_setup(formula 1)

Considering the worst case, i.e. the output delay of the flip-flop is the largest, and the delay of the combinational logic circuit is also the largest, the above equation 1 becomes:

T_clk-T_co-max-T_comb-max＞T_setup(formula 2)

For T_holdThe following requirements are met:

T_co+T_comb＞T_hold(formula 3)

In consideration of the worst case where the delay of the output of the flip-flop is minimized and the delay of the combinational logic circuit is also minimized, equation 3 above becomes

T_co-min+T_comb-min＞T_hold(formula 4)

In conjunction with the forward and reverse clock trees of FIGS. 2A and 2B, assume that the delay of each stage of the clock driving circuit is T_clklatencyThe above equations 2 and 4 become the following equations, respectively.

For a forward clock tree:

consider T_setup：

T_clk+T_clklatency-T_co-max-T_comb-max＞T_setup(formula 5)

That is to say that the first and second electrodes,

T_clk＞T_setup+T_co-max+T_comb-max-T_clklatency(formula 6)

Consider T_hold：

T_co-min+T_comb-min＞T_hold+T_clklatency(formula 7)

That is to say that the first and second electrodes,

T_co-min+T_comb-min-T_clklatency＞T_hold(formula 8)

For a reverse clock tree:

consider T_setup：

T_clk-T_clklatency-T_co-max-T_comb-max＞T_setup(formula)9)

That is to say that the first and second electrodes,

T_clk＞T_setup+T_co-max+T_comb-max+T_clklatency(formula 10)

Consider T_hold：

T_co-min+T_comb-min＞T_hold-T_clklatency(formula 11)

That is to say that the first and second electrodes,

T_co-min+T_comb-min+T_clklatency＞T_hold(formula 12)

Comparing equation 6 with equation 10, we can see T of the forward clock tree_clkThe frequency of the chip can be faster correspondingly, and higher performance can be achieved. And T of the reverse clock tree_clkIt needs to be larger, i.e. the period is larger, so the frequency of the chip becomes slower and the performance is reduced.

However, comparing equation 8 and equation 12, it can be seen that the hold time of the flip-flop is less easily satisfied when the forward clock tree is used, and the hold time of the flip-flop is more easily satisfied when the reverse clock tree is used. Especially if the delay of the combinational logic between two flip-flops is small or even absent, i.e. T_comb-minAt 0, the hold time of the forward clock tree will be difficult to satisfy.

The synchronous sequential circuit works normally on the premise that the setup time and the hold time of the flip-flop are both satisfied. The retention time is a more important indicator and must be met. If the holding time is not satisfied, the chip cannot work normally. Therefore, in the prior art, a reverse clock tree is typically used to ensure that the hold time T is met_holdAnd (4) requiring. But this sacrifices the frequency of the chip resulting in reduced performance of the chip.

The present disclosure provides a novel clock tree scheme that can satisfy the hold time T_holdThe operating frequency of the chip is required to be increased so as to improve the performance of the chip.

Fig. 4 is a schematic diagram illustrating a clock tree structure according to an embodiment of the present disclosure. As shown in FIG. 4, the clock tree includes clocksSource 400, multi-stage clock driver circuit 401₁......401_j......401_i......401_M.., a first set of clock buffer circuits 407₁......407_i......407_M.., a second set of clock buffer circuits 406₁......406_i......406_M.., and a third set of clock buffer circuits 408₁......408_{i- 1}......408_M....... The ith stage clock driving circuit is used for providing a clock for the ith operation stage of the pipeline. Where i, j, and M are less than the total number of stages N of the pipeline.

Here, the ith operation stage is explained as an example. As shown in FIG. 4, the ith operational stage of the operational block includes a first type of register 402_iRegister of the second type 403_iAnd a third type of register 404_i. Registers 402 of the first type_iIs coupled to the combinational logic 405 of the ith operational stage in addition to the input of the corresponding register of the (i + 1) th operational stage_iI.e. the first type register 402_iThe output of (c) needs to participate in the combinational logic operation. Registers 403 of the second type_iIs coupled to the combinational logic 405 of the (i-1) th operational stage_i-1I.e. the second type register 403_iReceives the output of the combinational logic from the (i-1) th arithmetic stage. Registers 402 of the first type_iAnd a second type register 403_iAre related to combinational logic operations. And a third type of register 404_iReceives the output of the corresponding register of the (i-1) th operational stage and provides its output to the corresponding register of the (i + 1) th operational stage, i.e., the third type register 404_iIndependent of the combinational logic operation of the i-1 th or ith arithmetic stage.

It should be noted that only one register of each type is shown here for simplicity of description. It will be understood by those skilled in the art that the number of registers of each type is not limited to one, but may be any number depending on the actual circuit configuration. Taking the SHA-256 circuit shown in FIG. 1 as an example, the first type register 402_iMay comprise W₀、W₁、W₉、W₁₄The second kindMemory 403_iMay comprise W₁₅Register of the third type 404_iMay comprise W₂～W₈And W₁₀～W₁₃. It should be noted that such classification of the registers of the SHA-256 circuit is merely an example, and those skilled in the art may make different classification ways according to actual situations.

As shown in fig. 4, according to the embodiment of the present disclosure, for the registers of the respective operation stages, a forward clock tree structure is adopted because the transfer direction of the clock signal is the same as the transfer direction of the data signal.

Taking the ith operation stage as an example, specifically, for the second type register 403_iClock buffer circuit 406_iIs coupled to the clock driving circuit 401 of the current ith operational stage_iTo the output terminal of (a). For registers of the first type 402_iClock buffer circuit 407 of partial register in (1)_iIs coupled to the clock driving circuit 401 of the current ith operational stage_iTo the output terminal of (a). That is, registers 402 of the first type_iAnd a second type of register 403_iIs coupled to the master clock tree.

For registers 404 of the third type_iWith clock signal terminals and corresponding registers 404 in the previous operational stage_i-1Is coupled to the same clock buffer circuit 408_i-1To the output terminal of (a). Register 404 of the third type for the (i + 1) th arithmetic stage_i+1Is also coupled to the clock buffer circuit 408_i-1Etc., and so on, up to the last stage register of the pipeline. Here corresponding register 404_i-1Register 404 referring to the ith operation stage_iIs coupled to that register 404 of the (i-1) th operational stage to which the signal input is coupled_i-1. Take SHA-256 as an example, such as register W of the ith operation stage₁₁Is coupled to the register W of the i-1 th operational stage₁₂Output of (1), thus register W of the ith arithmetic stage₁₁And the register W in the i-1 th operation stage₁₂Is coupled to the same clock bufferAnd the output end of the circuit.

Since the load capacity of the clock buffer circuit is limited, a clock buffer circuit 408 may be inserted at a certain operation stage (e.g., mth operation stage)_MWhich receives a previous clock buffer circuit 408_i-1And is a third type register 404 of the mth operation stage_MRegister of the third type 404 of the M +1 th operation stage_M+1Register of the third type 404 of the M +2 operation stage_M+2Etc. provide a clock signal. Typically, each clock buffer circuit may drive 2, 3 or 4 registers. Preferably, each clock buffer circuit can drive 2 registers.

That is, for the third type of register, a portion of the registers (e.g., the third type of register 404 of the ith arithmetic stage)_i) Is coupled to a third type of register 404 for a corresponding register (e.g., the i-1 th operational stage) in the first n operational stages (e.g., n is 1)_i-1) Clock buffer circuit 408 providing clock signal_i-1To the output terminal of (a). And another part of registers (e.g. register 404 of the third type of the mth operation stage)_M) Is coupled to a clock buffer circuit (e.g., 408) for providing a clock signal to the register of the current operational stage_M) And the clock buffer circuit 408, and_Mis coupled to respective registers 404 for the first n operational stages_i-1Clock buffer circuit 408_i-1To the output terminal of (a). Where n is the same number of registers that each clock buffer circuit can drive, i.e. may be 2, 3 or 4.

Similarly, clock buffer circuit 408_i-1Is coupled to the output of the respective clock buffer circuit of the first n operational stages up to the j-th operational stage. At the j-th operation stage, a clock buffer circuit 408 for providing clock signals to the corresponding clock buffer circuits of the next n operation stages_jIs coupled to the master clock tree.

As previously described, registers 402 of the first type_iThe clock signal terminal of the partial register in (a) is coupled to the master clock tree. And registers of the first type 402_iThe rest of (1) registersThe clock path of the register is the same as the register of the third type. That is, its clock signal terminal is not coupled to the main clock tree, but like the register of the third type, it is coupled to either the output terminal of the same clock buffer circuit as the clock signal terminal of the corresponding register in the previous operation stage or the output terminal of the clock buffer circuit for supplying the clock signal to the register of the current operation stage, and the input terminal of the clock buffer circuit is coupled to the output terminal of the clock buffer circuit for the corresponding register of the first n operation stages. Which will be described in detail below with reference to fig. 5 to 8.

According to the foregoing equation 8, since the first type register 402_iAnd a second type register 403_iParticipating in combinational logic operations, T_comb-minIs not 0 and the delay time with respect to the clock signal is often large, so that T can be satisfied even if a forward clock tree is used_hold. And not the third type of registers 404 that participate in combinational logic operations_iAnd part of the first type register 402_iBy building local sub-clock trees, coupling them to the same clock buffer circuit, i.e. such that T is_clklatencyIs 0, and can satisfy T_hold. Meanwhile, the clock module integrally adopts a forward clock tree structure, so that the running frequency of the chip can be improved, and the performance of the chip can be improved.

Examples of applications of the above inventive concepts of the present disclosure are described below in conjunction with the circuit configuration of SHA-256.

Fig. 5 is a schematic diagram illustrating a hash engine employing the clock tree structure of fig. 4 in accordance with an embodiment of the present disclosure. Fig. 5 shows a case where one clock buffer circuit drives 2 registers. In fig. 5, except for arrows between the clock driver circuits 501 and from the clock driver circuits 501, solid arrows 503 indicate transfer of a clock signal from the clock buffer circuit of the present stage to the register of the next stage, dotted arrows 502 indicate transfer of a clock signal from the clock buffer circuit of the present stage to the corresponding clock buffer circuits of the next two stages, and dotted arrows 504 indicate transfer directions of data. Note that unnecessary illustrations and descriptions are omitted herein to avoid obscuring the subject matter. For example, the hash engine of FIG. 5 omitsThe compression registers A-H are shown, only the extension register W is shown₀～W₁₅. Furthermore, for simplicity, fig. 5 shows only data transfer and clock transfer of a part of registers in each operation stage, and data transfer and clock transfer of other registers are omitted. Data transfer and clock transfer for each register in each arithmetic stage are readily contemplated by those skilled in the art in light of the teachings of this disclosure.

As shown in FIG. 5, the hash engine includes a plurality of operation stages, each operation stage including a plurality of registers W₀～W₁₅And are driven by respective clock driving circuits 501. According to the embodiment shown in fig. 5, the hash engine as a whole takes a forward clock tree structure and has partial sub-clock trees. As previously described, the first set of registers W of each operational stage₀、W₁、W₉、W₁₄And a second set of registers W₁₅Participate in combinational logic operations. Here W in the first set of registers₁And W₁₄And a second set of registers W₁₅Is coupled to the master clock tree, and W in the first set of registers₀And W₉And a third set of registers W_k(W₂～W₈And W₁₀～W₁₃) Constitute a sub-clock tree. Fig. 5 omits clock buffer circuits for ease of illustration, and those skilled in the art will appreciate that the clock signal terminals of the registers are each coupled to a corresponding clock buffer circuit.

The register W from the i-3 rd operation stage is described in detail below with reference to FIG. 6₁₄Register W to the i +11 th arithmetic stage₀The clock path of the sub-clock tree. FIG. 6 shows one clock path in the hash engine of FIG. 5, so that only one register is shown per arithmetic stage, and the other registers are omitted. Those skilled in the art will appreciate that the hash engine of fig. 5 is a pipelined structure, and thus the clock paths for the other registers in each arithmetic stage are similar to those shown in fig. 6. As shown in fig. 6, a clock signal is transmitted along the clock driving circuit 601 of each operation stage, and the clock buffer circuit 602 is used to provide the clock signal for the corresponding register. Similarly, except between clock driving circuits 601And arrows from the clock driver circuit 601, the remaining solid arrows in fig. 6 indicate the transfer of the clock signal from the clock buffer circuit to the register, the dotted arrows indicate the transfer of the clock signal from the clock buffer circuit of this stage to the corresponding clock buffer circuits of the next two stages, and the dotted arrows indicate the transfer direction of data.

As shown in FIGS. 5 and 6, a register W for the i-3 rd operation stage₁₄The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the i-2 nd operation stage₁₃And also provides a clock signal to the i-1 st operational stage for setting the register W₁₂A clock buffer circuit for providing a clock signal. By analogy, register W for the i +1 th operational stage₁₀The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the (i + 2) th operation stage₉And also provides a clock signal to the (i + 3) th operational stage for setting the register W₈A clock buffer circuit for providing a clock signal.

Register W for i +2 operation stage₉In other words, the output signal is provided in addition to the register W provided to the i +3 arithmetic stage₈In addition, a register W is required to participate in the i +3 arithmetic stage₁₅The combination operation of the signal inputs. Register W for i +3 operation stage₁₅The signal delay through 7 clock driving circuits and 1 clock buffer circuit on the main clock tree is required from the i-3 operation stage, while for the register W of the i +2 operation stage₉The signal delay of 1 clock driving circuit and 3 clock buffer circuits on the main clock tree is required from the i-3 operation stage, and thus to W₁₅Is set up for a time T_setupCan be ensured.

Referring next to fig. 5 and 6, a register W for the i +3 th operation stage₈The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the (i + 4) th operation stage₇And also provides a clock signal to the (i + 5) th operational stage for setting the register W₆A clock buffer circuit for providing a clock signal. And so on until the register W for the i +7 th operation stage₄Providing a clock signalThe clock buffer circuit supplies a clock signal to the register W of the i +8 th operation stage₃And also supplies a clock signal to the i +9 th operation stage for setting the register W₂A clock buffer circuit for providing a clock signal. Register W of the i +10 th operation stage₁And the clock buffer circuit is coupled to the clock driving circuit of the current operation stage. Further, a register W for the i +10 th operation stage₁The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the (i + 11) th operation stage₀。

Register W of the i +10 th operation stage₁Is to participate in the register W of the (i + 11) th operation stage₁₅Due to a combination operation of the signal inputs from W₁₄To W₁Has a much smaller number of clock cells than the clock cells in the master clock tree, may result in the register W of the (i + 11) th arithmetic stage₁₅Is kept for a time T_holdNot satisfying it. Thus in register W₂And a register W₁An additional register W is inserted between_{1_t}. Additional register W_{1_t}Is coupled to the register W of the current operational stage₁Its input terminal is coupled to the register W of the previous operation stage₂And its clock signal terminal is coupled to the register W for the previous operation stage₂To the output of the clock buffer circuit. Through a register W_{1_t}W for passing the signal directly to the same arithmetic stage without any logic₁The retention time T of the register can be ensured_holdIs satisfied.

Fig. 7 is a schematic diagram illustrating an exemplary clock path of a hash engine employing the clock tree structure of fig. 4, according to another embodiment of the present disclosure. It should be noted that the same portions as those of fig. 5 and 6 will not be described again, and only the portions different therefrom will be described.

Fig. 7 shows a case where one clock buffer circuit drives 3 registers. Similarly, in fig. 7, a clock signal is passed along the clock driving circuit 701 of each operation stage, and the clock buffer circuit 702 is used to supply the clock signal to the corresponding register. Similarly, clock-divided driving circuitBetween 701 and outside the arrow from the clock driver circuit 701, the remaining solid arrows in fig. 7 indicate the transfer of the clock signal from the clock buffer circuit to the register, the dotted arrows indicate the transfer of the clock signal from the clock buffer circuit of this stage to the corresponding clock buffer circuit of the next three stages, and the dotted arrows indicate the transfer direction of the data. Similarly, FIG. 7 shows a register W from the i-3 rd arithmetic stage in a hash engine employing the clock tree structure of FIG. 4₁₄Register W to the i +11 th arithmetic stage₀Thus only one register is shown per arithmetic stage, the other registers being omitted. Those skilled in the art will appreciate that the hash engine of fig. 7 is a pipelined structure, and thus the clock paths for the other registers in each arithmetic stage are similar to those shown in fig. 7.

As shown in FIG. 7, a register W for the i-3 rd operation stage₁₄The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the i-2 nd operation stage₁₃And a register W of the i-1 th operation stage₁₂And also supplies a clock signal to the ith operation stage for setting the register W₁₁A clock buffer circuit for providing a clock signal. By analogy, register W for the i +6 th operation stage₅The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the i +7 th operation stage₄And register W of the i +8 th operation stage₃And also supplies a clock signal to the i +9 th operation stage for setting the register W₂A clock buffer circuit for providing a clock signal. For register W of the i +9 th arithmetic stage₂The clock buffer circuit for supplying the clock signal also supplies the clock signal to the register W of the i +10 th operation stage_{1_t}. Register W of the i +10 th operation stage₁And the clock buffer circuit is coupled to the clock driving circuit of the current operation stage. Further, a register W for the i +10 th operation stage₁The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the (i + 11) th operation stage₀。

FIG. 8 is a diagram illustrating an exemplary clock path of a hash engine employing the clock tree structure of FIG. 4 according to yet another embodiment of the present disclosure. It should be noted that the same portions as those of fig. 5, 6 and 7 will not be described again, and only different portions therefrom will be described.

Fig. 8 shows a case where one clock buffer circuit drives 4 registers. Similarly, in fig. 8, a clock signal is passed along the clock driving circuit 801 of each operation stage, and a clock buffer circuit 802 is used to supply the clock signal to the corresponding register. Similarly, the solid arrows in fig. 8 indicate the transfer of the clock signal from the clock buffer circuit to the register, the dotted arrows indicate the transfer of the clock signal from the clock buffer circuit of the present stage to the corresponding clock buffer circuit of the next four stages, and the dotted arrows indicate the transfer direction of the data, except for the arrows between the clock driver circuits 801 and from the clock driver circuits 801. Similarly, FIG. 8 shows registers W from the i-3 rd arithmetic stage in a hash engine using the clock tree structure of FIG. 4₁₄Register W to the i +11 th arithmetic stage₀Thus only one register is shown per arithmetic stage, the other registers being omitted. Those skilled in the art will appreciate that the hash engine of fig. 8 is a pipelined structure, and thus the clock paths for the other registers in each arithmetic stage are similar to those shown in fig. 8.

As shown in FIG. 8, a register W for the i-3 rd operation stage₁₄The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the i-2 nd operation stage₁₃Register W of the i-1 th operation stage₁₂And register W of the ith operation stage₁₁And also provides a clock signal to the (i + 1) th operational stage for setting the register W₁₀A clock buffer circuit for providing a clock signal. By analogy, register W for the i +5 th operation stage₆The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the (i + 6) th operation stage₅Register W of the i +7 th operation stage₄And register W of the i +8 th operation stage₃And also supplies a clock signal to the i +9 th operation stage for setting the register W₂A clock buffer circuit for providing a clock signal. For register W of the i +9 th arithmetic stage₂Clock buffer circuit for providing clock signalRegister W provided for the i +10 th arithmetic stage_{1_t}. Register W of the i +10 th operation stage₁And the clock buffer circuit is coupled to the clock driving circuit of the current operation stage. Further, a register W for the i +10 th operation stage₁The clock buffer circuit for supplying the clock signal supplies the clock signal to the register W of the (i + 11) th operation stage₀。

In embodiments according to the present disclosure, the aforementioned registers may include edge triggered registers, such as rising edge triggered registers and/or falling edge triggered registers. The register may comprise D flip-flops (DFFs) and/or latches (latches), which may for example be latches employing a pulse type clock signal.

According to an embodiment of the present disclosure, each of the aforementioned multi-stage clock driving circuits may include an odd number of inverters. For example, each stage of the clock driving circuit may include an inverter.

The clock buffer circuit described above may include one or more clock buffers according to embodiments of the present disclosure.

Those skilled in the art will appreciate that while the concepts of the present disclosure have been described above in connection with one circuit configuration of SHA-256, the circuit configuration is not intended to constitute any limitation on the concepts of the present disclosure. The disclosed concept can be applied to any version of SHA-256 and variations and modifications thereof that are known and known. Even further, the disclosed concept can be applied in any computational circuit having a pipeline structure and including sequential devices.

According to embodiments of the present disclosure, the hash engine as described above may be implemented as a computing chip.

Those skilled in the art will appreciate that circuits and/or chips according to the present disclosure may be implemented in Hardware Description Languages (HDL) such as Verilog or VHDL. HDL descriptions can be synthesized for a library of cells designed for a given integrated circuit fabrication technology and can be modified for timing, power, and other reasons to obtain a final design database, which can be transferred to a factory for the production of integrated circuits by a semiconductor manufacturing system. Semiconductor manufacturing systems may produce integrated circuits by depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or modifying the dielectric constant with ultraviolet processing), and so forth. The integrated circuit may include transistors and may also include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between the transistors and the circuit elements.

According to an embodiment of the present disclosure, a computing chip as described above may be included in a force computing pad. In particular, the computing pad may include one or more computing chips. Multiple compute chips may perform computational tasks in parallel.

According to embodiments of the present disclosure, a computing force plate as described above may be included in a computing device, preferably for performing cryptographic currency mining. For example, the computing device may be a bitcoin miner. In particular, the cryptocurrency miner may include one or more computing plates. Multiple computing boards may perform computing tasks in parallel, such as executing the SHA-256 algorithm.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It will be further understood that the terms "comprises/comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components, and/or groups thereof.

While some specific embodiments of the present disclosure have been shown in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are intended to be illustrative only and are not limiting upon the scope of the present disclosure. It will be appreciated by those skilled in the art that the above-described embodiments may be modified without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims (14)

1. A hash engine, the hash engine comprising:

an input module configured to receive a block of data;

an arithmetic module configured to perform a hash operation on a received data block, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure such that a digital signal based on the data block passes along the plurality of arithmetic stages in sequence, each of the plurality of arithmetic stages comprising a plurality of registers and a combinational logic module; and

a clock module configured to provide a clock signal to each of the plurality of operation stages, the clock module including a multi-stage clock driving circuit such that the clock signal from a clock source is sequentially transferred along the multi-stage clock driving circuit, wherein a transfer direction of the digital signal is the same as a transfer direction of the clock signal for the plurality of registers of each of the plurality of operation stages.

2. The hash engine of claim 1, wherein, in each current operation stage,

the output of each register of a first set of registers of the plurality of registers is coupled to at least the input of the combinational logic module of the current operational stage,

an input of each register of a second set of registers of the plurality of registers is coupled to an output of a combinational logic module of a previous operational stage, an

Each register of the third set of registers of the plurality of registers has an input coupled to an output of a corresponding register in a previous operational stage and an output coupled to an input of a corresponding register in a next operational stage.

3. The hash engine of claim 2, wherein the clock module further comprises a clock buffer circuit for each register of the plurality of registers, a clock signal terminal of each register coupled to an output terminal of the corresponding clock buffer circuit,

an input of the clock buffer circuit for each of the second set of registers and the first portion of registers of the first set of registers for each current operational stage is coupled to an output of the clock driver circuit for the current operational stage, an

The clock signal terminal of each register in the second part of registers in the first group of registers of each current operation stage and the clock signal terminal of the corresponding register in the previous operation stage are coupled to the output terminal of the same clock buffer circuit.

4. The hash engine of claim 3,

the clock signal terminal of each register in the first part of registers in the third group of registers of each current operation stage and the clock signal terminal of the corresponding register in the previous operation stage are coupled to the output terminal of the same clock buffer circuit, and

the input of the clock buffer circuit for each register in the second subset of registers in the third set of registers for each current operational stage is coupled to the output of the clock buffer circuit for the corresponding register of the first n operational stages, where n is an integer and 2 ≦ n ≦ 4.

5. The hash engine of claim 4, wherein the plurality of registers of each current operation stage further comprises one or more additional registers, an output of one of the one or more additional registers being coupled to an input of a particular register of the first set of registers of the current operation stage, an input thereof being coupled to an output of a corresponding register of a previous operation stage corresponding to the particular register, and a clock signal terminal thereof being coupled to an output of a clock buffer circuit for the corresponding register of the previous operation stage corresponding to the particular register.

6. The hash engine of claim 5, in which the hash engine is a hash engineThe hash engine is used for executing SHA-256 algorithm, and the multiple registers of each current operation stage at least comprise first to sixteenth registers (W)₀......W₁₅) The first set of registers includes first, second, tenth and fifteenth registers (W)₀、W₁、W₉、W₁₄) Said second set of registers comprising a sixteenth register (W)₁₅) And the third set of registers includes third to ninth registers (W)₂......W₈) And eleventh to fourteenth registers (W)₁₀......W₁₃)，

Second, fifteenth and sixteenth registers (W) for each current operational stage₁、W₁₄、W₁₅) Is coupled to the output of the clock driving circuit for the current operational stage,

first register (W) of each current operation stage₀) Is coupled to a second register (W) for a previous operation stage₁) An output terminal of the clock buffer circuit, and

the one or more additional registers include a seventeenth register (W)_{1_t}) The output end of which is coupled to the second register (W) of the current operation stage₁) Having its input coupled to the third register (W) of the preceding operational stage₂) And its clock signal terminal is coupled to a third register (W) for a previous operational stage₂) To the output of the clock buffer circuit.

7. The hash engine of claim 6, wherein when n is 2,

the k-th register (W) of each current operation stage_k-1) Is coupled to the (k + 1) th register (W) for the previous operation stage_k) An output terminal of the clock buffer circuit, and

the k-1 register (W) for each current operation stage_k-2) Is coupled to the (k + 1) th register (W) for the first two operational stages_k) Wherein k is an even number and k is greater than or equal to 4 and less than or equal to 14.

8. The hash engine of claim 6, wherein when n is 3,

the (k + 2) th register (W) of each current operation stage_k+1) Is coupled to the (k + 3) th register (W) for the previous operation stage_k+2) At the output of the clock buffer circuit of (a),

the (k + 1) th register (W) of each current operation stage_k) And the k +2 register (W) of the previous operation stage_k+1) Are coupled together to the (k + 3) th register (W) for the first two operation stages_k+2) An output terminal of the clock buffer circuit, and

the k register (W) for each current operation stage_k-1) Is coupled to the (k + 3) th register (W) for the first three operational stages_k+2) Wherein k is a multiple of 3 and k is greater than or equal to 3 and less than or equal to 12.

9. The hash engine of claim 6, wherein when n is 4,

the (k + 2) th register (W) of each current operation stage_k+1) Is coupled to the (k + 3) th register (W) for the previous operation stage_k+2) At the output of the clock buffer circuit of (a),

the (k + 1) th register (W) of each current operation stage_k) And the k +2 register (W) of the previous operation stage_k+1) Are coupled together to the (k + 3) th register (W) for the first two operation stages_k+2) At the output of the clock buffer circuit of (a),

the k-th register (W) of each current operation stage_k-1) And the (k + 1) th register (W) of the previous operation stage_k) Clock signal terminal of (2) and the k +2 th register (W) of the first two operation stages_k+1) Are coupled together to the (k + 3) th register (W) for the first three operational stages_k+2) An output terminal of the clock buffer circuit, and

the k-1 register (W) for each current operation stage_k-2) Is coupled to the (k + 3) th register (W) for the first four operational stages_k+2) Wherein k is a multiple of 4 and k is greater than or equal to 4 and less than or equal to 12.

10. The hash engine of claim 1, in which each stage of the multi-stage clock driving circuit comprises an odd number of inverters.

11. A clock tree, the clock tree comprising:

a clock source for providing a basic clock signal; and

a multi-stage clock driving circuit along which a basic clock signal from the clock source is sequentially transferred, each stage of the multi-stage clock driving circuit for providing a clock signal for each of a plurality of operation stages arranged in a pipeline structure such that a digital signal based on a received data block is sequentially transferred along the plurality of operation stages, each of the plurality of operation stages including a plurality of registers and a combinational logic block; and

a plurality of clock buffer circuits for receiving signals from the multi-stage clock driving circuit and providing a clock signal to each of the plurality of registers, wherein a clock signal terminal of each register is coupled to an output terminal of a corresponding clock buffer circuit,

wherein a transfer direction of the digital signal is the same as a transfer direction of the clock signal for the plurality of registers of each of the plurality of operation stages,

wherein in each current operational stage, an output of each register of a first set of registers of the plurality of registers is coupled to at least an input of the combinational logic block of the current operational stage, an input of each register of a second set of registers of the plurality of registers is coupled to an output of the combinational logic block of the previous operational stage, and an input of each register of a third set of registers of the plurality of registers is coupled to an output of a corresponding register of the previous operational stage and an output thereof is coupled to an input of a corresponding register of the next operational stage,

wherein an input of the clock buffer circuit for each register in the second set of registers and the first portion of registers in the first set of registers for each current operational stage is coupled to an output of the clock driver circuit for the current operational stage,

the clock signal terminal of each register in the second part of registers in the first group of registers of each current operational stage and the clock signal terminal of the corresponding register in the previous operational stage are coupled to the output terminal of the same clock buffer circuit,

the clock signal terminal of each register in the first part of registers in the third group of registers of each current operation stage and the clock signal terminal of the corresponding register in the previous operation stage are coupled to the output terminal of the same clock buffer circuit, and

the input of the clock buffer circuit for each register in the second subset of registers in the third set of registers for each current operational stage is coupled to the output of the clock buffer circuit for the corresponding register of the first n operational stages, where n is an integer and 2 ≦ n ≦ 4.

12. A computing chip comprising one or more hash engines as claimed in any of claims 1 to 10.

13. An algorithm board comprising one or more computing chips as claimed in claim 12.

14. A cryptocurrency miner, comprising one or more force plates as claimed in claim 13.

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