CN111651403A

CN111651403A - Clock tree, hash engine, computing chip, force plate and digital currency mining machine

Info

Publication number: CN111651403A
Application number: CN202010688603.0A
Authority: CN
Inventors: 薛可; 范志军; 许超; 郭海丰; 杨作兴
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2020-07-16
Filing date: 2020-07-16
Publication date: 2020-09-11

Abstract

The present disclosure relates to a clock tree, a hash engine, a computing chip, a force plate, and a digital currency mining machine. The hash engine includes: an operation module including a plurality of operation stages arranged in a pipeline structure such that the digital signal is sequentially transferred along the plurality of operation stages, each operation stage including first, second, third, and fourth groups of registers, an input terminal of each register of the fourth group of registers being coupled to an output terminal of a corresponding register of a previous operation stage, and an output terminal being coupled to an input terminal of a corresponding register of a next operation stage; the clock module comprises a multi-stage clock driving circuit and a data processing circuit, wherein the multi-stage clock driving circuit is used for transmitting a clock signal from a clock source, and the transmission directions of the clock signal and the data signal are the same; and a plurality of clock buffer circuits for supplying a clock signal to each of the registers, an input terminal of the clock buffer circuit for supplying a clock signal to the fourth group of registers being coupled to an output terminal of the clock buffer circuit for supplying a clock signal to a corresponding register in the previous operation stage.

Description

Clock tree, hash engine, computing chip, force plate and digital currency mining machine

Technical Field

The present invention relates to circuitry for performing a hash algorithm, and more particularly to a circuit comprising a clock tree circuit, a hash engine, a computing chip, a force plate, and a cryptocurrency miner.

Background

The bitcoin system is the block chain system that was first proposed and is currently most widely recognized. One of the primary roles of bitcoin systems is to act as a decentralized public ledger, which can record a variety of financial transactions. This is called "decentralized" because the bitcoins are not issued by a single centralized monetary institution, but are generated by operations based on a particular algorithm. Bitcoin systems use distributed databases of nodes of a computer network to validate and record all transactions and use cryptographic designs to ensure security.

The current bitcoin protocol uses the secure Hash algorithm SHA (secure Hash Algorithm) -256. The SHA series of algorithms are published by the US institute of standards and technology, where SHA-256 is a secure hash algorithm with a hash length of 256 bits.

According to bitcoin protocol, a node that succeeds in determining a workload proof pow (proof of work) of a candidate block has the right to add the block to the blockchain and to generate a new crypto-currency unit as a reward. This process is known as "mining" and the nodes that execute the bitcoin algorithm are known as mining machines.

If an Application Specific Integrated Circuit (ASIC) is used to perform the mining process, i.e., an ASIC chip is used to perform the SHA-256 algorithm, the key to the design goal is to improve chip size, chip operating speed, and chip power consumption. The size of the chip determines the cost of the chip, the running speed of the chip determines the running speed of the mining machine, namely calculated force, and the power consumption of the chip determines the power consumption degree, namely the mining cost. In practical applications, the most important performance index for measuring the mining machine is the power consumed by a unit computing power, i.e., a power consumption computing power ratio. Therefore, for a bitcoin miner, it is most important to implement the SHA-256 algorithm with a lower power consumption computation ratio.

Therefore, there is a need for a circuit for implementing a hashing algorithm with a lower power consumption computation ratio.

Disclosure of Invention

According to a first aspect of the present invention, there is provided a hash engine comprising: an input module configured to receive a block of data; an arithmetic module configured to perform a hash operation on a received data block, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure such that a digital signal based on the data block passes along the plurality of arithmetic stages in sequence, each of the plurality of arithmetic stages comprising a plurality of registers and a combinational logic module, the plurality of registers comprising: a first set of registers, an output of each register in the first set of registers coupled to an input of a combinational logic module of a current operational stage and to an input of a corresponding register in a next operational stage; a second set of registers, each register in the second set of registers having an output coupled to an input of a combinational logic module of a current operational stage but not coupled to an input of a register in a next operational stage; a third set of registers, an input of each register in the third set of registers coupled to an output of a combinational logic module of a previous operational stage; and a fourth set of registers, each register in the fourth set of registers having an input coupled to an output of a corresponding register in a previous operational stage and an output coupled to an input of a corresponding register in a next operational stage; and a clock module configured to provide a clock signal to the plurality of registers of each of the plurality of operational stages, the clock module comprising: a multi-stage clock driving circuit configured to transfer a clock signal from a clock source and to provide the clock signal to the plurality of operation stages, wherein a transfer direction of the digital signal is the same as a transfer direction of the clock signal for the plurality of registers of each of the plurality of operation stages; and a plurality of clock buffer circuits configured to receive the clock signal from the multi-stage clock driving circuit and to provide the clock signal to each of the plurality of registers, wherein an input of the clock buffer circuit for providing the clock signal to each of the fourth set of registers of the current operational stage is coupled to an output of the clock buffer circuit for providing the clock signal to a corresponding register in the previous operational stage.

An input of the clock buffer circuit for each register of the first and third sets of registers of each current operational stage is coupled to an output of the clock driver circuit for the current operational stage, and an input of the clock buffer circuit for providing a clock signal to each register of the second set of registers of the current operational stage is coupled to an output of the clock buffer circuit for providing a clock signal to a respective register of the previous operational stage.

The plurality of registers of each current operational stage further includes one or more additional registers, an output terminal of one of the one or more additional registers is coupled to an input terminal of a specific register of the first group of registers of the current operational stage, an input terminal thereof is coupled to an output terminal of a corresponding register of the previous operational stage corresponding to the specific register, and a clock signal terminal thereof is coupled to an output terminal of one of the plurality of clock buffer circuits, an input terminal of which is coupled to an output terminal of a clock buffer circuit for supplying a clock signal to a corresponding register of the previous operational stage corresponding to the specific register.

A hash engine according to the present disclosure may be used to perform the SHA-256 algorithm.

According to a second aspect of the present invention, there is provided a clock tree circuit comprising: a clock source for providing a basic clock signal; and a multi-stage clock driving circuit, wherein a basic clock signal from the clock source is sequentially transferred along the multi-stage clock driving circuit, each stage of the multi-stage clock driving circuit is used for providing a clock signal for each operation stage of a plurality of operation stages, wherein the operation stages are arranged in a pipeline structure to enable a digital signal based on a received data block to be sequentially transferred along the operation stages, each operation stage of the operation stages comprises a plurality of registers and a combinational logic module, wherein for the registers of each operation stage of the operation stages, the transfer direction of the digital signal is the same as that of the clock signal, the registers comprise a first group of registers, a second group of registers, a third group of registers and a fourth group of registers, and the output end of each register of the first group of registers is coupled to the input end of the combinational logic module of the current operation stage A terminal and coupled to an input terminal of a corresponding register in a next operational stage, an output terminal of each register in the second set of registers is coupled to an input terminal of a combinational logic module of a current operational stage but is not coupled to an input terminal of a register in the next operational stage, an input terminal of each register in the third set of registers is coupled to an output terminal of a combinational logic module of a previous operational stage, and an input terminal of each register in the fourth set of registers is coupled to an output terminal of a corresponding register in the previous operational stage and an output terminal thereof is coupled to an input terminal of a corresponding register in the next operational stage; and a plurality of clock buffer circuits for receiving signals from the multi-stage clock driving circuit and providing a clock signal to each of the plurality of registers, wherein an input terminal of the clock buffer circuit for providing a clock signal to each of the fourth set of registers of the current operational stage is coupled to an output terminal of the clock buffer circuit for providing a clock signal to a corresponding register in the previous operational stage.

According to a third aspect of the present invention there is provided a computing chip comprising one or more hash engines as described above.

According to a fourth aspect of the present invention, there is provided an computing force plate comprising one or more computing chips as described above.

According to a fifth aspect of the invention there is provided a cryptocurrency miner comprising one or more computing plates as hereinbefore described.

Other characteristic features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings.

Drawings

The drawings are included for illustrative purposes and serve only to provide examples of possible structures and arrangements of the inventive apparatus disclosed herein and methods of applying the same to computing devices. These drawings in no way limit any changes in form and detail that may be made to the embodiments by one skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements.

FIG. 1 is a schematic diagram of a SHA-256 hash engine according to an embodiment of the invention.

FIG. 2A is a schematic diagram showing the driving of registers through a forward clock tree in a pipelined architecture.

FIG. 2B is a schematic diagram showing the driving of registers by an inverted clock tree in a pipelined architecture.

Fig. 3A and 3B are diagrams showing setup and hold times of registers.

Fig. 4 is a simplified schematic diagram showing a forward clock tree structure.

Fig. 5 is a diagram illustrating a clock tree structure according to an embodiment of the present invention.

FIG. 6 is a schematic diagram illustrating a hash engine employing the clock tree structure of FIG. 5.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the hash engine herein is shown by way of example to illustrate different embodiments of the circuit in the present disclosure and is not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of ways that the invention may be practiced, not exhaustive.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

The present invention proposes a novel clock tree scheme that can be used in any cryptographic algorithm circuit with a pipeline architecture. For convenience of description, the SHA-256 hash algorithm circuit is taken as an example for illustration. It will be appreciated by those skilled in the art that SHA-256 is only one example to which the clock tree scheme of the present invention may be applied, and that the present invention may also be applied to other cryptographic algorithm circuits having a pipelined structure.

Reference is now made to fig. 1, which is a schematic illustration of a SHA-256 hash engine according to an embodiment of the present invention. Those skilled in the art will appreciate that the following description of SHA-256 is provided for the purpose of more clearly presenting the inventive concepts of the present application and is not intended to be in any way limiting. Reference herein to SHA-256 includes any version of SHA-256 and variations and modifications thereof that are well known.

As shown in fig. 1, the hash engine 10 includes an input module 101, an operation module 102, and a clock module 103. The input module 101 is used to receive data blocks. The operation module 102 may perform a SHA-256 hash operation on the received data block. The clock module 103 is used for providing a required clock signal for the operation module 102.

As shown in fig. 1, the operation module 102 includes a plurality of operation stages arranged in a pipeline structure, a 1 st stage … … an ith stage … … an nth stage. N may be 32, 64, 128, etc. Each operational stage may include registers A-H and corresponding operational logic, register W₀～W₁₅And corresponding combinational logic and memory for storing the constant K. Register W₀～W₁₅Are often referred to as extension registers because they are configured to extend the input data block. Registers A-H are often referred to as packed registers because they are configured to pack expanded data into hash values.

As shown in fig. 1, in the register W₀～W₁₅In each stage of the register W₁～W₁₅Is supplied to the register W of the next stage₀～W₁₄As an input, the register W₀、W₁、W₉、W₁₄Is supplied as an input to combinational logic, the output of which is supplied to the register W of the next stage₁₅As an input. That is, the register W of each stage₀、W₁、W₉、W₁₄、W₁₅The other registers are independent of the combinational logic operation of the previous stage or the current stage.

The clock module 103 may provide a clock signal to the operation module 102, and specifically, to each register in the operation module 102. Typically, the clock signal output by clock module 103 is derived from a single clock source. However, in chips like SHA-256, there are a large number of sequential devices such as registers. If a sequential device is directly driven by a single clock source signal, the driving load capability becomes a problem, and the delay caused by the excessively long wiring from the clock source to the register clock terminal becomes excessively large. Therefore, a clock tree architecture is usually adopted to provide clock signals, i.e. a buffer or an inverter is inserted between a clock source and a sequential device to form a clock distribution network. In a pipeline architecture, there are two clock tree structures, a forward clock tree and a reverse clock tree.

FIG. 2A is a schematic diagram showing the driving of registers through a forward clock tree in a pipelined architecture. As shown, each pipelined arithmetic stage 202-1 … … 202-N is driven by a clock tree composed of a clock source 200 and a multi-stage clock driver circuit 201-1 … … 201-N. Since the direction of the clock signal propagation (left to right) coincides with the data propagation direction of the pipeline (left to right), this clock tree is called a forward clock tree.

FIG. 2B is a schematic diagram showing the driving of registers by an inverted clock tree in a pipelined architecture. As shown, each pipelined operational stage 202-N … … 202-1 is driven by a clock tree composed of a clock source 200 and a multi-stage clock driver circuit 201-1 … … 201-N. Since the direction of propagation of the clock signal (from right to left) is opposite to the direction of propagation of the data of the pipeline (from left to right), this clock tree is called an inverted clock tree.

Regardless of the clock tree structure used, the Setup Time (Setup Time) and Hold Time (Hold Time) requirements of the registers should be met. Fig. 3A and 3B are diagrams showing setup and hold times of registers. Establishing a time T_setupRefers to the time that the data must remain stable before the clock edge arrives. If the setup time does not meet the requirements, then the data cannot be stably driven into the register at this clock edge. Hold time T_holdRefers to the time after which the data must remain stable after the clock edge arrives. If the hold time does not meet the requirements, then the data likewise cannot be stably driven into the register.

This is described in detail as a circuit common to digital circuit designs. As shown in FIG. 3A, theThe circuit includes flip-

flops

301 and 303 and combinational logic 302. The data signal Q1 output by flip-flop 301 is passed through combinational logic 302 to the input of flip-flop 303, and the clock signal CLK controls flip-flop 303 to capture the data signal. In order for the data signal to be properly captured by flip-flop 303, the data signal should precede the clock edge by at least T_setupReaches the input of flip-flop 303 while holding at least T after the clock edge_holdTime of (d).

At the time of satisfying T_setupAnd T_holdThe range of the transmission delay of the intermediate combinational logic circuit can be determined. Assume a clock period of T_clkThe output delay of the flip-flop is T_coDelay of combinational logic is T_comb。

For T_setupThe following requirements are met:

T_clk-T_co-T_comb>T_setup(formula 1)

Considering the worst case, i.e. the output delay of the flip-flop is the largest, and the delay of the combinational logic circuit is also the largest, the above equation 1 becomes:

T_clk-T_co-max-T_comb-max>T_setup(formula 2)

For T_holdThe following requirements are met:

T_co+T_comb>T_hold(formula 3)

In consideration of the worst case where the delay of the output of the flip-flop is minimized and the delay of the combinational logic circuit is also minimized, equation 3 above becomes

T_co-min+T_comb-min>T_hold(formula 4)

In conjunction with the forward and reverse clock trees of FIGS. 2A and 2B, assume that the delay of each stage of the clock driving circuit is T_clklatencyThe above equations 2 and 4 become the following equations, respectively.

For a forward clock tree:

consider T_setup：

T_clk+T_clklatency-T_co-max-T_comb-max>T_setup(formula 5)

That is to say that the first and second electrodes,

T_clk>T_setup+T_co-max+T_comb-max-T_clklatency(formula 6)

Consider T_hold：

T_co-min+T_comb-min>T_hold+T_clklatency(formula 7)

That is to say that the first and second electrodes,

T_co-min+T_comb-min-T_clklatency>T_hold(formula 8)

For a reverse clock tree:

consider T_setup：

T_clk-T_clklatency-T_co-max-T_comb-max>T_setup(formula 9)

That is to say that the first and second electrodes,

T_clk>T_setup+T_co-max+T_comb-max+T_clklatency(formula 10)

Consider T_hold：

T_co-min+T_comb-min>T_hold-T_clklatency(formula 11)

That is to say that the first and second electrodes,

T_co-min+T_comb-min+T_clklatency>T_hold(formula 12)

Comparing equation 6 with equation 10, we can see T of the forward clock tree_clkThe frequency of the chip can be faster correspondingly, and higher performance can be achieved. And T of the reverse clock tree_clkIt needs to be larger, i.e. the period is larger, so the frequency of the chip becomes slower and the performance is reduced.

However, comparing equation 8 and equation 12, it can be seen that the hold time of the flip-flop is less easily satisfied when the forward clock tree is used, and the hold time of the flip-flop is more easily satisfied when the reverse clock tree is used. Especially if the delay of the combinational logic between two flip-flops is small or even absent, i.e. T_comb-minIs a non-volatile organic compound (I) with a value of 0,the hold time of the forward clock tree will be difficult to satisfy.

The synchronous sequential circuit works normally on the premise that the setup time and the hold time of the flip-flop are both satisfied. The retention time is a more important indicator and must be met. If the holding time is not satisfied, the chip cannot work normally. Therefore, in the prior art, a reverse clock tree is typically used to ensure that the hold time T is met_holdAnd (4) requiring. But this sacrifices the frequency of the chip resulting in reduced performance of the chip.

In addition, in the advanced process, no matter whether the forward clock tree or the reverse clock tree is used, the on-chip variation (OCV) factor needs to be considered when the chip is subjected to timing analysis. OCV means that the delays of the same circuit unit are different at different positions in the chip. The delay follows a gaussian distribution and may be fast or slow. This is explained below with reference to fig. 4.

Fig. 4 is a simplified schematic diagram showing a forward clock tree structure. It should be noted by those skilled in the art that the forward clock tree is used as an example herein to illustrate the effects of OCV, and those skilled in the art will appreciate that the reverse clock tree may employ the same analysis method. Furthermore, only one register is shown per operation stage for simplicity of description. It will be understood by those skilled in the art that each operational stage is not limited to one register, but that there may be multiple registers and corresponding connections. Similar methods can be used for the analysis of OCV of other registers.

As shown in FIG. 4, the clock tree includes a clock source 400, a clock driving circuit 401_iAnd a plurality of clock buffers 11 to 15 and 21 to 25. Clock driver 401_iTypically formed of an inverter. Register 402 for i-1 th arithmetic stage of pipeline circuit_i-1Driven by clock buffers 11-15, register 402 of ith operation stage of pipeline circuit_iDriven by clock buffers 21-25. Since the register 402_i-1Sending signals to register 402_iThus register 402_i-1Which may also be referred to as a launch register, and register 402_iMay be referred to as a receive register.

It is assumed that the clock buffers used in fig. 4 are identical circuit elements. It can be seen from the figure that clock source 400 goes to register 402_i-1The clock paths of (a) are: clock source → … … → clock driving circuit 401_i-1→ the clock buffer 11 → … … → the clock buffer 15 → the register 402_i-1And to register 402_iThe clock paths of (a) are: clock source → … … → clock driving circuit 401_i-1→ clock driving circuit 401_i→ the clock buffer 21 → … … → the clock buffer 25 → the register 402_i. It can be seen that register 402_iClock delay ratio register 402_i-1Only one more clock driver circuit 401_iThe delay of (2). If it is a simple clock driving circuit 401_iIs delayed, typically, register 402_i-1To register 402_iThe hold time of such directly connected registers is all that is sufficient, register 402_i-1Output delay of (T)_co-min>Clock driver 401_iTime delay T of_clklatency+ register 402_iT of_hold。

However, since the delay of the clock buffer is not fixed at different positions, the worst case scenario is analyzed in the actual chip design. For hold time timing analysis, when register 402 is launched_i-1Faster path of receiving register 402_iSlower is the worst case. Thus in an architecture such as that of FIG. 4, all slave clock sources are coupled to register 402_i-1The clock buffer is passed through with a random value α subtracted, α, from the register 402_i-1The speed of the input of (1) and the size of the output load are related. From the clock source to the register 402_iThe clock buffers are all clocked with a random value β, β and the register 402_iThe speed of the input and the size of the output load are related. In timing analysis, register 402_iComparison register 402_i-1The delay of the clock is no longer just the delay of one clock buffer but is added to the register 402_i-1Sum of random values subtracted by the clock units of each stage sum (α) on the clock path, and register 402_iSum of random values sum (β) added by the clock cells of each stage on the clock path of (1).

At this time, the register 402 according to equation 8_i-1To register 402_iThe hold time requirement of (2) becomes:

register 402_i-1Output delay of (T)_co-min>Clock driver 401_iTime delay T of_clklatency+ sum (α) + sum (β) + register 402_iT of_hold(formula 13)

The retention time requirement is then difficult to meet.

The present disclosure provides a novel clock tree scheme that can satisfy the hold time T_holdThe operating frequency of the chip is required to be increased so as to improve the performance of the chip.

Fig. 5 is a schematic diagram illustrating a clock tree structure according to an embodiment of the present invention. As shown in FIG. 5, the clock tree includes a clock source 500, a multi-stage clock driving circuit 501_j……501_i… …, a first set of clock buffer circuits 507_i… …, second set of clock buffer circuits 508_i… …, and a third clock buffer circuit 509_i… … and a fourth set of clock buffer circuits 510_i… … are provided. The ith stage clock driving circuit is used for providing a clock for the ith operation stage of the pipeline. Where i, j is less than or equal to the total number of stages N of the pipeline. The clock tree is used to clock an arithmetic module that includes registers and combinational logic.

Here, the ith operation stage is explained as an example. As shown in FIG. 5, the ith operation stage of the operation module includes a first type register 502_iRegister of the second type 503_iRegister of the third type 504_iAnd a fourth type register 505_i. Registers 502 of the first type_iIs coupled to the input of the corresponding register of the i +1 th operational stage, and is also coupled to the combinational logic 506 of the i-th operational stage_iTo the input terminal of (1). Second type register 503_iHaving its input coupled to the corresponding register of the previous operational stage and its output coupled to the group of the ith operational stageAnd logic 506_iBut not to the input of any register in the (i + 1) th operational stage. Register 504 of the third type_iIs coupled to the combinational logic 506 of the (i-1) th operational stage_i-1I.e. the third type register 504_iReceives the output of the combinational logic from the (i-1) th arithmetic stage. Register 505 of the fourth type_iIs coupled to the register 505 of the (i-1) th operational stage_i-1And its output is coupled to the register 505 of the (i + 1) th operational stage_i+1To the input terminal of (1).

It should be noted that only one register of each type is shown here for simplicity of description. It will be understood by those skilled in the art that the number of registers of each type is not limited to one, but may be any number depending on the actual circuit configuration. Taking the SHA-256 circuit shown in FIG. 1 as an example, the first type register 502_iMay comprise W₁、W₉、W₁₄Register of the second type 503_iMay comprise W₀Register of the third type 504_iMay comprise W₁₅Register of the fourth type 505_iMay comprise W₂～W₈And W₁₀～W₁₃. It should be noted that such classification of the registers of the SHA-256 circuit is merely an example, and those skilled in the art may make different classification ways according to actual situations.

As shown in fig. 5, according to the embodiment of the present invention, for the registers of the respective operation stages, a forward clock tree structure is adopted because the transfer direction of the clock signal is the same as the transfer direction of the data signal.

Taking the ith operation stage as an example, specifically, for the first type register 502_iClock buffer circuit 507_iIs coupled to the clock driving circuit 501 of the current ith operational stage_iTo the output terminal of (a). For registers 504 of the third type_iClock buffer circuit 509_iIs coupled to the clock driving circuit 501 of the current ith operational stage_iTo the output terminal of (a). That is, registers 502 of the first type_iAnd a third type of register 504_iWhen (2) is in contact withThe clock signal terminal is coupled to the master clock tree.

For registers 505 of the fourth type_iWith its clock signal terminal coupled to the clock buffer circuit 510_iI.e. clock buffer circuit 510_iFor registers 505 of the fourth type_iA clock signal is provided. As shown in FIG. 5, clock buffer circuit 510_iIs coupled to a corresponding register 505 for the (i-1) th operational stage_i-1 Clock buffer circuit 510 for providing clock signal_i-1To the output terminal of (a). And so on, for the fourth type register 505 for the i +1 th operation stage_i+1 Clock buffer circuit 510 for providing clock signal_i+1Is coupled to a respective register 505 for entering an i-th arithmetic stage_i Clock buffer circuit 510 for providing clock signal_iUp to a register of the pipeline that receives the clock signal from the master clock tree. Here corresponding register 505_i-1Register 505 referring to the ith operation stage_iIs coupled to the register 505 of the (i-1) th operational stage to which the signal input is coupled_i-1. Take SHA-256 as an example, such as register W of the ith operation stage₁₁Is coupled to the register W of the i-1 th operational stage₁₂Thus for the register W to the ith arithmetic stage₁₁The input terminal of the clock buffer circuit for providing clock signal is coupled to the register W in the i-1 th operation stage₁₂An output of the clock buffer circuit providing a clock signal.

As shown in fig. 5, a clock buffer circuit 510 is included_i-1、510_iIs at the j-th operation stage before the i-th operation stage. At the j-th operation stage, a clock buffer circuit 510 for providing a clock signal to a certain type of register (e.g., a first type of register, not shown) of the j-th operation stage_jIs coupled to the main clock tree, and the clock buffer circuit 510_jIs also coupled to an input of a clock buffer circuit for providing a clock signal to a corresponding register of the fourth type of the j +1 operational stage. Taking SHA-256 as an example, the clock buffer circuit 510_jMay be W of the j-th operation stage₉Providing clock signalsClock buffer circuit, and the clock buffer circuit 510_jIs also coupled to the register W for the j +1 operation stage₈An input of a clock buffer circuit providing a clock signal.

For registers of the second type 503_iWith its clock signal terminal coupled to the clock buffer circuit 508_iI.e. clock buffer circuit 508_iFor registers 503 of the second type_iA clock signal is provided. Second type register 503_iAlthough participating in logic operations, its inputs are also passed from the corresponding registers of the previous operational stage and are usually at the end of the pipeline signal path, so that its clock signal may not come from the main clock tree of the current operational stage, i.e. the clock buffer circuit 508_iClock driving circuit 501 that may not be coupled to the ith operation stage_iBut may be coupled to the output of a clock buffer circuit for providing a clock signal to the corresponding register of the i-1 th operational stage. For example, using SHA-256 as an example, the second type of register 503_iMay be the register W in fig. 1₀Register W for the current operational stage₀The clock buffer circuit may be coupled to the register W for the previous operation stage to provide a clock signal₁An output of the clock buffer circuit providing a clock signal.

From the foregoing equations 8 and 13, since the first type register 502_iAnd a third type of register 504_iParticipating in combinational logic operations, T_comb-minIs not 0 and the delay time with respect to the clock signal is often large, so that T can be satisfied even if a forward clock tree is used_hold. And a second type of register 503_iAnd a fourth type of register 505 that does not participate in combinational logic operations_iBy establishing a local sub-clock tree, namely, the clock buffer circuit of the register used for the current operation level is connected to the clock buffer circuit of the corresponding register used for the previous operation level, the phenomenon that the hold time of the directly connected register is violated due to the influence of OCV (open circuit control) caused by overlarge clock path difference can be avoided, and the problem that the hold time in a forward clock tree structure is not easy to meet is solved. Meanwhile, the clock module adopts a forward clock tree structure as a whole, so that the clock module has the advantages of simple structure, low cost and high reliabilityThe operating frequency of the chip can be increased to improve the chip performance.

An application example of the above inventive concept of the present invention is described below in conjunction with the circuit structure of SHA-256.

FIG. 6 is a diagram illustrating a hash engine that employs the clock tree structure of FIG. 5, according to an embodiment of the present invention. Solid arrows in fig. 6 indicate the transfer direction of the clock signal, and dotted arrows indicate the transfer direction of the data. Note that unnecessary illustrations and descriptions are omitted herein to avoid obscuring the subject matter. For example, the hash engine of FIG. 6 omits the compression registers A-H, and only the extension register W is shown₀～W₁₅. Furthermore, for simplicity, fig. 6 shows only data transfer and clock transfer of a part of registers in each operation stage, and data transfer and clock transfer of other registers are omitted. Data transfer and clock transfer for each register in each arithmetic stage are readily contemplated by those skilled in the art in light of the teachings of this disclosure.

As shown in FIG. 6, the hash engine includes a plurality of operation stages, each operation stage including a plurality of registers W₀～W₁₅And is driven by a corresponding clock driving circuit 601. According to the embodiment shown in FIG. 6, the hash engine employs a forward clock tree structure as a whole and partial sub-clock trees (e.g., from W)₁₄To W₉) As well as forward. As previously described, the register W of each operational stage₁、W₉、W₁₄、W₁₅Is coupled to the master clock tree, while the remaining registers W_k(W₀、W₂～W₈And W₁₀～W₁₃) Is clocked by the register W of the previous stage_k+1Is transferred, i.e. is the register W of the current operational stage_k(W₀、W₂～W₈And W₁₀～W₁₃) The input of the clock buffer circuit for providing the clock is coupled to the register W for the previous operation stage_k+1An output of the clock buffer circuit providing the clock. Fig. 6 omits a clock buffer circuit for convenience of explanation, and only solid arrows indicate the transfer paths of the clock signals of the registersAnd (4) diameter. It will be appreciated by those skilled in the art and informed by the teachings of the present disclosure that the clock terminal of each register is coupled to the output terminal of the corresponding clock buffer circuit.

Register W for each operation stage₉In other words, it participates in combinational logic operations, thus receiving a clock signal from a forward clock tree, while register W is simultaneously present₉And also receives the register W of the previous operation stage₁₀Of the previous operation stage, so that the register W of the previous operation stage₁₀The clock signal of (2) needs to be transferred to the register W of the current operation stage₉To meet the requirements of the sub-clock tree. Register W₁Similarly.

To this end, in the embodiment of FIG. 6, each operation stage is provided with the exception of the first to sixteenth registers W₀～W₁₅Besides, it also includes a seventeenth register W_{1_t}And an eighteenth register W_{9_t}。

Seventeenth register W_{1_t}Is coupled to the second register W of the current operational stage₁Its input terminal is coupled to the third register W of the previous operation stage₂And for supplying to the seventeenth register W_{1_t}The input terminal of the clock buffer circuit for providing the clock signal to the clock signal terminal of the preceding operational stage is coupled to the third register (W) for the preceding operational stage₂) An output of the clock buffer circuit providing a clock signal. I.e. the seventeenth register W_{1_t}Is clocked by W of the preceding operational stage₂Is transmitted.

Eighteenth register W_{9_t}Is coupled to the tenth register W of the current operational stage₉Its input terminal is coupled to the eleventh register W of the previous operation stage₁₀And for supplying to the eighteenth register W_{9_t}An input terminal of the clock buffer circuit for supplying the clock signal to the clock signal terminal of the preceding operation stage is coupled to the eleventh register W for the preceding operation stage₁₀An output of the clock buffer circuit providing a clock signal. I.e. the register W_{9_t}Clocked by a register W of a previous operation stage₁₀Is transmitted.

From the whole pipelineFrom the viewpoint, the register W of the ith operation stage₁、W₉、W₁₄、W₁₅Is coupled to the master clock tree. Register W of ith operation stage_{9_t}Is clocked by the register W of the i-1 th operational stage₁₀Is transmitted. Register W of the i-1 th operation stage₁₀Is clocked by the register W of the i-2 nd arithmetic stage₁₁Is transmitted. By analogy, the register W of the i-4 th operation stage₁₃Is clocked by the register W of the i-5 th arithmetic stage₁₄Is transmitted. Register W of ith operation stage₉Is transferred to the register W of the (i + 1) th operation stage₈. By analogy, register W of the i +6 th operation stage₃Is transferred to the register W of the (i + 7) th operation stage₂. Register W of the i +7 th operation stage₂Is transferred to the register W of the (i + 8) th operation stage_{1_t}. Register W of the i +8 th operation stage₁Is transferred to the register W of the (i + 9) th operation stage₀。

By adding the seventeenth register W configured as above_{1_t}And an eighteenth register W_{9_t}The use of both a forward primary clock tree and a forward sub-clock tree for a pipeline structure may be implemented to satisfy the T of a register_holdThe operating frequency of the chip is required to be increased so as to improve the performance of the chip.

In embodiments according to the present disclosure, the aforementioned registers may include edge triggered registers, such as rising edge triggered registers and/or falling edge triggered registers. The register may comprise D flip-flops (DFFs) and/or latches (latches), which may for example be latches employing a pulse type clock signal.

According to an embodiment of the present disclosure, each of the aforementioned multi-stage clock driving circuits may include an odd number of inverters. For example, each stage of the clock driving circuit may include an inverter.

The clock buffer circuit described above may include one or more clock buffers according to embodiments of the present disclosure.

It will be appreciated by those skilled in the art that while the inventive concept has been described above in connection with one circuit configuration of SHA-256, the circuit configuration is not intended to constitute any limitation of the inventive concept. The inventive concept can be applied to any version of SHA-256 and variations and modifications thereof that are known and known. Even more, the inventive concept can be applied in any computational circuit having a pipeline structure and including sequential devices.

According to embodiments of the present disclosure, the hash engine as described above may be implemented as a computing chip.

Those skilled in the art will appreciate that circuits and/or chips according to the present disclosure may be implemented in Hardware Description Languages (HDL) such as Verilog or VHDL. HDL descriptions can be synthesized for a library of cells designed for a given integrated circuit fabrication technology and can be modified for timing, power, and other reasons to obtain a final design database, which can be transferred to a factory for the production of integrated circuits by a semiconductor manufacturing system. Semiconductor manufacturing systems may produce integrated circuits by depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or modifying the dielectric constant with ultraviolet processing), and so forth. The integrated circuit may include transistors and may also include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnections between the transistors and the circuit elements.

According to an embodiment of the present disclosure, a computing chip as described above may be included in a force computing pad. In particular, the computing pad may include one or more computing chips. Multiple compute chips may perform computational tasks in parallel.

According to embodiments of the present disclosure, a computing force plate as described above may be included in a computing device, preferably for performing cryptographic currency mining. For example, the computing device may be a bitcoin miner. In particular, the cryptocurrency miner may include one or more computing plates. Multiple computing boards may perform computing tasks in parallel, such as executing the SHA-256 algorithm.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

While some specific embodiments of the present invention have been shown in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are intended to be illustrative only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that the above-described embodiments may be modified without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A hash engine, comprising:

an input module configured to receive a block of data;

an arithmetic module configured to perform a hash operation on a received data block, the arithmetic module comprising a plurality of arithmetic stages arranged in a pipeline structure such that a digital signal based on the data block passes along the plurality of arithmetic stages in sequence, each of the plurality of arithmetic stages comprising a plurality of registers and a combinational logic module, the plurality of registers comprising:

a first set of registers, an output of each register in the first set of registers coupled to an input of a combinational logic module of a current operational stage and to an input of a corresponding register in a next operational stage;

a second set of registers, each register in the second set of registers having an output coupled to an input of a combinational logic module of a current operational stage but not coupled to an input of a register in a next operational stage;

a third set of registers, an input of each register in the third set of registers coupled to an output of a combinational logic module of a previous operational stage; and

a fourth set of registers, each register in the fourth set of registers having an input coupled to an output of a corresponding register in a previous operational stage and an output coupled to an input of a corresponding register in a next operational stage; and

a clock module configured to provide a clock signal to the plurality of registers of each of the plurality of operational stages, the clock module comprising:

a multi-stage clock driving circuit configured to transfer a clock signal from a clock source and to provide the clock signal to the plurality of operation stages, wherein a transfer direction of the digital signal is the same as a transfer direction of the clock signal for the plurality of registers of each of the plurality of operation stages; and

a plurality of clock buffer circuits configured to receive the clock signal from the multi-stage clock driving circuit and to provide the clock signal to each of the plurality of registers, wherein an input of the clock buffer circuit for providing the clock signal to each of the fourth set of registers of the current operational stage is coupled to an output of the clock buffer circuit for providing the clock signal to a corresponding register in the previous operational stage.

2. The hash engine of claim 2, wherein an input of the clock buffer circuit for each register of the first and third sets of registers of each current operational stage is coupled to an output of the clock driving circuit for the current operational stage, an

An input of a clock buffer circuit for providing a clock signal to each register of said second set of registers of the current operational stage is coupled to an output of a clock buffer circuit for providing a clock signal to a respective register of the previous operational stage.

3. The hash engine of claim 2, wherein the plurality of registers of each current operation stage further comprises one or more additional registers, an output terminal of one of the one or more additional registers being coupled to an input terminal of a particular register of the first set of registers of the current operation stage, an input terminal thereof being coupled to an output terminal of a corresponding register of a previous operation stage corresponding to the particular register, and a clock signal terminal thereof being coupled to an output terminal of one of the plurality of clock buffer circuits, an input terminal of the one clock buffer circuit being coupled to an output terminal of a clock buffer circuit for supplying a clock signal to a corresponding register of a previous operation stage corresponding to the particular register.

4. The hash engine of claim 3, wherein the hash engine is configured to perform a SHA-256 algorithm, the plurality of registers of each current operation stage comprising at least first through sixteenth registers (W)₀……W₁₅) The first set of registers includes second, tenth and fifteenth registers (W)₁、W₉、W₁₄) Said second set of registers comprising a first register (W)₀) Said third set of registers comprising a sixteenth register (W)₁₅) And the fourth set of registers includes third to ninth registers (W)₂……W₈) And eleventh to fourteenth registers (W)₁₀……W₁₃)，

Second, tenth, fifteenth and sixteenth registers (W) for each current operational stage₁、W₉、W₁₄、W₁₅) Is coupled to the output of the clock driving circuit for the current operational stage, an

First register (W) for each current operation stage₀) Is coupled to a second register (W) for a previous operational stage₁) To the output of the clock buffer circuit.

5. The hash engine of claim 4, wherein the k-th register (W) for each current operation stage_k-1) Wherein k is an integer of 3 to k9 or 11 ≦ k ≦ 14 for the k-th register (W)_k-1) The input of the clock buffer circuit supplying the clock signal is coupled to the (k + 1) th register (W) used in the previous operation stage_k) An output of the clock buffer circuit providing a clock signal.

6. The hash engine of claim 5, wherein the one or more additional registers comprise:

seventeenth register (W)_{1_t}) The output end of which is coupled to the second register (W) of the current operation stage₁) Having its input coupled to the third register (W) of the preceding operational stage₂) And for supplying to the seventeenth register (W)_{1_t}) The input terminal of the clock buffer circuit for providing the clock signal to the clock signal terminal of the preceding operational stage is coupled to the third register (W) for the preceding operational stage₂) An output of a clock buffer circuit that provides a clock signal; and

eighteenth register (W)_{9_t}) The output end of which is coupled to the tenth register (W) of the current operation stage₉) Has its input coupled to the eleventh register (W) of the preceding operational stage₁₀) And for supplying the eighteenth register (W)_{9_t}) An input terminal of the clock buffer circuit for supplying the clock signal to the clock signal terminal of the first operation stage is coupled to an eleventh register (W) for the preceding operation stage₁₀) An output of the clock buffer circuit providing a clock signal.

7. The hash engine of claim 1, wherein each stage of the multi-stage clock driving circuit comprises an odd number of inverters.

8. The hash engine of claim 1, wherein the clock buffer circuitry for each register of the first and third sets of registers comprises two clock buffers, and the clock buffer circuitry for each register of the second and fourth sets of registers comprises one clock buffer.

9. A clock tree circuit comprising:

a clock source for providing a basic clock signal; and

a multi-stage clock driving circuit, wherein a basic clock signal from the clock source is sequentially transmitted along the multi-stage clock driving circuit, each stage of the multi-stage clock driving circuit is used for providing a clock signal for each operation stage of a plurality of operation stages, wherein the operation stages are arranged in a pipeline structure to enable a digital signal based on a received data block to be sequentially transmitted along the operation stages, each operation stage of the operation stages comprises a plurality of registers and a combinational logic module, wherein for the registers of each operation stage of the operation stages, the transmission direction of the digital signal is the same as that of the clock signal, the registers comprise a first group of registers, a second group of registers, a third group of registers and a fourth group of registers, and the output end of each register of the first group of registers is coupled to the input end of the combinational logic module of the current operation stage And coupled to inputs of respective registers in a next operational stage, an output of each register in the second set of registers being coupled to an input of a combinational logic module of a current operational stage but not to an input of a register in the next operational stage, an input of each register in the third set of registers being coupled to an output of a combinational logic module of a previous operational stage, and an input of each register in the fourth set of registers being coupled to an output of a respective register in the previous operational stage and an output thereof being coupled to an input of a respective register in the next operational stage; and

a plurality of clock buffer circuits for receiving signals from the multi-stage clock driving circuit and providing a clock signal to each of the plurality of registers, wherein an input of the clock buffer circuit for providing a clock signal to each of the fourth set of registers of the current operational stage is coupled to an output of the clock buffer circuit for providing a clock signal to a corresponding register in the previous operational stage.

10. A computing chip comprising one or more hash engines as claimed in any of claims 1 to 8.

11. An computing force board comprising one or more computing chips as claimed in claim 10.

12. A cryptocurrency miner including one or more force plates as claimed in claim 11.