CN105629159B - The measuring circuit of the data setup time of d type flip flop - Google Patents
The measuring circuit of the data setup time of d type flip flop Download PDFInfo
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- CN105629159B CN105629159B CN201511026731.4A CN201511026731A CN105629159B CN 105629159 B CN105629159 B CN 105629159B CN 201511026731 A CN201511026731 A CN 201511026731A CN 105629159 B CN105629159 B CN 105629159B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
Abstract
The invention discloses a kind of measuring circuits of the data setup time of d type flip flop, including m d type flip flop, and the data input pin of each d type flip flop is all connected data input signal；The non-output end of Q and Q of m d type flip flop exports m positive oppisite phase data output signals respectively；The input end of clock of kth position d type flip flop is connected to clock input signal by k+1 data buffer；When measurement, in the state that the positive data output signal of the Q output of each d type flip flop is all " 0 ", it enters data into signal and one state is switched to by " 0 " state, clock input signal follows data input signal to change, by read in m positive data output signals be state " 0 " number or m bit Inverting data output signals in be state " 1 " number, the delay which is multiplied by data buffer obtains the data setup time of d type flip flop.The present invention can realize the accurate measurement of the data setup time of d type flip flop.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to the data setup time of d type flip flop (DFF) a kind of
Measuring circuit.
Background technology
As shown in Figure 1, being the schematic diagram of the data setup time (setup) of d type flip flop；The ends D of d type flip flop 101 count
Data input signal DATA is connected according to input terminal, input end of clock connects clock input signal CLOCK, in clock input signal
The rising edge of CLOCK, the non-output end of Q output or Q of d type flip flop 101 will carry out data according to data input signal DATA and cut
Change, but a realization condition be data input signal DATA must be one of the rising edge apart from clock input signal CLOCK
It is maintained for stablizing before a data setup time, in the data setup time before the rising edge of clock input signal CLOCK
The signal of variation will not be exported.
SETUP is delayed between two dotted lines in Fig. 1, as shown in Figure 1, as shown in Figure 1, as data input signal DATA
When being more than that the width of setup times all remains unchanged before the rising edge of clock input signal CLOCK, at this moment output signal
Correct, i.e., the value of data input signal DATA when Q output output is the rising edge of clock input signal CLOCK；And work as
When just changing in the width of setup times of the data input signal DATA before the rising edge of clock input signal CLOCK, this
When output signal will be incorrect, i.e., Q output output no longer be clock input signal CLOCK rising edge when data input signal
The value of DATA, but the value before changing.
So in Digital Design, in standard cell lib the data setup time of d type flip flop be its key technical index it
One.It after the completion of cell library designs, needs to measure it, to verify design, simulation data base and silicon data
Consistency.But the data setup time of d type flip flop directly measures relatively difficult generally in the order of magnitude of ps.
Invention content
Technical problem to be solved by the invention is to provide a kind of measuring circuit of the data setup time of d type flip flop, energy
Realize the accurate measurement of the data setup time of d type flip flop.
In order to solve the above technical problems, the measuring circuit of the data setup time of d type flip flop provided by the invention includes m
The data input pin of each d type flip flop is all connected data input signal by d type flip flop；The reset of each d type flip flop is reset
End all connections reset reset signal.
The Q output of each d type flip flop exports the non-output end of 1 positive data output signal, Q and exports 1 instead
Phase data output signal, the Q outputs of m d type flip flops exports m positive data output signals altogether, the non-output ends of Q be total to it is defeated
Go out m bit Inverting data output signals；It is any one value in 0 to m-1 to enable k, corresponding to the positive data output signal of kth position
The d type flip flop is kth position d type flip flop, and the input end of clock of kth position d type flip flop is connected by k+1 data buffer
To clock input signal, each data buffer delay having the same.
When measurement, in the state that the positive data output signal of the Q output of each d type flip flop is all " 0 ", by institute
It states data input signal and one state is switched to by " 0 " state, the clock input signal follows the data input signal to become
Change, by reading number or m bit Invertings data output letter in the m positive data output signal for state " 0 "
It is the number of state " 1 " in number, the delay which is multiplied by the data buffer obtains the data foundation of the d type flip flop
Time.
A further improvement is that further including：The Time delay measurement circuit of data buffer；The delay of the data buffer is surveyed
Amount circuit includes n data buffer, the XOR gate of one two input.
One input terminal of the XOR gate is directly connected to the clock input signal, another input of the XOR gate
End is connected to the clock input signal by the n data buffers.
When measurement, after the clock input signal is switched to one state by " 0 " state, the XOR gate is read
The high level lasting time of output signal obtains the delay of the data buffer with the high level lasting time divided by n.
A further improvement is that the reset reset signal, the input input signal and the clock input signal by
External drive control device provides；The m positive data output signal or the m bit Invertings data output signal are read by outside
Device is taken to read.
A further improvement is that the reset reset signal, the input input signal and the clock input signal by
External drive control device provides；The m positive data output signal or the m bit Invertings data output signal are read by outside
Device is taken to read, the output signal of the XOR gate is read by external read device.
A further improvement is that the size of m is determined according to the data setup time of the d type flip flop, it is desirable that ensure that m is multiplied by
Data setup time of the delay of the data buffer more than the d type flip flop.
A further improvement is that the input end of clock of each d type flip flop and data buffer
The quantity of the connected data buffer being connected with the input end of clock of the d type flip flop of output end is m, the m numbers
It is together in series according to buffer, the input terminal of the 0th data buffer connects the clock input signal, kth position data buffer
Input terminal connection -1 data buffer of kth output end, kth be data buffer output end be connected to kth position D triggering
The input end of clock of device.
A further improvement is that more than n ratios m is order of magnitude greater, in the Time delay measurement circuit of the data buffer
The output end of preceding m data buffer is connected with the input end of clock of the corresponding d type flip flop, wherein the 0th data buffering
The input terminal of device connects the clock input signal, input terminal connection -1 data buffer of kth of kth position data buffer
Output end, kth are that the output end of data buffer is connected to the input end of clock of kth position d type flip flop.
The present invention passes through data buffering by the way that m d type flip flops are arranged between the clock input signal of adjacent bit d type flip flop
The delay of device into line delay and the d type flip flop of adjacent bit is equal to the delay of a data buffer.When measuring, enter data into
Signal is switched to one state by " 0 " state, clock input signal follows data input signal to change, and at this moment, d type flip flop will
The switching of data output signal is carried out according to the rising edge of the clock signal after the delay of input end of clock being an actually-received：
If inputted with data when the clock signal after the d type flip flop delay of corresponding position is switched to one state from " 0 " state
Delay when signal is switched to one state by " 0 " state more than or equal to data setup time, the Q of the then d type flip flop of the correspondence position
Output end exports " 1 ", non-Q output output " 0 "；And if clock signal after the d type flip flop delay of corresponding position is from " 0 " state
Delay when being switched to one state and when data input signal is switched to one state by " 0 " state be less than data setup time,
The then Q output output " 0 ", non-Q output output " 1 " of the d type flip flop of the correspondence position.
The number or m bit Inverting data of " 0 " are defeated in the positions the m positive data output signal for reading m d type flip flops
The number for going out in signal " 1 ", when can be obtained the data of d type flip flop by the product of the delay of the number and buffer and establishing
Between.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Fig. 1 is the schematic diagram of the data setup time of d type flip flop；
Fig. 2 is the measuring circuit figure of the data setup time of d type flip flop of the embodiment of the present invention；
Fig. 3 is the oscillogram of the input/output signal in Fig. 2.
Specific implementation mode
As shown in Fig. 2, being the measuring circuit figure of the data setup time of d type flip flop of the embodiment of the present invention；As shown in figure 3,
It is the oscillogram of the input/output signal in Fig. 2.The measuring circuit of the data setup time of d type flip flop of the embodiment of the present invention includes
The data input pin of each d type flip flop 201, that is, ends D are all connected data input signal DATA by m d type flip flop 201；Each institute
The reset clear terminal i.e. ends CLR for stating d type flip flop 201 all connect reset reset signal CLEAR.
The Q output of each d type flip flop 201 exports the non-output end of 1 positive data output signal, Q and exports 1
The Q output of oppisite phase data output signal, the m d type flip flops 201 exports m positive data output signals, the non-outputs of Q altogether
End exports m bit Inverting data output signals, in Fig. 2, OUTPUT data altogether<m-1:0>Corresponding to m positive phase data output letters
Number；It is any one value in 0 to m-1 to enable k, and the d type flip flop 201 corresponding to the positive data output signal of kth position is kth
Position d type flip flop 201, if the DFF0 in figure corresponds to the 0th d type flip flop 201, DFF1 corresponds to the 1st d type flip flop 201,
DFFm-1 corresponds to m-1 d type flip flops 201.The input end of clock of kth position d type flip flop 201 is slow by k+1 data
It rushes device (buffer) 202 and is connected to clock input signal CLOCK, 202 delay having the same of each data buffer
Tbuf-delay。
In the embodiment of the present invention, the size of m is determined according to the data setup time of the d type flip flop 201, it is desirable that ensures m
It is multiplied by data setup time of the delay more than the d type flip flop 201 of the data buffer 202.
Further include the delay i.e. T of data buffer 202 in the embodiment of the present inventionbuf-delayMeasuring circuit；The data
The Time delay measurement circuit of buffer 202 includes n data buffer 202, the XOR gate 203 of one two input.
One input terminal of the XOR gate 203 is directly connected to the clock input signal CLOCK, the XOR gate 203
Another input terminal be connected to the clock input signal CLOCK by n data buffers 202.
When measurement, after the clock input signal CLOCK is switched to one state by " 0 " state, the exclusive or is read
It is slow to obtain the data with the high level lasting time divided by n for the high level lasting time of the output signal OUTPUT2 of door 203
Rush the delay of device 202.
In the embodiment of the present invention, the input end of clock of each d type flip flop 201 and a data buffer
The quantity of the connected data buffer 202 being connected with the input end of clock of the d type flip flop 201 of 202 output end is m,
The m data buffers 202 are together in series, and the input terminal of the 0th data buffer 202 connects the clock input signal
CLOCK, the output end of -1 data buffer of input terminal connection kth 202 of kth position data buffer 202, kth are slow for data
The output end for rushing device 202 is connected to the input end of clock of kth position d type flip flop 201.
In the embodiment of the present invention n be arranged much larger than m such as n ratios m it is order of magnitude greater more than, the data buffer 202
Time delay measurement circuit in preceding m data buffer 202 output end and the corresponding d type flip flop 201 clock input
End is connected, wherein the input terminal of the 0th data buffer 202 connects the clock input signal CLOCK, kth position data buffering
The output end of -1 data buffer of input terminal connection kth 202 of device 202, kth are that the output end of data buffer 202 connects
To the input end of clock of kth position d type flip flop 201.The data before one input terminal of XOR gate 203 described in Fig. 2 are slow
The n rushed below device 202 indicates that the data buffer 202 be sum is the last one i.e. n-th described data buffer in n
202。
The reset reset signal CLEAR, the input input signal and the clock input signal CLOCK are driven by outside
Dynamic control device provides；The m positive data output signal or the m bit Invertings data output signal are by external read device
It reads, the output signal OUTPUT2 of the XOR gate 203 is read by external read device.
When measurement, in the state that the positive data output signal of the Q output of each d type flip flop 201 is all " 0 ",
The data input signal DATA is switched to one state by " 0 " state, the clock input signal CLOCK follows the number
Change according to input signal DATA, at this moment, d type flip flop will be believed according to the clock after the delay of input end of clock being an actually-received
Number rising edge carry out data output signal switching：
If the d type flip flop 201 of corresponding position be delayed after clock signal when being switched to one state from " 0 " state and data
Delay when input signal DATA is switched to one state by " 0 " state more than or equal to data setup time, the D of the then correspondence position
Q output output " 1 ", the non-Q output output " 0 " of trigger 201；And if the d type flip flop 201 of corresponding position be delayed after when
Prolonging when clock signal is switched to one state from " 0 " state and when data input signal DATA is switched to one state by " 0 " state
When less than data setup time, then the d type flip flop 201 of the correspondence position Q output output " 0 ", non-Q output output " 1 ".
In this way by reading number or the m bit Invertings number in the m positive data output signal for state " 0 "
According to the number in output signal being state " 1 ", the delay which is multiplied by the data buffer 202 obtains the D triggerings
The data setup time of device 201.It is described as follows：Due to the clock letter for the d type flip flop 201 being adjacent in the embodiment of the present invention
Number delay equal and that be equal to the data buffer 202 of delay；When the Q output of the d type flip flop 201 of a certain position start it is defeated
Go out after " 1 ", the Q output of the d type flip flop 201 before the correspondence position all exports " 0 ", the d type flip flop 201 after the correspondence position
Q output all export " 1 ", and Q output all export the d type flip flop 201 of " 0 " be delayed all in clock signal it is less low
Position；As long as it is found that counting the number for the d type flip flop 201 that Q output output is " 0 ", which is multiplied by the data buffering
The delay of device 202 obtains the data setup time of the d type flip flop 201；And more than the d type flip flop 201 of the corresponding position of the number
Q output all export " 1 ", the delay of clock signal is both greater than data setup time.
As shown in Figure 3, CLEAR, DATA, CLOCK are the drive signal to be provided by external drive control device；It opens
When the beginning, CLEAR, DATA signal is all set to " 0 " state, and it is " 0 " state that CLOCK signal, which follows DATA signal also,.
Then, sufficiently long CLEAR high level signals are inputted, all d type flip flops is made to be reset to " 0 " state；
Later, DATA signal is made to become high level from low level input control signal, CLOCK signal follows DATA signal
Variation；And CLOCK signal has corresponding delay after each data buffer 202, as CLOCKm corresponds to m-th
Clock signal according to buffer 202 namely with the output of m-1 201 corresponding m-1 data buffers 202 of d type flip flop,
Signal CLOCKm can postpone m × T relative to initial CLOCK signalbuf-delay；CLOCKn corresponds to nth data buffer
The clock signal of 202 outputs, signal CLOCKn can postpone n × T relative to initial CLOCK signalbuf-delay。
Later, the width value that the width for measuring the high level of the OUTPUT2 outputs of NOR gate circuit enables measurement obtain is T, T
It is equal to n × T in factbuf-delay；By the width divided by n, that is, T/n, the delay of the data buffer 202 can be thus obtained
Tbuf-delay。
Later, number, that is, OUTPUT data of d type flip flop output " 0 " are read<m-1:0>In " 0 " number；In other realities
It also can be the number of " 1 " in m bit Inverting data output signals to apply in example, and the two is identical, and it is j to enable the number.
Number j is multiplied by the delay T of the data buffer 202buf-delayIt can obtain the setup of d type flip flop, formula
For j × T/n, last value is j × Tbuf-delay。
In the embodiment of the present invention, Test driver signal, that is, CLEAR, DATA, CLOCK signal can external control, and will not
The delay on the input links such as I/O port is introduced so as to cause measurement error.
Number, that is, the j for " 0 " that the SETUP of d type flip flop 201 is exported by its end Q is obtained indirectly：That is setup is equal to j times
The delay of buffer is the delay T of data buffer 202buf-delay；And the delay of buffer is amplified n times by circuit and is obtained.It is logical
Often, the order of magnitude that the size that the time delay of buffer is generally one of tens namely j of the setup of d type flip flop is tens, and m exists
If timing demands are more than j, this can be estimated by technique, and m values can obtain greatly a bit.
Output measures signal and can directly be measured from I/O port, and will not introduce the error of output circuit delay.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of measuring circuit of the data setup time of d type flip flop, it is characterised in that：
Including m d type flip flop, the data input pin of each d type flip flop is all connected into data input signal；Each D triggerings
The reset clear terminal of device, which all connects, resets reset signal；
The Q output of each d type flip flop exports the non-output end of 1 positive data output signal, Q and exports 1 bit Inverting number
According to output signal, the Q outputs of m d type flip flops exports m positive data output signals, Q altogether, and non-output end exports m altogether
Bit Inverting data output signal；It is any one value in 0 to m-1, the institute corresponding to the positive data output signal of kth position to enable k
It is kth position d type flip flop to state d type flip flop, and the input end of clock of kth position d type flip flop is connected to by k+1 data buffer
Clock input signal, each data buffer delay having the same；
When measurement, in the state that the positive data output signal of the Q output of each d type flip flop is all " 0 ", by the number
One state is switched to by " 0 " state according to input signal, the clock input signal follows the data input signal to change, and leads to
Cross read in the m positive data output signal be state " 0 " number or the m bit Invertings data output signal in be
The number of state " 1 ", the delay which is multiplied by the data buffer obtain the data setup time of the d type flip flop.
2. the measuring circuit of the data setup time of d type flip flop as described in claim 1, which is characterized in that further include：Data
The Time delay measurement circuit of buffer；
The Time delay measurement circuit of the data buffer includes n data buffer, the XOR gate of one two input；
One input terminal of the XOR gate is directly connected to the clock input signal, another input terminal of the XOR gate is logical
It crosses the n data buffers and is connected to the clock input signal；
When measurement, after the clock input signal is switched to one state by " 0 " state, the output of the XOR gate is read
The high level lasting time of signal obtains the delay of the data buffer with the high level lasting time divided by n.
3. the measuring circuit of the data setup time of d type flip flop as described in claim 1, it is characterised in that：It is described to reset clearly
Zero-signal, the data input signal and the clock input signal are provided by external drive control device；The m positive number of phases
It is read by external read device according to output signal or the m bit Invertings data output signal.
4. the measuring circuit of the data setup time of d type flip flop as described in claim 1, it is characterised in that：It is described to reset clearly
Zero-signal, the data input signal and the clock input signal are provided by external drive control device；The m positive number of phases
Read by external read device according to output signal or the m bit Invertings data output signal, the output signal of the XOR gate by
External read device is read.
5. the measuring circuit of the data setup time of d type flip flop as described in claim 1, it is characterised in that：The size of m according to
The data setup time of the d type flip flop determines, it is desirable that ensures that m is multiplied by the delay of the data buffer more than D triggerings
The data setup time of device.
6. the measuring circuit of the data setup time of d type flip flop as described in claim 1, it is characterised in that：Each described D
The input end of clock of trigger is all connected with the output end of a data buffer and the input of the clock of the d type flip flop
The quantity of the connected data buffer in end is m, and the m data buffers are together in series, the 0th data buffer
Input terminal connects the clock input signal, the output of input terminal connection -1 data buffer of kth of kth position data buffer
End, kth are that the output end of data buffer is connected to the input end of clock of kth position d type flip flop.
7. the measuring circuit of the data setup time of d type flip flop as claimed in claim 2, it is characterised in that：
More than n ratios m is order of magnitude greater, preceding m data buffer in the Time delay measurement circuit of the data buffer it is defeated
Outlet is connected with the input end of clock of the corresponding d type flip flop, wherein described in the input terminal connection of the 0th data buffer
Clock input signal, the output end of input terminal connection -1 data buffer of kth of kth position data buffer, kth are slow for data
The output end for rushing device is connected to the input end of clock of kth position d type flip flop.
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| CN106297893B (en) * | 2016-08-01 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | The clock circuit and its design method of memory measuring circuit |
| CN106771990B (en) * | 2016-12-07 | 2020-01-24 | 武汉新芯集成电路制造有限公司 | Measuring circuit and measuring method for D trigger setup time |
| CN107300688B (en) * | 2017-06-01 | 2019-07-19 | 中国电子科技集团公司第二十八研究所 | A kind of clock frequency Calibration Method in multipoint location system |
| CN113740718A (en) * | 2020-05-29 | 2021-12-03 | 深圳市中兴微电子技术有限公司 | Method and circuit for measuring time sequence unit establishing time |
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| US7649395B2 (en) * | 2007-05-15 | 2010-01-19 | Ati Technologies Ulc | Scan flip-flop with internal latency for scan input |
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