CN105629159A - Measuring circuit of data establishing time of D triggers - Google Patents
Measuring circuit of data establishing time of D triggers Download PDFInfo
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- CN105629159A CN105629159A CN201511026731.4A CN201511026731A CN105629159A CN 105629159 A CN105629159 A CN 105629159A CN 201511026731 A CN201511026731 A CN 201511026731A CN 105629159 A CN105629159 A CN 105629159A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
Abstract
The invention discloses a measuring circuit of data establishing time of D triggers. The measuring circuit comprises m D triggers. Data input ends of the D triggers are connected with data input signals. Q output ends and Q NOT-output ends of the D triggers output m positive and negative phase data output signals. The clock input end of the kth D trigger is connected to a clock input signal via k+1 data buffers. During measurement, when the positive phase data output signals of Q output ends of all the D triggers are in '0' states, the data input signals are switched to the '1' state from the '0' state and the clock input signals change along with the data input signals. By reading numbers in the '0' state in m positive phase data output signals or numbers in the '1' state in m negative phase data output signals, the number is multiplied by the time delay of the data buffer so that the data establishing time of the D triggers is obtained. According to the invention, precise measurement of the data establishing time of the D triggers can be achieved.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, the data particularly relating to a kind of d type flip flop (DFF) set up the metering circuit of time.
Background technology
As shown in Figure 1, it is the schematic diagram that the data of d type flip flop set up the time (setup), the D end of d type flip flop 101 and data input terminus connect data input signal DATA, input end of clock connects clock input signal CLOCK, at the positive rise of clock input signal CLOCK, the Q output of d type flip flop 101 or the non-output terminal of Q will carry out data exchange according to data input signal DATA, but a realization condition is that data input signal DATA must just keep stable before data of the positive rise of distance clock input signal CLOCK set up the time, the signal that data before the positive rise of clock input signal CLOCK set up change in the time can not be output.
SETUP is time delay between two dotted lines in FIG, as shown in Figure 1, as shown in Figure 1, when data input signal DATA before the positive rise of clock input signal CLOCK when all remaining unchanged more than the width of setup time, at this moment output signal is correct, the value of data input signal DATA when namely Q output exports the positive rise for clock input signal CLOCK; And when just changing in the width of the setup time of data input signal DATA before the positive rise of clock input signal CLOCK, at this moment output signal is by incorrect, namely the value of data input signal DATA when Q output output is no longer the positive rise of clock input signal CLOCK, but the value before change.
So in digital Design, in standard cell storehouse, the data time of setting up of d type flip flop is one of its key technical index. After unit storehouse has been designed, it is necessary to it measured, thus verify the consistence of design, emulation database and silicon data. But the data of d type flip flop set up the time generally at the order of magnitude of ps, directly measure more difficult.
Summary of the invention
The data that technical problem to be solved by this invention is to provide a kind of d type flip flop set up the metering circuit of time, and the data that can realize d type flip flop set up the Measurement accuracy of time.
For solving the problems of the technologies described above, the metering circuit that the data of d type flip flop provided by the invention set up the time comprises m d type flip flop, and the data input terminus of each described d type flip flop is all connected data input signal; The reset of each described d type flip flop resets end and all connects reset reset signal.
The Q output of d type flip flop described in each exports 1 positive data output signal, the non-output terminal of Q exports 1 bit Inverting data output signal, and the Q output of m described d type flip flop exports m position positive data output signal altogether, the non-output terminal of Q exports m bit Inverting data output signal altogether; K is made to be any one value in 0 to m-1, described d type flip flop corresponding to the positive data output signal of kth position is kth position d type flip flop, the input end of clock of described kth position d type flip flop is connected to clock input signal by k+1 data snubber, and each described data snubber has identical time delay.
During measurement, when the positive data output signal of the Q output of each described d type flip flop is all " 0 ", described data input signal is switched to " 1 " state by " 0 " state, described clock input signal follows the change of described data input signal, being number for state " 1 " in the number of state " 0 " or described m bit Inverting data output signal by reading in the positive data output signal of described m position, the data that the time delay that this number is multiplied by described data snubber obtains described d type flip flop set up the time.
Further improvement also comprises: the Time delay measurement circuit of data snubber; The Time delay measurement circuit of described data snubber comprises n data snubber, the different or door of one two input.
A described input terminus that is different or door directly connects described clock input signal, and described another input terminus that is different or door is connected to described clock input signal by n described data snubber.
During measurement, after described clock input signal switches to " 1 " state by " 0 " state, read the high level lasting time of the output signal of described different or door, obtain the time delay of described data snubber with this high level lasting time divided by n.
Further improvement is, described reset reset signal, described input input signal and described clock input signal are provided by external drive control device; Described m position positive data output signal or described m bit Inverting data output signal are read by external read device.
Further improvement is, described reset reset signal, described input input signal and described clock input signal are provided by external drive control device; Described m position positive data output signal or described m bit Inverting data output signal are read by external read device, and described output signal that is different or door is read by external read device.
Further improvement is, the size of m was determined according to the data time of setting up of described d type flip flop, it is desired to ensure that the data that the time delay that m is multiplied by described data snubber is greater than described d type flip flop set up the time.
Further improvement is, the output terminal of the input end of clock of d type flip flop described in each data snubber described with one is connected, the quantity of the described data snubber being connected with the input end of clock of described d type flip flop is m, this m described data snubber is together in series, the input terminus of the 0th bit data snubber connects described clock input signal, the input terminus of kth bit data snubber connects the output terminal of kth-1 bit data snubber, and kth is the input end of clock that the output terminal of data snubber is connected to kth position d type flip flop.
Further improvement is, more than a n order of magnitude bigger than m, the output terminal of the front m data snubber in the Time delay measurement circuit of described data snubber is connected with the input end of clock of corresponding described d type flip flop, wherein, the input terminus of the 0th bit data snubber connects described clock input signal, the input terminus of kth bit data snubber connects the output terminal of kth-1 bit data snubber, and kth is the input end of clock that the output terminal of data snubber is connected to kth position d type flip flop.
The present invention is by arranging m position d type flip flop, and the time delay being carried out the d type flip flop of time delay and adjacent bit between the clock input signal of adjacent bit d type flip flop by data snubber equals the time delay of a data snubber. When measuring, " 1 " state, clock input signal is switched to follow data input signal change by " 0 " state data input signal, at this moment, d type flip flop will carry out the switching of data output signal according to the positive rise of the clocksignal after the actual time delay received of input end of clock:
When if the clocksignal after the d type flip flop time delay of corresponding position switches to " 1 " state from " 0 " state and data input signal by " 0 " state switch to time delay during " 1 " state be more than or equal to data set up the time, the Q output of the d type flip flop of this correspondence position exports " 1 ", non-Q output output " 0 "; When if the clocksignal after the d type flip flop time delay of corresponding position switches to " 1 " state from " 0 " state and data input signal by " 0 " state switch to time delay during " 1 " state be less than data set up the time, the Q output of the d type flip flop of this correspondence position exports " 0 ", non-Q output output " 1 ".
Finally by the number reading " 1 " in the number of " 0 " in the m position positive data output signal of m position d type flip flop or m bit Inverting data output signal, the data that can be obtained d type flip flop by the product of this number and the time delay of snubber set up the time.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the schematic diagram that the data of d type flip flop set up the time;
Fig. 2 is the metering circuit figure that the data of embodiment of the present invention d type flip flop set up the time;
Fig. 3 is the oscillogram of the input and output signal in Fig. 2.
Embodiment
As shown in Figure 2, it is the metering circuit figure that the data of embodiment of the present invention d type flip flop set up the time; As shown in Figure 3, it is the oscillogram of the input and output signal in Fig. 2. The metering circuit that the data of embodiment of the present invention d type flip flop set up the time comprises m d type flip flop 201, and the data input terminus of each described d type flip flop 201 and D end are all connected data input signal DATA; The reset of each described d type flip flop 201 resets end and CLR end all connects reset reset signal CLEAR.
The Q output of d type flip flop 201 described in each exports 1 positive data output signal, the non-output terminal of Q exports 1 bit Inverting data output signal, the Q output of m described d type flip flop 201 exports m position positive data output signal altogether, the non-output terminal of Q exports m bit Inverting data output signal altogether, as in Fig. 2, OUTPUTdata<m-1:0>corresponding to m position positive data output signal; K is made to be any one value in 0 to m-1, described d type flip flop 201 corresponding to the positive data output signal of kth position is kth position d type flip flop 201, as the DFF0 in figure corresponds to m-1 position d type flip flop 201 corresponding to the 0th d type flip flop 201, DFF1 corresponding to the 1st d type flip flop 201, DFFm-1. The input end of clock of described kth position d type flip flop 201 is connected to clock input signal CLOCK by k+1 data snubber (buffer) 202, and each described data snubber 202 has identical time delay Tbuf-delay��
In the embodiment of the present invention, the size of m was determined according to the data time of setting up of described d type flip flop 201, it is desired to ensure that the data that the time delay that m is multiplied by described data snubber 202 is greater than described d type flip flop 201 set up the time.
In the embodiment of the present invention, also comprise time delay and the T of data snubber 202buf-delayMetering circuit; The Time delay measurement circuit of described data snubber 202 comprises the different or door 203 of 202, one two, n data snubber input.
A described input terminus that is different or door 203 directly connects described clock input signal CLOCK, and described another input terminus that is different or door 203 is connected to described clock input signal CLOCK by n described data snubber 202.
During measurement, after described clock input signal CLOCK switches to " 1 " state by " 0 " state, read the high level lasting time of the output signal OUTPUT2 of described different or door 203, obtain the time delay of described data snubber 202 with this high level lasting time divided by n.
In the embodiment of the present invention, the output terminal of the data snubber 202 described with of the input end of clock of d type flip flop 201 described in each is connected, the quantity of the described data snubber 202 being connected with the input end of clock of described d type flip flop 201 is m, this m described data snubber 202 is together in series, the input terminus of the 0th bit data snubber 202 connects described clock input signal CLOCK, the input terminus of kth bit data snubber 202 connects the output terminal of kth-1 bit data snubber 202, kth is the input end of clock that the output terminal of data snubber 202 is connected to kth position d type flip flop 201.
In the embodiment of the present invention n arrange much larger than more than a m order of magnitude as bigger than m in n, the output terminal of the front m data snubber 202 in the Time delay measurement circuit of described data snubber 202 is connected with the input end of clock of corresponding described d type flip flop 201, wherein, the input terminus of the 0th bit data snubber 202 connects described clock input signal CLOCK, the input terminus of kth bit data snubber 202 connects the output terminal of kth-1 bit data snubber 202, and kth is the input end of clock that the output terminal of data snubber 202 is connected to kth position d type flip flop 201. The n below described data snubber 202 before an input terminus of different or door 203 described in Fig. 2 represents this data snubber 202 for sum for last in n is data snubber 202 described in n-th.
Described reset reset signal CLEAR, described input input signal and described clock input signal CLOCK are provided by external drive control device; Described m position positive data output signal or described m bit Inverting data output signal are read by external read device, and described output signal OUTPUT2 that is different or door 203 is read by external read device.
During measurement, when the positive data output signal of the Q output of each described d type flip flop 201 is all " 0 ", described data input signal DATA is switched to " 1 " state by " 0 " state, described clock input signal CLOCK follows described data input signal DATA and changes, at this moment, d type flip flop will carry out the switching of data output signal according to the positive rise of the clocksignal after the actual time delay received of input end of clock:
When if the clocksignal after d type flip flop 201 time delay of corresponding position switches to " 1 " state from " 0 " state and data input signal DATA by " 0 " state switch to time delay during " 1 " state be more than or equal to data set up the time, the Q output of the d type flip flop 201 of this correspondence position exports " 1 ", non-Q output output " 0 "; When if the clocksignal after d type flip flop 201 time delay of corresponding position switches to " 1 " state from " 0 " state and data input signal DATA by " 0 " state switch to time delay during " 1 " state be less than data set up the time, the Q output of the d type flip flop 201 of this correspondence position exports " 0 ", non-Q output output " 1 ".
Be be the number of state " 1 " in the number of state " 0 " or described m bit Inverting data output signal in described m position positive data output signal by reading like this, the data that the time delay that this number is multiplied by described data snubber 202 obtains described d type flip flop 201 set up the time. It is described as follows: owing to the clocksignal time delay of the d type flip flop 201 being adjacent in the embodiment of the present invention is equal and all equals the time delay of described data snubber 202; After the Q output of the d type flip flop 201 of a certain position starts to export " 1 ", the Q output of the d type flip flop 201 before this correspondence position all exports " 0 ", the Q output of the d type flip flop 201 after this correspondence position all exports " 1 ", and the d type flip flop 201 that Q output all exports " 0 " is all in the less low position of clocksignal time delay; As long as it will be seen that count Q output to export the number of d type flip flop 201 for " 0 ", the data that the time delay that this number is multiplied by described data snubber 202 obtains described d type flip flop 201 set up the time; And the Q output being greater than the d type flip flop 201 of position corresponding to this number all exports " 1 ", the time delay of clocksignal is all greater than data and sets up the time.
As shown in Figure 3, CLEAR, DATA, CLOCK are actuate signals for providing by external drive control device; During beginning, CLEAR, DATA signal is all set to " 0 " state, and it is also " 0 " state that CLOCK signal follows DATA signal.
Then, the CLEAR high level signal of input sufficiently long, makes all d type flip flops be reset to " 0 " state;
Afterwards, making DATA signal turn into high level from lower level input control signal, CLOCK signal follows DATA signal change; And CLOCK signal has corresponding delay after each described data snubber 202, such as the clocksignal that CLOCKm exports corresponding to the m-1 bit data snubber 202 that m data snubber 202 is also namely corresponding with m-1 position d type flip flop 201, this signal CLOCKm can postpone m �� T relative to initial CLOCK signalbuf-delay; The clocksignal that CLOCKn exports corresponding to the n-th data snubber 202, this signal CLOCKn can postpone n �� T relative to initial CLOCK signalbuf-delay��
Afterwards, it is that T, T equal n �� T in fact that the width value obtained is measured in the width order of the high level that the OUTPUT2 measuring NOR gate circuit exportsbuf-delay; By this width divided by n and T/n, the time delay T of described data snubber 202 so just can be obtainedbuf-delay��
Afterwards, read d type flip flop and export the number of " 0 " and OUTPUTdata<m-1:0>in the number of " 0 "; Also being the number of " 1 " in m bit Inverting data output signal in other embodiments, both are identical, make this number be j.
Number j is multiplied by the time delay T of described data snubber 202buf-delayJust obtaining the setup of d type flip flop, formula is j �� T/n, and last value is j �� Tbuf-delay��
In the embodiment of the present invention, Test driver signal and CLEAR, DATA, CLOCK signal can external control, and the delay on the input links such as I/O port can not be introduced thus cause measuring error.
The number of " 0 " that the SETUP of d type flip flop 201 is exported by its Q end and j obtain indirectly: the delay of buffer and the time delay T of data snubber 202 that namely setup equals j timesbuf-delay; And the delay of buffer is doubly obtained by circuit amplification n. Usually, the time delay of buffer is generally one of tens of the setup of d type flip flop, and also namely the size of j is the order of magnitude of tens, and m requires when setting to be greater than j, and this can be estimated by technique, and m value can obtain greatly a bit.
Output records signal and directly can measure from I/O port, and can not introduce the error of output circuit delay.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention. Without departing from the principles of the present invention, the technician of this area also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. the data of a d type flip flop set up the metering circuit of time, it is characterised in that:
Comprise m d type flip flop, the data input terminus of each described d type flip flop is all connected data input signal; The reset of each described d type flip flop resets end and all connects reset reset signal;
The Q output of d type flip flop described in each exports 1 positive data output signal, the non-output terminal of Q exports 1 bit Inverting data output signal, and the Q output of m described d type flip flop exports m position positive data output signal altogether, the non-output terminal of Q exports m bit Inverting data output signal altogether; K is made to be any one value in 0 to m-1, described d type flip flop corresponding to the positive data output signal of kth position is kth position d type flip flop, the input end of clock of described kth position d type flip flop is connected to clock input signal by k+1 data snubber, and each described data snubber has identical time delay;
During measurement, when the positive data output signal of the Q output of each described d type flip flop is all " 0 ", described data input signal is switched to " 1 " state by " 0 " state, described clock input signal follows the change of described data input signal, being number for state " 1 " in the number of state " 0 " or described m bit Inverting data output signal by reading in the positive data output signal of described m position, the data that the time delay that this number is multiplied by described data snubber obtains described d type flip flop set up the time.
2. the data of d type flip flop as claimed in claim 1 set up the metering circuit of time, it is characterised in that, also comprise: the Time delay measurement circuit of data snubber;
The Time delay measurement circuit of described data snubber comprises n data snubber, the different or door of one two input;
A described input terminus that is different or door directly connects described clock input signal, and described another input terminus that is different or door is connected to described clock input signal by n described data snubber;
During measurement, after described clock input signal switches to " 1 " state by " 0 " state, read the high level lasting time of the output signal of described different or door, obtain the time delay of described data snubber with this high level lasting time divided by n.
3. the data of d type flip flop as claimed in claim 1 set up the metering circuit of time, it is characterised in that: described reset reset signal, described input input signal and described clock input signal are provided by external drive control device; Described m position positive data output signal or described m bit Inverting data output signal are read by external read device.
4. the data of d type flip flop as claimed in claim 1 set up the metering circuit of time, it is characterised in that: described reset reset signal, described input input signal and described clock input signal are provided by external drive control device; Described m position positive data output signal or described m bit Inverting data output signal are read by external read device, and described output signal that is different or door is read by external read device.
5. the data of d type flip flop as claimed in claim 1 set up the metering circuit of time, it is characterized in that: the size of m was determined according to the data time of setting up of described d type flip flop, it is desired to ensure that the data that the time delay that m is multiplied by described data snubber is greater than described d type flip flop set up the time.
6. the data of d type flip flop as claimed in claim 1 set up the metering circuit of time, it is characterized in that: the output terminal of the input end of clock of d type flip flop described in each data snubber described with one is connected, the quantity of the described data snubber being connected with the input end of clock of described d type flip flop is m, this m described data snubber is together in series, the input terminus of the 0th bit data snubber connects described clock input signal, the input terminus of kth bit data snubber connects the output terminal of kth-1 bit data snubber, kth is the input end of clock that the output terminal of data snubber is connected to kth position d type flip flop.
7. the data of d type flip flop as claimed in claim 2 set up the metering circuit of time, it is characterised in that:
More than a n order of magnitude bigger than m, the output terminal of the front m data snubber in the Time delay measurement circuit of described data snubber is connected with the input end of clock of corresponding described d type flip flop, wherein, the input terminus of the 0th bit data snubber connects described clock input signal, the input terminus of kth bit data snubber connects the output terminal of kth-1 bit data snubber, and kth is the input end of clock that the output terminal of data snubber is connected to kth position d type flip flop.
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| CN106771990A (en) * | 2016-12-07 | 2017-05-31 | 武汉新芯集成电路制造有限公司 | The measuring circuit and measuring method of d type flip flop setup time |
| CN107300688A (en) * | 2017-06-01 | 2017-10-27 | 中国电子科技集团公司第二十八研究所 | A kind of clock frequency Calibration Method in multipoint location system |
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| CN105629159B (en) | 2018-08-21 |
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