CN101848007A - The apparatus and method that are used for the digital adaptive equalizer of serial receiver - Google Patents
The apparatus and method that are used for the digital adaptive equalizer of serial receiver Download PDFInfo
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Abstract
The invention discloses the circuit and the method that are used to carry out adaptive frequency compensation in the serial receiver that is connected to the differential signal channel link.In the exemplary embodiment, provide the receiver that comprises linear equalization function, is used for signal on the serial channel link.Data recovery circuit is connected to the output and the receive frequency compensating analog signal of receiver.The output of digital feedback control circuit observation numeral.The signal that the data accumulator circuit receives the output of comparator and represents institute's observation data pattern in the numerical data output.Digital filter receives the control signal that accumulator data and output are used for revising the linear equalization of feedback loop.Receiver and linear equalization function are revised automatically and adaptively so that frequency compensation to be provided.The invention discloses and be used to use digital feedback to revise the method for the frequency response of receiver and linear equalizer adaptively.
Description
It is the U.S. Provisional Application the 61/163rd of " Apparatus and Methodsfor Digital Adaptive Equalizer in Serial Receiver " that the application requires in the title that on March 27th, 2009 submitted to, No. 985 priority, its full content combination therewith as a reference.
Technical field
The present invention relates to be used to provide the circuit and the method for improved integrated circuit (IC) design and be used to provide method at the receiver of differential input signal.The use of serial-unstring (SerDes) data link is being known in the art, wherein, the numerical data digital data stream that become serial data stream, clock control, convert analog signal to, use the transmission of difference signaling channel link, be received as analog signal, recovered clock information and be received from clock control by receiver.Then, the deserializer output digital data is used in the receiving equipment.Channel has the significant loss of signal, especially at high frequency.Therefore, in receiver, use linear equalizer to lose with compensate for channel.Embodiments of the invention provide the linear equalizer that utilizes in the integrated circuit that uses various transmitters and channel to realize the advantage of this receiver.
Background technology
At present, in the integrated circuit that uses analog circuit, be used to realize the receiver of differential signal.For example, Fig. 1 shows the system diagram of the existing transmitter 11 of typical case that is connected to link channel 13, and link channel 13 is used for differential signal is sent to receiver 15.Receiver may be implemented as in the integrated circuit, on the circuit board or receiver in a plurality of integrated circuit and AFE (analog front end) (RXAFE).Receiver extracts the data that receive from analog difference signal, and after some are handled, can export the digital data signal that receives by receiver.Can use the known self clock technology of prior art in the SerDes link.
When the analog receiver circuit is integrated circuit a part of, the parameter that changes the analogue component that uses in the receiver difficulty that becomes.Some known existing methods employing external components compensate the response at the receiver of different channels and transmitter.Some known methods can comprise adjusts the interior resistor of chip etc.These adjustment or tuning methods are not adaptive for the change after a while in the system.That is, if receiver ic is connected to different channel links or different transmitter after a while or has the channel of time-varying characteristics, then the integrated receiver of prior art can be subsequently be optimized at the environment of mistake.
Fig. 2 (a) shows the exemplary frequency response curve at channel link.As known to those skilled in the art, channel loss occurs in the transmission channel, and this causes the gain loss (amplitude decline) in the channel, especially on characteristic frequency.These losses may be because some kinds of factors include but not limited to kelvin effect, dielectric coupling loss and other transmission losses.Total channel loss seems to be similar to the frequency response of low pass filter.In order to lose in the channel that compensates received signal, receiver should be used as high pass filter (aspect frequency response).Fig. 2 (b) shows the desired frequency response of the receiver that is connected to channel.By providing gain with correct frequency, receiver can be the signal compensation channel loss that is received, and in conveyer they is returned to original amplitude.Therefore, the receiving machine frequency response of expectation and the channel loss in the channel frequency response be complementary and the compensate for channel frequency response in channel loss.The overall frequency response of the expectation of channel and receiver is a kind of in the expansion of smooth loss and bandwidth.
Fig. 3 shows the example combination frequency response of channel response among Fig. 2 (a) and the response of the receiver among Fig. 2 (b).Amplitude is gone up in frequency range (smooth loss) and is kept constant and compensated the channel loss effect, and signal amplitude is remained on the upper frequency (bandwidth expansion) that channel loss will take place.
Receiving machine frequency response is represented by the linear equalization function (LEQ) in receiver AFE (analog front end) (RXAFE) circuit.LEQ should be complementary with channel frequency response ideally.By the curve among Fig. 4 this notion is shown.In the top view that the curve that is designated as " channel 1 ", " channel 2 " and " channel 3 " is shown, show frequency response at three different channels, wherein, receiver circuit and analog front circuit RXAFE should be connected to this three different channels.Each channel all has different channel loss characteristics.In the diagrammatic sketch of bottom, show the receiver LEQ frequency response that needs in these three channels of compensation each.If receiver utilizes various channel conditions to operate, then LEQ should be adaptive with loss characteristic of the difference in the compensate for channel or different channels.
The LEQ frequency response has at least 3 important components, shown in the response curve among Fig. 5.Gain peak frequency Fgp is a kind of target property and the frequency of having represented to obtain most of receiver gains.For compensate for channel loss, its should with the frequency dependence that causes the channel loss in the channel frequency response.The Gmax characteristic represents to comprise needed maximum gain in the receiver of LEQ.Δ G characteristic is the gain inequality that needs between height and the response of low frequency receiver.Typically, in stability at lower frequencies, channel loss is not very remarkable, so receiver does not need to have the gain of these parts that are used for received signal.
Figure 6 illustrates the method for the prior art that receiver function is provided.Channel 13 is shown as and is connected to receiver function 60.This receiver function can be the one or more integrated circuits on the circuit board, and discrete circuit or increasing receiver function can be to comprise such as the ASIC of other functions of signal processor etc. or the part of SOC integrated circuit.Receiver front end 63 comprises analog receiver and the linear equalizer function that prior art is known.Then, analog signal is transferred to clock and data recovery piece 65 in couples, it includes but not limited to analog to digital converter, clock recovery circuitry.Then, the serial data stream of recovery is converted to parallel data by serial input and line output circuit (SIPO) 67, and circuit 67 can be implemented as FIFO, circular buffer, shift register or other Digital Logical Circuits known in the art.
The input of receiver front end 63 is denoted as (1), (2) and (3), and expression is used to change the input of above-mentioned three characteristics (that is, peak gain frequency Fgp, peak signal gain G max and gain inequality Δ G).Must provide these inputs by external circuit or additional internal circuit.These inputs of the prior art are selected with respect to channel frequency response by adjustment or calibration process (for example, being fixed).If channel response changes with temperature or other variations take place, if perhaps receiving equipment is connected to different channels, the circuit that then drives these inputs should be changed, otherwise the response of receiver LEQ no longer can the compensate for channel loss.
In the analog receiver that is formed for the serial differential channel communication, use the increase trend of integrated circuit to increase to regulating demand adaptively with the receiver that correct compensation is provided.
Therefore, lasting needs can solve the improving one's methods and circuit of these and other problems of prior art receiver.
Summary of the invention
By embodiments of the invention, solve or avoided these and other problems usually and realized technological merit usually, embodiments of the invention provide: a kind of receiver provides linear equalization for the signal that receives from the differential channel link adaptively; And a kind of method, the variation in the compensate for channel frequency response automatically, and need not additional calibration or adjustment.Receiver combines the digital feedback function to provide automatically and the self adaptation operation.
In first exemplary embodiment of the present invention, provide the receiver that is used on the serial channel link, receiving differential signal.This receiver includes linear equalization function.Data recovery circuit is connected to the output and the receive frequency compensating analog signal of receiver.Carry out analog-to-digital conversion and clock recovery, obtain digital output signal.Carry out string and conversion with the output parallel data signal.The output of digital feedback control circuit observation data.At least one amplitude comparator is connected to the output of linear equalization function.The data accumulator circuit receives the output of comparator and is illustrated in data pattern (pattern, signal pattern) that observes in the numerical data output.Digital filter receives the control signal that accumulator data and output are used for revising the linear equalization of feedback control loop.Receiver and linear equalization function are revised automatically and adaptively so that the frequency compensation to the loss of signal in the channel link to be provided.
In one approach, differential signal is received on the serial channel link, and carries out linear equalization with output frequency compensating analog signal.Analog signal is carried out analog-to-digital conversion, and recover numerical data and clock signal.Carry out amplitude ratio to determine whether analog signal amplitude surpasses at least one predetermined threshold.Handle the output digital feedback signal with the characteristic of linear adjustment equilibrium and provide self adaptation and frequency compensation method automatically by digital filtering.
Front summary is also wide in range has described feature of the present invention and technological merit, thus the detailed description that the present invention may be better understood below.This summary of the invention part has briefly been described certain exemplary embodiments of the present invention, but the present invention is not limited only to these exemplary embodiments.
Below will describe supplementary features of the present invention and advantage, it forms the theme of claim of the present invention.It should be appreciated by those skilled in the art that disclosed notion and specific embodiment can be by easily with making an amendment or being designed for other structures of carrying out the purpose identical with the present invention or the basis of processing.Those skilled in the art be also to be understood that this equivalent constructions does not deviate from the spirit and scope of the present invention of claims.
Description of drawings
For complete understanding the present invention and advantage thereof, carry out following description referring now to accompanying drawing, wherein:
Fig. 1 shows receiver, transmitter and the link channel of prior art;
Fig. 2 (a) shows the channel frequency response curve of prior art, and Fig. 2 (b) shows the receiving machine frequency response of prior art;
Fig. 3 shows the receiver that is used for Fig. 2 (a) and Fig. 2 (b) and the combination frequency response curve of channel;
The desired frequency response that Fig. 4 shows the frequency response curve that is used for three kinds of channel conditions and is used for the linear equalizer of three kinds of channel conditions;
Fig. 5 shows in detail the channel frequency response curve that is used for the prior art linear equalizer;
Fig. 6 shows receiver and the interlock circuit in the prior art scheme block diagram;
Fig. 7 shows the exemplary embodiment of receiver of the present invention with block diagram;
Fig. 8 illustrates three kinds of signal eye conditions with voltage time;
Fig. 9 shows the digital feedback control unit of the embodiment of Fig. 7 with block diagram;
Figure 10 shows the function of data pattern matching unit of the digital feedback control unit of Fig. 9 with block diagram;
Figure 11 illustrates trigger (toggle) measuring ability with simple logic;
Figure 12 shows data-signal pattern corresponding to first group identifier with timing diagram;
Figure 13 shows data-signal pattern corresponding to second group identifier with timing diagram;
Figure 14 shows data-signal pattern corresponding to the 3rd group identifier with timing diagram;
Figure 15 shows data-signal pattern corresponding to the 4th group identifier with timing diagram;
Figure 16 shows the function of data accumulator of the digital feedback control unit of Fig. 9 with block diagram;
Figure 17 shows the function of digital filter of the digital feedback control unit of Fig. 9 with block diagram;
Figure 18 shows three kinds of channel conditions that use in the emulation with another frequency response curve;
Figure 19 shows the response that utilizes the linear equalizer of the embodiment of the invention for three curves of Figure 18 with another frequency response curve;
Figure 20 shows each the combination frequency response curve of curve with three kinds of channel conditions being used for Figure 18 and Figure 19 and three linear equalizer emulation;
Figure 21 shows the signal eye diagram that does not use the embodiment of the invention and obtain; And
Figure 22 shows the signal eye diagram that obtains at receiver example of the present invention.
Accompanying drawing, illustrative diagram only are exemplary, are not limited to the example of the embodiment of the invention, and for exemplary purpose, they are simplified, and needn't draw in proportion.
Embodiment
Go through the manufacturing and the use of the preferred embodiment of the present invention below.Yet, should be appreciated that, the invention provides many applicable notions that can in various concrete environment, realize.The specific embodiment of being discussed only is the signal of making and use concrete mode of the present invention, limits the scope of the invention and be not used in.
Fig. 7 shows the exemplary embodiment in conjunction with the receiver circuit of feature of the present invention.For example, receiver 70 may be implemented as an integrated circuit part, that use ASIC, SOC or traditional design technology as the big integrated circuit that is combined with optional feature and circuit; For example, in transceiver or systems approach integrated circuit, perhaps as the circuit board that is combined with some integrated circuits or discrete circuit.Each of these optional realizations is all expected as the part of embodiment, and is fallen in the scope of claims.Use in-line memory and other designing techniques that the specific part of receiver 70 is divided into digital integrated circuit, analog integrated circuit, software and programmable processor, this is divided all within the scope of the appended claims.Composite signal integrated circuits can be used to realize receiver 70.Can use semiconductor processes to make composite signal integrated circuits, device is optimized for the analog functuion such as analog receiver, operational amplifier etc., and additional device is optimized for the digital function such as Digital Logic, digital filter, digital processing unit etc.Then, can be arranged on the single piece of silicon as integrated circuit by the device that these are different.Can use multicore sheet method for packing, wherein, individual devices or module are formed and comprise the analog-and digital-integrated circuit that is joined together to form receiver 70.
Fig. 8 shows the signal amplitude comparator 79 of Fig. 7 and 83 operation with simple timing diagram.Comparator will be from the amplitude of the differential signal of receiver front end 73 output and two voltage references one compares.In Fig. 7, comparator 79 receives voltage reference Vreference1.Comparator 83 receives Vreference2.These amplitude comparators can use known sampling and keep analog comparator circuit (such as at paper (the IEEE J.Solid-StateCircuits of people's titles such as Lee for " LOW-POWER AREA-EFFICIENTHIGH-SPEED I/O CIRCUIT TECHNIQUES ", volume 35, o.11,2000,1596 pages) the middle circuit of describing) form, it is as the limiting examples of sampling and holding circuit.Can also use other known samplings and keep comparator.
In Fig. 8, amplitude and these voltage references of the signal eye (signal eye) that will form on the zero crossing interval of the time-varying input signal that receives compare.When receiver LEQ 73 suitably to received signal compensate for channel loss, the amplitude of received signal will be greater than voltage threshold Vreference1 and Vreference2.If compensate insufficiently, then amplitude can be greater than less threshold value but less than big threshold voltage.If the compensation in the receiver 73 is more inadequate, then the amplitude of received signal eye can be lower than low threshold value more.The output of two comparators is used to determine whether three feedback control signals need to change to change receiver LEQ 73 frequency responses.In requiring the optional embodiment of less silicon, only use a comparator and a voltage reference.
Comparator circuit can fully operated under the sample frequency less than data transfer rate.For example, the comparator sample frequency can be low to moderate 1/20 of data transfer rate, and is perhaps high to 1/2,1/4,1/8 or 1/16 of data transfer rate.The lower frequency comparator is simpler for design and enforcement, uses less power and less silicon area, is favourable therefore.Use for specific design,, can also use than the high sampling rate comparator certainly if allow power and area sources to consider.Even utilize the lower frequency comparator to realize the advantage of embodiment.Comparator output provides the watch-dog of channel and LEQ combination overall frequency response.When the signal eye amplitude was higher for a plurality of received signals, it was good that receiver LEQ is provided with, and for the particular channel condition, the expectation purpose of smooth loss and spread bandwidth is satisfied in the combination frequency response.When signal eye had short arc, receiver LEQ need be conditioned.Short arc means that the combination frequency response is not used in the optimization channel condition.
The output of two comparators is connected to digital control feedback unit 81.Fig. 9 shows digital control feedback unit 81 with the block diagram form.Digital control feedback unit 81 comprises three functional blocks.The data flow that data pattern matching unit 92 receives from SIPO circuit 77, and carry out the data pattern matching feature as described further below.The data pattern matching unit provides m output Gr (m-1:0).One among the group output Gr is which is detected by piece 92 in logic high or four possible group data pattern of " 1 " expression.Receive group expression information Gr by data accumulator 94.In data accumulator 94, there be m accumulator.Shown in this example of describing, have three data accumulators at least, one is used for each of three feedback control functions.Each accumulator in the data accumulator 94 is all exported the accumulator signal Ac of k bit wide.In the exemplary embodiment described in detail here, the directed peak gain frequency Fgp control signal of accumulator; One is pointed to maximum gain Gmax control signal; And the directed Δ G of the 3rd accumulator gain inequality control signal.
Then, the Ac of the k bit wide of three accumulators output is connected to digital filter functions 96.Digital filter functions is designed or is programmed for the correction feedback control output that generates the LEQ frequency response that is used for optimizing receiver front end 73 based on data accumulator output.Digital filter can be set up as the hardware capability that uses circuit, perhaps alternatively as the program of being carried out by programmable digital processor (such as digital signal processor), perhaps can use their combination.
In operation, three of digital control feedback unit 81 kinds of functions one work to export three feedback control signals in response to the observation signal from receiver front end.In this self adaptation feedback control loop, the digital feedback controlled function will automatically be revised the frequency response of control signal with processing receiver LEQ 73, thereby compensate total channel frequency response and the response of the combination frequency with smooth loss and spread bandwidth characteristic is provided.Change in transmitter or the channel or change receiver receive different channels and are compensated automatically by digital control feedback unit.
Figure 10 simply shows the operation of an example of data pattern matching feature 92 enforcements, and it makes a distinction four preset pattern groups and the data flow that is received.Show the order of received data stream with timeline 80 in the block diagram bottom of Figure 10.The data D[n-1:0 of " t " constantly] formed parallel word Dt[0] ..., Dt[n-1]." t-1 " data of being received have formed parallel word Dt-1[0 constantly] ..., Dt-1[n-1].The parallel group of these of serial received data is exported by the SIPO unit, and fclk1 is synchronous with clock.Output data bus Gr[m-1:0] the current pattern matching result of expression, notice that clock fclk1 is identical with the speed of fclk1.Gr[m-1:0] will upgrade with the fclk1 clock frequency.
In operation, the data pattern matching feature 92 trigger pattern in the specified data stream at first.Figure 11 shows an example of the trigger pattern detector of data pattern matching feature 92 uses and implements.A plurality of xor functions are connected in series and form trigger consequential signal (TR) by each data bit D is compared with its nearest neighbours.By this way, there are data (trigger) to zero in the serial data stream that receives by SIPO or, can be confirmed as trigger from zero to one variation.Notice that trigger TR is as a result imported with matched data by time index.
Each group of four groups (in this illustrative examples, use four groups, but can also be more) all corresponding to the one or more predetermined data pattern in the data flow that receives by SIPO.Data pattern matching feature 92 must according to the trigger of constantly " t " as a result TR determine group identifier.In an exemplary enforcement, this information is at m bit wide group bus Gr[m-1:0] go up output as proprietary sign indicating number, the Gr bus only has a quilt " set " or is height.Can also use other sign indicating numbers.
Figure 12 shows the example of " group 1 " pattern.In Figure 12, show trigger TR as a result in the bottom of figure.TR field TRt-1[n-2] ... TRt[2] in pattern " 00110 " expression organize 1 pattern.In Figure 13, from TRt-1[n-2] ... TRt[2], the pattern among the trigger result field TR of " x1111x " or " x1100x " or " x1100x " represents to organize 2 patterns.
Figure 14 shows the example of group 3 patterns.Similarly, Figure 15 shows the example of group 4 patterns.
The pattern of expression group 1 concentrates on gain peak frequency Fgp.The pattern of expression group 2 concentrates on maximum gain Gmax.Expression group 3 concentrates on the relevant pattern of Δ G with 4 pattern.Which accumulator that the output of data pattern matching feature illustrates in the data accumulator function should work.Have three accumulators, one is used for each of feedback control signal.These accumulator cross-references.
Therefore, the combination by the XOR computing detect four patterns each with identification trigger position and with pattern matching feature 92 in comparison storage, preset pattern.In this example, output signal Gr is a single position effective code, so if organizing 1 is identified in the pattern that moment t sees, then be provided with from signal Gr[m-1:0] position 0, other are set to zero.Be identified if organize 2, position 1 is set, and position Gr[m-1:2] and Gr[0] be zero.Similarly coding is used to indicate group 3 or organizes 4 patterns coupling.
In data accumulator function 94, comparator input (if use two comparators, then being a plurality of inputs) is relevant with picture group sample coupling.Whether the LEQ receiving machine frequency response that comparator input expression combines with channel frequency response is fully compensated.
Figure 16 shows the internal frame diagram of the exemplary enforcement of data accumulator function 94.The data accumulator function receives group identifier signal Gr and clock signal fclk2.Data accumulator has m bidirectional counter (or forward-backward counter), and each all has " k " position and is used for counting.These variablees allow design flexible.For concrete enforcement as described herein, have 3 bidirectional counters, each of a control signal that is suitable for being used to controlling self adaptation LEQ.Therefore, in this example, m is 3.Can select the value of k based on clock frequency and design parameter as required; Certainly, cause less counter than the k of low value, therefore, less transistor and silicon area are used for the accumulator function.For each the clock fclk2 that is provided with corresponding Gr position, the comparator input tells counter to increase progressively counting or countdown.The form of accumulator output is signal Ac_0[k-1:0] ... Ac_m-1[k-1:0].
In operation, based on the input of at that time comparator, bidirectional counter subtracts 1 or add 1.Select effective bidirectional counter by the position that is provided with among the group signal Gr.Typically, subtract 1 by carrying out to current counting added value 111....0.Add 1 by carrying out to current counting increase 000...01.Preferably, utilize to overflow to protect and implement counter with underflow.That is, when the border is overflowed in the counter touching, it will no longer increase.When counter touching underflow border, it will no longer reduce.Although do not lost some information owing to counting has change no longer to touch boundary condition until Counter Value, underflow or overflow error during this has prevented to calculate.
Figure 17 shows the exemplary enforcement of digital filter functions 96 with block diagram.Divider is used to divided by the accumulator value that enters to form less output area.Formed digital filter signal Df_0 ... Df_m-1.Each digital filter signal substantially all is corresponding accumulator signal Ac[k-1:0] from the Ac signal, subtract " j " position highest significant position (MSB).This effectively with the Ac signal divided by the value 2j.Counter of the correspondence of divider 961 and 962 from data accumulator 94 receives the Ac signal, and output is corresponding to the Df signal of position [k-1-j:0].Then, digital filter is converted to this Df bus heat sign indicating number (thermal code) or thermometer-code in piece 963.In this illustrative examples, have three feedback control signals; One is used for the LEQ crest frequency, and one is used for LEQ maximum gain Gmax, and one is used for LEQ Δ G.In other exemplary application, can use more feedback signal, data accumulator, divider and hot code generator all will be with each output signals that is to use in the feedback control loop.
Figure 18 illustrates the simulated example set of three different channels conditions with frequency response.Figure 19 shows the example that the example of the embodiment of Fig. 7 is implemented according to emulation, three receiver LEQ frequency response of exemplary embodiment feedback circuit is provided.Figure 20 shows for each aggregate channel and the receiving machine frequency response figure in three kinds of situations.In Figure 20, use the advantage of these embodiment as can be seen, it is smooth that total frequency response keeps, and for each frequency response spread bandwidth so that bandwidth more uniformly to be provided.
Figure 21 and Figure 22 also show the result who obtains in the emulation of using exemplary embodiment of the present.In Figure 21,, show the voltage pattern of received signal at the receiver of the LEQ that does not have exemplary embodiment of the present.In Figure 22, show voltage pattern for the self adaptation feedback signal that LEQ received that uses the embodiment of the invention.As shown in figure 22, when the circuit of using the embodiment of the invention and method, significantly improved signal eye.
Although describe the present invention and advantage thereof in detail, should be appreciated that, under the situation that does not deviate from the spirit and scope of the present invention that are defined by the following claims, can carry out various changes, replacement and change.For example, it is apparent to those skilled in the art that and to change method and keep simultaneously within the scope of the present invention.
In addition, the application's the scope method that is not limited to describe in the specification and the specific embodiment of step.Those skilled in the art openly can easily understand according to of the present invention, can utilize according to the present invention existing or exploitation after a while, compare the essentially identical function of execution with the corresponding embodiment of describe or realize essentially identical result's processing or step.Therefore, claims are included in the scope such as this processing or step.
Claims (15)
1. device that is used to receive differential signal comprises:
Receiver is connected to a pair of input that is used to receive differential signal;
Linear equalizer is used for providing frequency compensation to recover received signal because the caused loss of Channel Transmission;
Data recovery circuit is connected to the output of described linear equalizer, and the analog signal conversion that is configured to receive is a digital form and according to described digital form restore data and the clock signal that received, and has numeral output; And
Feedback circuit, be connected to described numeral output and be connected at least one voltage comparator that the output of described linear equalizer is sampled, it is configured to export feedback control signal to export the frequency response of revising described linear equalizer in response to described numeral output and at least one comparator.
2. device according to claim 1, wherein, described linear equalizer also comprises:
First input is used to revise the peak gain frequency (Fgp) that is used for described linear equalizer;
Second imports, and is used to revise the maximum gain (Gmax) of described linear equalizer; And
The 3rd imports, and is used to revise the described maximum gain and the gain inequality between the least gain (Δ G) of described linear equalizer.
3. device according to claim 1, wherein, described at least one comparator also comprises:
Sampling and keep amplitude comparator is configured to receive the simulation output of described linear equalizer, and whether the amplitude that is configured to export the signal that expression receives surpass the signal of first threshold voltage, and described device also comprises:
At least one additional amplitude sampling and maintenance comparator are used to receive the simulation output of described linear equalizer, and are configured to export the signal whether amplitude of representing described signal surpasses second threshold voltage.
4. device according to claim 1, wherein, described feedback circuit also comprises:
The data pattern match circuit, be configured to export expression from the numerical data of described data recovery circuit output when with the signal of preset pattern coupling;
The data accumulator circuit is configured to cumulative data, and is connected to described data pattern match circuit and described at least one comparator; And
Digital filter is connected to described data accumulator circuit, is configured to export described feedback control signal,
Wherein, described data accumulator circuit also comprises:
First accumulator is configured to carry out data accumulation when described data pattern coupling is represented the pattern relevant with described peak gain frequency Fgp;
Second accumulator is configured to carry out data accumulation when described data pattern coupling is represented the pattern relevant with described maximum gain Gmax; And
The 3rd accumulator is configured to carry out data accumulation when described data pattern coupling is represented the pattern relevant with described gain inequality Δ G.
5. device according to claim 1 also comprises:
Serial input and line output circuit are connected to described data recovery circuit, are configured to receive serial digital data stream and export parallel data, and wherein, described at least one comparator is to sample less than the speed of data clock speed.
6. device according to claim 1, wherein, sample rate is less than 1/2 of described data clock rate.
7. integrated circuit that is used on the differential signal channel link receiving serial signal comprises:
A pair of input is used to receive analog difference signal;
Receiver circuit is connected to described a pair of input, and comprises the linear equalization circuit, is configured to export the signal as frequency response compensate for poor sub-signal, and has at least three control inputs;
Data recovery circuit is connected to the output of described linear equalizer, and the analog signal conversion that is configured to be received is digital form, and is configured to according to described digital form restore data and the clock signal that received, and has digital signal output; And
Feedback circuit, be connected to described digital signal output and be connected at least one voltage comparator that the analog signal output of described linear equalizer is sampled, be configured to export at least three feedback control signals to export the frequency response of revising described linear equalizer in response to described numeral output and at least one comparator.
8. integrated circuit according to claim 7, wherein, described linear equalizer also comprises:
First input is used to revise the peak gain frequency (Fgp) that is used for described linear equalizer;
Second imports, and is used to revise the maximum gain (Gmax) of described linear equalizer; And
The 3rd imports, and is used to revise the described maximum gain and the gain inequality between the least gain (Δ G) of described linear equalizer.
9. integrated circuit according to claim 7, wherein, described at least one voltage comparator also comprises:
Sampling and keep amplitude comparator is configured to receive the simulation output of described linear equalizer, and whether the amplitude that is configured to export the signal that expression receives surpasses the signal of first threshold voltage.
10. integrated circuit according to claim 7, wherein, described feedback circuit also comprises:
The data pattern match circuit, be configured to export expression from the numerical data of described data recovery circuit output when with the signal of preset pattern coupling;
The data accumulator circuit is configured to cumulative data, and is connected to described data pattern match circuit and described at least one comparator; And
Digital filter is connected to described data accumulator circuit, is configured to export described feedback control signal,
Wherein, described data accumulator circuit also comprises:
First accumulator is configured to carry out data accumulation when described data pattern coupling is represented the pattern relevant with described peak gain frequency Fgp;
Second accumulator is configured to carry out data accumulation when described data pattern coupling is represented the pattern relevant with described maximum gain Gmax; And
The 3rd accumulator is configured to carry out data accumulation when described data pattern coupling is represented the pattern relevant with described gain inequality Δ G.
11. integrated circuit according to claim 7 also comprises further user designation number logical circuit, is used to receive the numerical data by described data recovery circuit output.
12. a method that is used for receiving differential signal on the serial channel link comprises:
Receive a pair of differential analog signal;
Carry out linear equalization, providing, thereby compensate the loss of signal in the described channel link as frequency compensated analog output signal;
The execution data are recovered, and so that described analog output signal is converted to digital form, and extract clock signal and digital data signal from described analog output signal, and export described digital data signal;
In first amplitude comparator, described analog output signal is sampled, and when the described analog output signal of output expression surpasses the signal of predetermined threshold; And
Use feedback, revise the characteristic of described linear equalization, to obtain the expectation overall frequency response of described analog output signal.
13. method according to claim 12 wherein, uses feedback also to comprise:
Observe described digital data signal and discern pattern, and the signal of the pattern that observed of output expression;
In response to the pattern that is observed data accumulation is carried out in the output of amplitude comparator; And
Combine digital filtering is also exported control signal, to revise described linear equalization.
14. method according to claim 12 wherein, is revised characteristic and is also comprised at least one following step:
Revise the peak gain frequency Fgp of described linear equalization;
Revise the maximum gain Gmax of described linear equalization; And
Revise the maximum gain of described linear equalization and the gain inequality Δ G between the least gain.
15. method according to claim 12 also comprises:
In second amplitude comparator, described analog output signal is sampled, and exports the signal when described analog output signal of expression surpasses second predetermined threshold,
Wherein, carry out sampling with 1/2 speed less than bit rate clock signal.
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| US16398509P | 2009-03-27 | 2009-03-27 | |
| US61/163,985 | 2009-03-27 | ||
| US12/633,533 US8111792B2 (en) | 2009-03-27 | 2009-12-08 | Apparatus and methods for digital adaptive equalizer in serial receiver |
| US12/633,533 | 2009-12-08 |
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