CN101848007B - Apparatus and methods for digital adaptive equalizer in serial receiver - Google Patents
Apparatus and methods for digital adaptive equalizer in serial receiver Download PDFInfo
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Abstract
Circuits and methods for performing adaptive frequency compensation in a serial receiver coupled to a differential signal channel link are disclosed. In an exemplary embodiment, a receiver for signals over a serial channel link is provided including a linear equalization function. A data recovery circuit is coupled to the output of the receiver and receives frequency compensated analog signals. A digital feedback control circuit observes the digital output. A data accumulator circuit receives the output of a comparator and a signal indicating the data pattern observed in the digital data output. A digital filter receives the accumulator data and outputs control signals for modifying the linear equalization in a feedback loop. The receiver and linear equalization function are automatically and adaptively modified to provide frequency compensation. Methods for adaptively modifying the frequency response of a receiver and linear equalizer using digital feedback are disclosed.
Description
It is the U.S. Provisional Application the 61/163rd of " Apparatus and Methodsfor Digital Adaptive Equalizer in Serial Receiver " that the application requires in the title that on March 27th, 2009 submitted to, the priority of No. 985, its full content combination therewith as a reference.
Technical field
The present invention relates to be used to the circuit that improved integrated circuit (IC) design is provided and method and be used for providing method for the receiver of differential input signal.The use of serial-unstringing (SerDes) data link is being known in the art, wherein, the numerical data digit data stream that is changed to serial data stream, clock control, converts analog signal to, use the transmission of difference signaling channel link, be received as analog signal, recovered clock information and be received from clock control by receiver.Then, the deserializer output digital data is used in receiving equipment.Channel has the significant loss of signal, especially at high frequency.Therefore, use linear equalizer to lose with compensate for channel in receiver.Embodiments of the invention provide the linear equalizer that utilizes in the integrated circuit that uses various transmitters and channel to realize the advantage of this receiver.
Background technology
At present, be used for realizing the receiver of differential signal in the integrated circuit that uses analog circuit.For example, Fig. 1 shows the system diagram of the existing transmitter 11 of typical case that is connected to link channel 13, and link channel 13 is used for differential signal is sent to receiver 15.Receiver may be implemented as in integrated circuit, on circuit board or the receiver in a plurality of integrated circuit and AFE (analog front end) (RXAFE).Receiver extracts the data that receive from analog difference signal, and after some are processed, can export the digital data signal that receives by receiver.Can use the known self clock technology of prior art in the SerDes link.
When the analog receiver circuit is integrated circuit a part of, the parameter that changes the analogue component that uses in the receiver difficulty that becomes.Some known existing methods employing external components compensate the response for the receiver of different channels and transmitter.Some known methods can comprise adjusts the interior resistor of chip etc.These adjustment or tuning methods are not adaptive for the change after a while in system.That is, if receiver ic is connected to after a while different channel links or different transmitter or has the channel of time-varying characteristics, the integrated receiver of prior art can be subsequently be optimized for the environment of mistake.
Fig. 2 (a) shows the exemplary frequency response curve for channel link.As known to those skilled in the art, channel loss occurs in transmission channel, and this causes the gain loss (amplitude decline) in channel, especially on characteristic frequency.These losses may due to several factor, include but not limited to kelvin effect, dielectric coupling loss and other transmission losses.Total channel loss seems to be similar to the frequency response of low pass filter.In order to lose in the channel that compensates received signal, receiver should be used as high pass filter (aspect frequency response).Fig. 2 (b) shows the desired frequency response of the receiver that is connected to channel.By providing gain with correct frequency, receiver can be the signal compensation channel loss that receives, and in conveyer, they is returned to original amplitude.Therefore, the receiving machine frequency response of expectation and the channel loss in channel frequency response be complementary and the compensate for channel frequency response in channel loss.The overall frequency response of the expectation of channel and receiver is a kind of in smooth loss and bandwidth expansion.
Fig. 3 shows the example combination frequency response of channel response in Fig. 2 (a) and the response of the receiver in Fig. 2 (b).Amplitude upward keeps constant and has compensated the channel loss effect in frequency range (smooth loss), and signal amplitude is remained on the upper frequency (bandwidth expansion) that channel loss will occur.
Receiving machine frequency response represents by the linear equalization function (LEQ) in receiver AFE (analog front end) (RXAFE) circuit.LEQ should be complementary with channel frequency response ideally.By the curve in Fig. 4, this concept is shown.In the top view that the curve that is designated as " channel 1 ", " channel 2 " and " channel 3 " is shown, show the frequency response for three different channels, wherein, receiver circuit and analog front circuit RXAFE should be connected to this three different channels.Each channel has different channel loss characteristics.In the diagram of bottom, show the receiver LEQ frequency response that needs in these three channels of compensation each.If receiver utilizes various channel conditions to operate, LEQ should be adaptive with different loss properties or different channels in compensate for channel.
The LEQ frequency response has at least 3 important components, as shown in the response curve in Fig. 5.Gain peak frequency Fgp is a kind of target property and the frequency that has represented to obtain most of receiver gains.For compensate for channel loss, its should with the frequency dependence that causes the channel loss in channel frequency response.The Gmax characteristic represents to comprise needed maximum gain in the receiver of LEQ.Δ G characteristic is the gain inequality that needs between height and the response of low frequency receiver.Typically, in stability at lower frequencies, channel loss is not very remarkable, so receiver does not need to have the gain for these parts of received signal.
Figure 6 illustrates the method for the prior art that receiver function is provided.Channel 13 is shown as and is connected to receiver function 60.This receiver function can be the one or more integrated circuits on circuit board, and discrete circuit or increasing receiver function can be to comprise such as the ASIC of other functions of signal processor etc. or the part of SOC integrated circuit.Receiver front end 63 comprises analog receiver and the linear equalizer function that prior art is known.Then, analog signal is transferred to clock and data recovery piece 65 in couples, it includes but not limited to analog to digital converter, clock recovery circuitry.Then, the serial data stream of recovery is converted to parallel data by serial input-parallel output circuit (SIPO) 67, and circuit 67 can be implemented as FIFO, circular buffer, shift register or other Digital Logical Circuits known in the art.
The input of receiver front end 63 is denoted as (1), (2) and (3), and expression is used for changing the input of above-mentioned three characteristics (that is, peak gain frequency Fgp, peak signal gain G max and gain inequality Δ G).Must provide these inputs by external circuit or additional internal circuit.These inputs of the prior art are selected with respect to channel frequency response by adjustment or calibration process (for example, being fixed).If channel response changes with temperature or other variations occur, if perhaps receiving equipment is connected to different channels, the circuit that drives these inputs should be changed, otherwise the response of receiver LEQ no longer can the compensate for channel loss.
Use the increase trend of integrated circuit to increase demand to the receiver of regulating adaptively to provide correct compensation in the analog receiver that is formed for the serial differential channel communication.
Therefore, lasting needs can solve the improving one's methods and circuit of these and other problems of prior art receiver.
Summary of the invention
By embodiments of the invention, usually solve or avoided these and other problems and usually realized technological merit, embodiments of the invention provide: a kind of receiver provides linear equalization for the signal that receives from the differential channel link adaptively; And a kind of method, the variation in automatically compensate for channel frequency response, and need not additional calibration or adjustment.Receiver combines the digital feedback function to provide automatically and the self adaptation operation.
In the first exemplary embodiment of the present invention, provide the receiver that is used for receiving differential signal on the serial channel link.This receiver includes linear equalization function.Data recovery circuit is connected to output and the receive frequency compensating analog signal of receiver.Carry out analog-to-digital conversion and clock recovery, obtain digital output signal.Carry out and go here and there and change with the output parallel data signal.The output of digital feedback control circuit observation data.At least one amplitude comparator is connected to the output of linear equalization function.The data accumulator circuit receives the output of comparator and is illustrated in data pattern (pattern, signal pattern) that observes in numerical data output.Digital filter receives accumulator data and exports the control signal of the linear equalization that is used for the modification feedback control loop.Receiver and linear equalization function are revised to provide the frequency compensation to the loss of signal in channel link automatically and adaptively.
In one approach, differential signal is received on the serial channel link, and carries out linear equalization with output frequency compensating analog signal.Analog signal is carried out analog-to-digital conversion, and recover numerical data and clock signal.Carry out Amplitude Comparison to determine whether analog signal amplitude surpasses at least one predetermined threshold.Process the output digital feedback signal with the characteristic of linear adjustment equilibrium and provide self adaptation and automatic frequency compensation method by digital filtering.
Front summary is also wide in range has described feature of the present invention and technological merit, thus the detailed description that the present invention may be better understood below.This summary of the invention part has briefly been described certain exemplary embodiments of the present invention, but the present invention is not limited only to these exemplary embodiments.
Below will describe supplementary features of the present invention and advantage, it forms the theme of claim of the present invention.It should be appreciated by those skilled in the art, disclosed concept can easily be used with specific embodiment and make an amendment or be designed for other structures of the execution purpose identical with the present invention or the basis of processing.Those skilled in the art be also to be understood that this equivalent constructions does not deviate from the spirit and scope of the present invention of claims.
Description of drawings
For complete understanding the present invention and advantage thereof, carry out following description referring now to accompanying drawing, wherein:
Fig. 1 shows receiver, transmitter and the link channel of prior art;
Fig. 2 (a) shows the channel frequency response curve of prior art, and Fig. 2 (b) shows the receiving machine frequency response of prior art;
Fig. 3 shows for the receiver of Fig. 2 (a) and Fig. 2 (b) and the combination frequency response curve of channel;
Fig. 4 shows for the frequency response curve of three kinds of channel conditions and the desired frequency response that is used for the linear equalizer of three kinds of channel conditions;
Fig. 5 shows in detail the channel frequency response curve for the prior art linear equalizer;
Fig. 6 shows receiver and the interlock circuit in prior art scheme block diagram;
Fig. 7 shows the exemplary embodiment of receiver of the present invention with block diagram;
Fig. 8 illustrates three kinds of signal eye conditions with voltage time;
Fig. 9 shows the digital feedback control unit of the embodiment of Fig. 7 with block diagram;
Figure 10 shows the function of data pattern matching unit of the digital feedback control unit of Fig. 9 with block diagram;
Figure 11 illustrates trigger (toggle) measuring ability with simple logic;
Figure 12 shows data-signal pattern corresponding to the first group identifier with timing diagram;
Figure 13 shows data-signal pattern corresponding to the second group identifier with timing diagram;
Figure 14 shows data-signal pattern corresponding to the 3rd group identifier with timing diagram;
Figure 15 shows data-signal pattern corresponding to the 4th group identifier with timing diagram;
Figure 16 shows the function of data accumulator of the digital feedback control unit of Fig. 9 with block diagram;
Figure 17 shows the function of digital filter of the digital feedback control unit of Fig. 9 with block diagram;
Figure 18 shows three kinds of channel conditions that use in emulation with another frequency response curve;
Figure 19 shows the response that utilizes the linear equalizer of the embodiment of the present invention for three curves of Figure 18 with another frequency response curve;
Figure 20 shows the combination frequency response curve of curve that has for each of three kinds of channel conditions of Figure 18 and Figure 19 and three linear equalizer emulation;
Figure 21 shows the signal eye diagram that does not use the embodiment of the present invention and obtain; And
Figure 22 shows the signal eye diagram that obtains for receiver example of the present invention.
Accompanying drawing, illustrative diagram are only exemplary, are not limited to the example of the embodiment of the present invention, and for exemplary purpose, they are simplified, and needn't draw in proportion.
Embodiment
The below discusses manufacturing and the use of the preferred embodiment of the present invention in detail.Yet, should be appreciated that, the invention provides many applicable concepts that can realize in various specific environments.The specific embodiment of discussing is only the signal of making and use concrete mode of the present invention, limits the scope of the invention and be not used in.
Fig. 7 shows the exemplary embodiment in conjunction with the receiver circuit of feature of the present invention.For example, receiver 70 may be implemented as a part, the integrated circuit that use ASIC, SOC or traditional design technology as the larger integrated circuit that is combined with optional feature and circuit; For example, in transceiver or systems approach integrated circuit, perhaps as the circuit board that is combined with some integrated circuits or discrete circuit.Each of these optional realizations is all expected as the part of embodiment, and is fallen in the scope of claims.Use in-line memory and other designing techniques that the specific part of receiver 70 is divided into digital integrated circuit, analog integrated circuit, software and programmable processor, this is divided all within the scope of the appended claims.Composite signal integrated circuits can be used for realizing receiver 70.Useful semiconductor processes is made composite signal integrated circuits, device is optimized for the analog functuion such as analog receiver, operational amplifier etc., and additional device is optimized for the digital function such as Digital Logic, digital filter, digital processing unit etc.Then, can be arranged on single piece of silicon as integrated circuit by the device that these are different.Can use the multi-chip package method, wherein, individual devices or module are formed and comprise the analog-and digital-integrated circuit that is joined together to form receiver 70.
Fig. 8 shows the signal amplitude comparator 79 of Fig. 7 and 83 operation with simple timing diagram.Comparator compares one from the amplitude of the differential signal of receiver front end 73 output and two voltage references.In Fig. 7, comparator 79 receiver voltage benchmark Vreference1.Comparator 83 receives Vreference2.These amplitude comparators can use known sampling and keep analog comparator circuit (such as at paper (the IEEE J.Solid-StateCircuits of people's titles such as Lee for " LOW-POWER AREA-EFFICIENTHIGH-SPEED I/O CIRCUIT TECHNIQUES ", volume 35, o.11,2000,1596 pages) the middle circuit of describing) form, it is as the limiting examples of sampling and holding circuit.Can also use other known samplings and keep comparator.
In Fig. 8, amplitude and these voltage references of the signal eye (signal eye) that will form on the zero crossing interval of the time-varying input signal that receives compare.Suitably to the loss of received signal compensate for channel, the amplitude of received signal will be greater than voltage threshold Vreference1 and Vreference2 as receiver LEQ 73.If compensate insufficiently, amplitude can be greater than less threshold value but less than larger threshold voltage.If the compensation in receiver 73 is more inadequate, the amplitude of received signal eye can be more lower than low threshold value.The output of two comparators is used to determine whether three feedback control signals need to change to change receiver LEQ 73 frequency responses.In requiring the optional embodiment of less silicon, only use a comparator and a voltage reference.
Comparator circuit can fully operate under the sample frequency less than data transfer rate.For example, the comparator sample frequency can be low to moderate 1/20 of data transfer rate, and is perhaps high to 1/2,1/4,1/8 or 1/16 of data transfer rate.The lower frequency comparator is simpler for design and implementation, uses less power and less silicon area, is therefore favourable.Use for specific design, if allow power and area sources to consider, certainly can also use than the high sampling rate comparator.Even utilize the lower frequency comparator to realize the advantage of embodiment.Comparator output provides the watch-dog of channel and LEQ combination overall frequency response.When the signal eye amplitude was higher for a plurality of reception signals, it was good that receiver LEQ arranges, and for the particular channel condition, the expectation purpose of smooth loss and spread bandwidth is satisfied in the combination frequency response.When signal eye had short arc, receiver LEQ need to be conditioned.Short arc means that the combination frequency response is not used in the optimization channel condition.
The output of two comparators is connected to digital control feedback unit 81.Fig. 9 shows digital control feedback unit 81 with the block diagram form.Digital control feedback unit 81 comprises the three functions piece.Data pattern matching unit 92 receives the data flow from SIPO circuit 77, and executing data pattern matching feature as described further below.The data pattern matching unit provides m output Gr (m-1:0).In group output Gr one is that in high or four the possible group data pattern of " 1 " expression of logic, which is detected by piece 92.Receive group expression information Gr by data accumulator 94.There is m accumulator in data accumulator 94.Shown in this example of describing, have at least three data accumulators, one is used for each of three feedback control functions.Each accumulator in data accumulator 94 is exported the accumulator signal Ac of k bit wide.In exemplary embodiment described in detail here, the directed peak gain frequency Fgp control signal of accumulator; One is pointed to maximum gain Gmax control signal; And the 3rd directed Δ G of accumulator gain inequality control signal.
Then, the Ac of the k bit wide of three accumulators output is connected to digital filter functions 96.Digital filter functions is designed or is programmed for the correction feedback control output that the output of based on data accumulator generates the LEQ frequency response that is used for optimization of receiver algorithms front end 73.Digital filter can be set up as the hardware capability that uses circuit, perhaps alternatively as the program of being carried out by programmable digital processor (such as digital signal processor), perhaps can use their combination.
In operation, three of digital control feedback unit 81 kinds of functions one work to export three feedback control signals in response to the observation signal from receiver front end.In this self adaptation feedback control loop, digital feedback control function automatically the change control signal processing the frequency response of receiver LEQ 73, thereby compensate total channel frequency response and the response of the combination frequency with smooth loss and spread bandwidth characteristic be provided.Change in transmitter or channel or change receiver receive different channels by digital control feedback unit auto-compensation.
Figure 10 simply shows the operation of an example of data pattern matching feature 92 enforcements, and it makes a distinction four preset pattern groups and the data flow that receives.Show the order of received data stream with timeline 80 bottom the block diagram of Figure 10.The data D[n-1:0 of " t " constantly] formed parallel word Dt[0] ..., Dt[n-1].Constantly " t-1 " data formation of receiving parallel word Dt-1[0] ..., Dt-1[n-1].The parallel group of these of serial received data is exported by the SIPO unit, and fclk1 is synchronizeed with clock.Output data bus Gr[m-1:0] the current pattern matching result of expression, note, clock fclk1 is identical with the speed of fclk1.Gr[m-1:0] will upgrade with the fclk1 clock frequency.
In operation, the data pattern matching feature 92 trigger pattern in specified data stream at first.Figure 11 shows an example of the trigger pattern detector of data pattern matching feature 92 uses and implements.A plurality of xor functions are connected in series and by each data bit D is compared to form trigger consequential signal (TR) with its nearest neighbours.By this way, there are data (trigger) to zero in the serial data stream that is received by SIPO or from zero to one variation, can be confirmed as trigger.Note, trigger TR is as a result inputted with matched data by time index.
Each group of four groups (in this illustrative examples, use four groups, but can also be more) all corresponding to the one or more predetermined data pattern in the data flow that is received by SIPO.Data pattern matching feature 92 must according to the trigger of constantly " t " as a result TR determine group identifier.In an exemplary enforcement, this information is at m bit wide group bus Gr[m-1:0] upper output is as proprietary code, and the Gr bus only has a quilt " set " or is height.Can also use other codes.
Figure 12 shows the example of " group 1 " pattern.In Figure 12, show trigger TR as a result in the bottom of figure.TR field TRt-1[n-2] ... TRt[2] in pattern " 00110 " expression group 1 pattern.In Figure 13, from TRt-1[n-2] ... TRt[2], the pattern in the trigger result field TR of " x1111x " or " x1100x " or " x1100x " represents to organize 2 patterns.
Figure 14 shows the example of group 3 patterns.Similarly, Figure 15 shows the example of group 4 patterns.
The pattern of expression group 1 concentrates on gain peak frequency Fgp.The pattern of expression group 2 concentrates on maximum gain Gmax.Expression group 3 concentrates on the relevant pattern of Δ G with 4 pattern.Which accumulator that the output of data pattern matching feature illustrates in the data accumulator function should work.Have three accumulators, one is used for each of feedback control signal.These accumulator cross-references.
Therefore, the combination by the XOR computing detect four patterns each with identification trigger position and with pattern matching feature 92 in storage, comparison preset pattern.In this example, output signal Gr is single position effective code, so if organizing 1 is identified in the pattern that moment t sees, arrange from signal Gr[m-1:0] position 0, other are set to zero.Be identified if organize 2, position 1 is set, and position Gr[m-1:2] and Gr[0] be zero.Similarly coding is used to indicate group 3 or organizes 4 pattern couplings.
In data accumulator function 94, comparator input (if use two comparators, being a plurality of inputs) is relevant to picture group sample coupling.Whether the LEQ receiving machine frequency response that comparator input expression is combined with channel frequency response is fully compensated.
Figure 16 shows the internal frame diagram of the exemplary enforcement of data accumulator function 94.The data accumulator function receives group identifier signal Gr and clock signal fclk2.Data accumulator has m bidirectional counter (or forward-backward counter), and each has " k " position and is used for counting.These variablees allow to design flexibly.For concrete enforcement as described herein, have 3 bidirectional counters, each that is suitable for for the control signal of controlling self adaptation LEQ.Therefore, in this example, m is 3.Can select as required based on clock frequency and design parameter the value of k; Certainly, the k of lower value causes less counter, and therefore, less transistor and silicon area are used for the accumulator function.For each the clock fclk2 that is provided with corresponding Gr position, the comparator input tells counter to increase progressively counting or countdown.The form of accumulator output is signal Ac_0[k-1:0] ... Ac_m-1[k-1:0].
In operation, based on the input of at that time comparator, bidirectional counter subtracts 1 or add 1.Select effective bidirectional counter by the position that arranges in group signal Gr.Typically, subtract 1 by carrying out to current counting added value 111....0.Add 1 by carrying out to current counting increase 000...01.Preferably, utilization is overflowed with underflow and is protected to implement counter.That is, when the border is overflowed in the counter touching, it will no longer increase.When counter touching underflow border, it will no longer reduce.Although do not lost some information because counting changes until Counter Value no longer touches boundary condition, underflow or overflow error during this has prevented from calculating.
Figure 17 shows the exemplary enforcement of digital filter functions 96 with block diagram.Divider is used to divided by the accumulator value that enters to form less output area.Formed digital filter signal Df_0 ... Df_m-1.Each digital filter signal is corresponding accumulator signal Ac[k-1:0 substantially] subtract from the Ac signal " j " position highest significant position (MSB).This effectively with the Ac signal divided by the value 2j.Counter of the correspondence of divider 961 and 962 from data accumulator 94 receives the Ac signal, and output is corresponding to the Df signal of position [k-1-j:0].Then, digital filter is converted to this Df bus heat code (thermal code) or thermometer-code in piece 963.In this illustrative examples, have three feedback control signals; One is used for the LEQ crest frequency, and one is used for LEQ maximum gain Gmax, and one is used for LEQ Δ G.In other exemplary application, can use more feedback signal, data accumulator, divider and hot code generator all will be with each output signals that is to use in feedback control loop.
Figure 18 illustrates the simulated example set of three different channels conditions with frequency response.Figure 19 shows the example that the example of the embodiment of Fig. 7 is implemented according to emulation, three receiver LEQ frequency response of exemplary embodiment feedback circuit is provided.Figure 20 shows for each aggregate channel and the receiving machine frequency response figure in three kinds of situations.In Figure 20, can find out the advantage of using these embodiment, it is smooth that total frequency response keeps, and for each frequency response spread bandwidth so that bandwidth more uniformly to be provided.
Figure 21 and Figure 22 also show the result that obtains in the emulation of using exemplary embodiment of the present.In Figure 21, for the receiver of the LEQ that does not have exemplary embodiment of the present, show the voltage pattern of received signal.In Figure 22, the signal that receives for the self adaptation feedback LEQ that uses the embodiment of the present invention shows voltage pattern.As shown in figure 22, when the circuit of using the embodiment of the present invention and method, significantly improved signal eye.
Although describe the present invention and advantage thereof in detail, should be appreciated that, in the situation that do not deviate from the spirit and scope of the present invention that are defined by the following claims, can carry out various changes, replacement and change.For example, it is apparent to those skilled in the art that and to change method and keep simultaneously within the scope of the present invention.
In addition, the application's the scope method that is not limited to describe in specification and the specific embodiment of step.Those skilled in the art openly can easily understand according to of the present invention, can utilize according to the present invention existing or exploitation after a while, compare the essentially identical function of execution with the corresponding embodiment of describe or realize processing or the step of essentially identical result.Therefore, claims are included in scope such as this processing or step.
Claims (15)
1. device that be used for to receive differential signal comprises:
Receiver is connected to for a pair of input that receives differential signal;
Linear equalizer is used for providing frequency compensation to recover received signal due to the caused loss of transmission;
Data recovery circuit is connected to the output of described linear equalizer, and the analog signal conversion that is configured to receive is digital form and recovers data and the clock signal that receives according to described digital form, and has numeral output; And
Feedback circuit, be connected to described numeral and export and be connected at least one voltage comparator that the output of described linear equalizer is sampled, it is configured to export feedback control signal to export to revise the frequency response of described linear equalizer in response to described numeral output and at least one comparator.
2. device according to claim 1, wherein, described linear equalizer also comprises:
The first input is used for revising the peak gain frequency (Fgp) that is used for described linear equalizer;
The second input is for the maximum gain (Gmax) of revising described linear equalizer; And
The 3rd input is for described maximum gain and the gain inequality between least gain (Δ G) of revising described linear equalizer.
3. device according to claim 1, wherein, described at least one comparator also comprises:
Sampling and amplitude reserving comparator are configured to receive the simulation output of described linear equalizer, and whether the amplitude that is configured to export the signal that expression receives over the signal of first threshold voltage, and described device also comprises:
At least one additional amplitude sampling and maintenance comparator are used for receiving the simulation output of described linear equalizer, and are configured to export the signal whether amplitude that represents described signal surpasses Second Threshold voltage.
4. device according to claim 1, wherein, described feedback circuit also comprises:
The data pattern match circuit, be configured to export expression from the numerical data of described data recovery circuit output when with the signal of preset pattern coupling;
The data accumulator circuit is configured to cumulative data, and is connected to described data pattern match circuit and described at least one comparator; And
Digital filter is connected to described data accumulator circuit, is configured to export described feedback control signal,
Wherein, described data accumulator circuit also comprises:
The first accumulator is configured to that executing data adds up when the described data pattern coupling expression pattern relevant to peak gain frequency Fgp;
The second accumulator is configured to that executing data adds up when the described data pattern coupling expression pattern relevant to maximum gain Gmax; And
The 3rd accumulator is configured to that executing data adds up when the described data pattern coupling expression pattern relevant to gain inequality Δ G.
5. device according to claim 1 also comprises:
The serial input-parallel output circuit is connected to described data recovery circuit, is configured to receive serial digital data stream and exports parallel data, and wherein, described at least one comparator is to sample less than the speed of data clock speed.
6. device according to claim 1, wherein, sample rate is less than 1/2 of the data clock rate.
7. integrated circuit that is used for receiving serial signal on the differential signal channel link comprises:
A pair of input is used for receiving analog difference signal;
Receiver circuit is connected to described a pair of input, and comprises linear equalizer, is configured to export the signal as frequency response compensate for poor sub-signal, and has at least three control inputs;
Data recovery circuit is connected to the output of described linear equalizer, and the analog signal conversion that is configured to receive is digital form, and is configured to the clock signal recovering data and receive according to described digital form, and has digital signal output; And
Feedback circuit, be connected to described digital signal and export and be connected at least one voltage comparator that the analog signal output of described linear equalizer is sampled, be configured to export at least three feedback control signals to export to revise the frequency response of described linear equalizer in response to described numeral output and at least one comparator.
8. integrated circuit according to claim 7, wherein, described linear equalizer also comprises:
The first input is used for revising the peak gain frequency (Fgp) that is used for described linear equalizer;
The second input is for the maximum gain (Gmax) of revising described linear equalizer; And
The 3rd input is for described maximum gain and the gain inequality between least gain (Δ G) of revising described linear equalizer.
9. integrated circuit according to claim 7, wherein, described at least one voltage comparator also comprises:
Sampling and amplitude reserving comparator are configured to receive the simulation output of described linear equalizer, and whether the amplitude that is configured to export the signal that expression receives is over the signal of first threshold voltage.
10. integrated circuit according to claim 7, wherein, described feedback circuit also comprises:
The data pattern match circuit, be configured to export expression from the numerical data of described data recovery circuit output when with the signal of preset pattern coupling;
The data accumulator circuit is configured to cumulative data, and is connected to described data pattern match circuit and described at least one comparator; And
Digital filter is connected to described data accumulator circuit, is configured to export described feedback control signal,
Wherein, described data accumulator circuit also comprises:
The first accumulator is configured to that executing data adds up when the described data pattern coupling expression pattern relevant to peak gain frequency Fgp;
The second accumulator is configured to that executing data adds up when the described data pattern coupling expression pattern relevant to maximum gain Gmax; And
The 3rd accumulator is configured to that executing data adds up when the described data pattern coupling expression pattern relevant to gain inequality Δ G.
11. integrated circuit according to claim 7 also comprises further user designation number logical circuit, is used for receiving the numerical data by described data recovery circuit output.
12. a method that is used for receiving differential signal on the serial channel link comprises:
Receive a pair of differential analog signal;
Carry out linear equalization, being provided as frequency compensated analog output signal, thereby compensate the loss of signal in described channel link;
Executing data recovers, and so that described analog output signal is converted to digital form, and extracts clock signal and digital data signal from described analog output signal, and exports described digital data signal;
In the first amplitude comparator, described analog output signal is sampled, and when the described analog output signal of output expression surpasses the signal of the first predetermined threshold; And
Based on the described digital data signal use the feedback when described analog output signal of the expression of exporting surpasses the signal of the first predetermined threshold and export, revise the characteristic of described linear equalization, to obtain the expectation overall frequency response of described analog output signal.
13. method according to claim 12 wherein, uses feedback also to comprise:
Observe described digital data signal and identify pattern, and the signal of the pattern that observes of output expression;
Cumulative to the output executing data of amplitude comparator in response to the pattern that observes; And
Combine digital filtering is also exported control signal, to revise described linear equalization.
14. method according to claim 12 wherein, is revised characteristic and is also comprised at least one following step:
Revise the peak gain frequency Fgp of described linear equalization;
Revise the maximum gain Gmax of described linear equalization; And
Revise the maximum gain of described linear equalization and the gain inequality Δ G between least gain.
15. method according to claim 12 also comprises:
In the second amplitude comparator, described analog output signal is sampled, and exports the signal when described analog output signal of expression surpasses the second predetermined threshold,
Wherein, carry out sampling with 1/2 speed less than bit rate clock signal;
When further comprise over the signal of the first predetermined threshold and the described digital data signal use feedback of exporting based on the described analog output signal of the expression of exporting: when when feed back over the signal of the second predetermined threshold and the described digital data signal use of exporting over the signal of the first predetermined threshold, the described analog output signal of expression of exporting based on the described analog output signal of the expression of exporting.
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| US16398509P | 2009-03-27 | 2009-03-27 | |
| US61/163,985 | 2009-03-27 | ||
| US12/633,533 US8111792B2 (en) | 2009-03-27 | 2009-12-08 | Apparatus and methods for digital adaptive equalizer in serial receiver |
| US12/633,533 | 2009-12-08 |
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| CN106411797B (en) * | 2016-08-31 | 2019-12-03 | 硅谷数模半导体（北京）有限公司 | The adaptive equilibrium method and device of receiver |
| CN106453168B (en) * | 2016-08-31 | 2019-12-03 | 硅谷数模半导体（北京）有限公司 | The adaptive equilibrium method and device of receiver |
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| TWI763459B (en) * | 2021-04-23 | 2022-05-01 | 瑞昱半導體股份有限公司 | Switch device and signal adjusting method thereof |
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