CN106453168B - The adaptive equilibrium method and device of receiver - Google Patents
The adaptive equilibrium method and device of receiver Download PDFInfo
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- CN106453168B CN106453168B CN201610792058.3A CN201610792058A CN106453168B CN 106453168 B CN106453168 B CN 106453168B CN 201610792058 A CN201610792058 A CN 201610792058A CN 106453168 B CN106453168 B CN 106453168B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
- H04L25/03885—Line equalisers; line build-out devices adaptive
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/12—Neutralising, balancing, or compensation arrangements
- H04B1/123—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03891—Spatial equalizers
- H04L25/03949—Spatial equalizers equalizer selection or adaptation based on feedback
Abstract
The invention discloses a kind of adaptive equilibrium method of receiver and devices.Wherein, the algorithm includes: the first pattern data and the second pattern data for obtaining the clock data recovery circuit output of receiver, wherein, first pattern data and the second pattern data are extracted from the first circuit-switched data and the second circuit-switched data respectively by clock data recovery circuit to be obtained, the compensation of linear equalizer and decision feedback equalizer that first circuit-switched data and the second circuit-switched data successively pass through receiver by data to be received obtains, and the bandwidth of linear equalizer is the 1/4 of the rate of data to be received;Compensated information is determined according to the first pattern data and the second pattern data;The decision feedback equalization coefficient of decision feedback equalizer is adjusted according to compensated information.The present invention solve as the Dissipation change of channel it is more complicated caused by the ropy technical problem of receiving end signal.
Description
Technical field
The present invention relates to field of signal transmissions, in particular to the adaptive equilibrium method and device of a kind of receiver.
Background technique
In the application of HSSI High-Speed Serial Interface, due to the dielectric loss and skin effect of channel, so that receiving end signal
Quality is by serious influence.The prior art compensates channel to signal by the equilibrium of the preemphasis of transmitting terminal and receiving end
Low frequency and high frequency attenuation.Wherein, the preemphasis of transmitting terminal is a kind of method of priori, it compensates subsequent letter by predistortion
Road decaying;And the equilibrium of receiving end is a kind of posterior method, is decayed by known signal to be compensated accordingly.
Fig. 1 is according to the block diagram of the HSSI High-Speed Serial Interface receiving terminal circuit of the relevant technologies, as shown in Figure 1, using linear equal
Weighing apparatus and decision feedback equalizer compensate decaying of the channel for high speed signal, high speed differential data by linear equalizer into
Enter decision feedback equalizer, when resetting by clock data recovery circuit, completes data receiver.Linear equalizer is actually one
A high-pass filter, since low-pass characteristic is presented for the decaying of signal in channel, so linear equalizer, which is added, can be good at
Decaying of the channel for high-frequency signal is compensated, to obtain the signal of preferable eye diagram quality after linear equalizer.
When signal rate is higher or the decaying of channel is larger, the compensation of linear equalizer receives a degree of limit
System, because linear equalizer is also exaggerated noise while compensating high frequency attenuation, so if only with linear equal
Weighing apparatus often cannot obtain good signal-to-noise ratio in clock data recovery circuit front end.Based on this reason, in this case
We further carry out equilibrium to signal by insertion decision feedback equalizer, and decision feedback equalizer is carried out to data
Without amplifying the noise of link while compensation, to improve the signal-to-noise ratio in clock data recovery circuit front end.
But when signal rate is higher or channel loss variation is more complicated, the prior art is due to can not dynamically adjust
The coefficient of whole decision feedback equalizer, so that the compensation ability of receiving end can not be dynamically adjusted, before clock data recovery circuit
The noise at end is relatively low, causes clock data recovery circuit can not good retimed data.
For above-mentioned problem, currently no effective solution has been proposed.
Summary of the invention
The embodiment of the invention provides a kind of adaptive equilibrium method of receiver and devices, at least to solve due to channel
Dissipation change it is more complicated caused by the ropy technical problem of receiving end signal.
According to an aspect of an embodiment of the present invention, a kind of adaptive equilibrium method is provided, comprising: obtain the reception
Machine clock data recovery circuit output the first pattern data and the second pattern data, wherein the first pattern data and
The second pattern data are extracted from the first circuit-switched data and the second circuit-switched data respectively by the clock data recovery circuit and are obtained,
First circuit-switched data and second circuit-switched data successively by the linear equalizer of the receiver and are sentenced by data to be received
Certainly the compensation of feedback equalizer obtains, and the bandwidth of the linear equalizer is the 1/4 of the rate of the data to be received;According to institute
It states the first pattern data and the second pattern data determines compensated information;The decision-feedback is adjusted according to the compensated information
The decision feedback equalization coefficient of balanced device.
Further, determine that compensated information includes: to institute according to the first pattern data and the second pattern data
It states the first pattern data and the second pattern data is calculated according to pre-set design conditions, export compensated information.
Further, the first pattern data include at least: pattern 1:0011, pattern 2:1100.
Further, determine that compensated information includes: in institute according to the first pattern data and the second pattern data
Stating the first pattern data is pattern 1, and when the second pattern data are 0011, the compensated information is high level;Described
One pattern data are pattern 1, and when the second pattern data are 0001, the compensated information is low level;At described first yard
Type data are pattern 2, and when the second pattern data are 1100, the compensated information is high level;In the first pattern number
According to for pattern 2, when the second pattern data are 1110, the compensated information is low level.
Further, the decision feedback equalization coefficient packet of the decision feedback equalizer is adjusted according to the compensated information
It includes: Accumulating generation self-adapting signal is carried out to the compensated information;It is equal that the decision-feedback is adjusted by the self-adapting signal
The decision feedback equalization coefficient of weighing apparatus, wherein the feedback reception end of the decision feedback equalizer receives the self-adapting signal.
According to another aspect of an embodiment of the present invention, a kind of adaptive equalization device is additionally provided, comprising: acquiring unit,
The the first pattern data and the second pattern data that clock data recovery circuit for obtaining the receiver exports, wherein institute
The first pattern data and the second pattern data are stated by the clock data recovery circuit respectively from the first circuit-switched data and second
It extracts and obtains in circuit-switched data, first circuit-switched data and second circuit-switched data successively pass through the receiver by data to be received
The compensation of linear equalizer and decision feedback equalizer obtain, the bandwidth of the linear equalizer is the data to be received
The 1/4 of rate;Determination unit, for determining compensated information according to the first pattern data and the second pattern data;It adjusts
Whole unit, for adjusting the decision feedback equalization coefficient of the decision feedback equalizer according to the compensated information, wherein described
The feedback reception end of linear equalizer receives the self-adapting signal.
Further, the determination unit includes: computing module, for the first pattern data and the second code
Type data are calculated according to pre-set design conditions, export compensated information.
Further, the pattern data include at least: pattern 1:0011, pattern 2:1100.
Further, the determination unit includes: the first determining module, for being pattern 1 in the first pattern data,
When the second pattern data are 0011, determine that the compensated information is high level;Second determining module, for described first
Pattern data are pattern 1, when the second pattern data are 0001, determine that the compensated information is low level;Third determines mould
Block, for determining that the compensated information is when the first pattern data are pattern 2, and the second pattern data are 1100
High level;4th determining module is used to be pattern 2 in the first pattern data, when the second pattern data are 1110, really
The fixed compensated information is low level.
Further, the adjustment unit includes: generation module, adaptive for carrying out Accumulating generation to the compensated information
Induction signal;Module is adjusted, for adjusting the decision feedback equalization system of the decision feedback equalizer by the self-adapting signal
Number, wherein the feedback reception end of the decision feedback equalizer receives the self-adapting signal.
To achieve the goals above, according to another aspect of the present invention, a kind of storage medium, the storage medium are provided
Program including storage, wherein equipment where controlling the storage medium in described program operation execute it is described above from
Adaptive equalization method.
To achieve the goals above, according to another aspect of the present invention, a kind of processor is provided, the processor is used for
Run program, wherein described program executes adaptive equilibrium method described above when running.
In embodiments of the present invention, using the first pattern number of the clock data recovery circuit output for obtaining the receiver
According to the second pattern data;Compensated information is determined according to the first pattern data and the second pattern data;According to described
Compensated information adjusts the mode of the decision feedback equalization coefficient of the decision feedback equalizer, by adaptively adjusting decision-feedback
The decision feedback equalization coefficient of balanced device has achieved the purpose that carry out adaptive equalization to data to be received, has increased clock data
The equivalent eye figure noise immunity in restoring circuit front end, so solve as the Dissipation change of channel it is more complicated caused by receiving end
The technical issues of poor signal quality, has reached the technical effect for improving receiving end signal quality.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present invention, constitutes part of this application, this hair
Bright illustrative embodiments and their description are used to explain the present invention, and are not constituted improper limitations of the present invention.In the accompanying drawings:
Fig. 1 is the block diagram according to the HSSI High-Speed Serial Interface receiving terminal circuit of the relevant technologies;
Fig. 2 is a kind of flow chart of adaptive equilibrium method according to an embodiment of the present invention;
Fig. 3 is the functional block diagram according to a kind of adaptive equilibrium method of the present embodiment;
Fig. 4 is the equivalent eye figure of H1- circuit-switched data according to an embodiment of the present invention;
Fig. 5 is the equivalent eye figure of H1+ circuit-switched data according to an embodiment of the present invention;
Fig. 6 is that middle clock data recovery circuit judges code from H1+ circuit-switched data and H1- circuit-switched data according to embodiments of the present invention
The schematic diagram of type 1:0011;
Fig. 7 is that middle clock data recovery circuit judges code from H1+ circuit-switched data and H1- circuit-switched data according to embodiments of the present invention
The schematic diagram of type 2:1100;
Fig. 8 is integrator structure schematic diagram according to an embodiment of the present invention;
Fig. 9 is the schematic diagram of decision feedback equalization coefficient establishment process according to an embodiment of the present invention
Figure 10 is a kind of schematic diagram of the adaptive equalization device of receiver according to an embodiment of the present invention
Figure 11 is the structural schematic diagram according to an embodiment of the present invention using adaptive equilibrium method
Specific embodiment
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work
It encloses.
It should be noted that description and claims of this specification and term " first " in above-mentioned attached drawing, "
Two " etc. be to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should be understood that using in this way
Data be interchangeable under appropriate circumstances, so as to the embodiment of the present invention described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that cover
Cover it is non-exclusive include, for example, the process, method, system, product or equipment for containing a series of steps or units are not necessarily limited to
Step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, product
Or other step or units that equipment is intrinsic.
According to embodiments of the present invention, a kind of embodiment of the method for adaptive equalization is provided, it should be noted that in attached drawing
Process the step of illustrating can execute in a computer system such as a set of computer executable instructions, although also,
Logical order is shown in flow charts, but in some cases, can be executed with the sequence for being different from herein it is shown or
The step of description.
Fig. 2 is a kind of flow chart of adaptive equilibrium method according to an embodiment of the present invention, as shown in Fig. 2, this method packet
Include following steps:
Step S102 obtains the first pattern data and the second pattern number of the clock data recovery circuit output of receiver
According to, wherein the first pattern data and the second pattern data by clock data recovery circuit respectively from the first circuit-switched data and the second tunnel
Extract and obtain in data, the first circuit-switched data and the second circuit-switched data by data to be received successively pass through receiver linear equalizer and
The compensation of decision feedback equalizer obtains, and the bandwidth of linear equalizer is the 1/4 of the rate of data to be received;
Step S104 determines compensated information according to the first pattern data and the second pattern data;
Step S106 adjusts the decision feedback equalization coefficient of decision feedback equalizer according to compensated information.
Fig. 3 is according to a kind of functional block diagram of adaptive equilibrium method of the present embodiment, as shown in figure 3, differential data is logical
It crosses linear equalizer and enters decision feedback equalizer and clock recovery circuitry, the bandwidth that wherein linear equalizer uses is data speed
The 1/4 of rate can carry out effective compensation due to the high pass characteristic of linear equalizer to the decaying of high-frequency signal in the channel, but
In the higher situation of signal rate, linear equalizer is also exaggerated noise while compensating to high-frequency signal, is based on
This reason inserts the decision feedback equalizer based on advanced feedback (Look-Ahead) structure behind linear equalizer,
Further data can be compensated, without amplifying noise, the high speed differential data through overcompensation is extensive by clock data
When compound circuit is reset, parallel data is obtained.In receiving end, the output data to clock recovery circuitry is detected, and is judged current
The compensating coefficient of decision feedback equalizer, and self-adapting signal is accordingly generated, the decision-feedback for adjusting decision feedback equalizer is equal
Weigh coefficient.
In embodiments of the present invention, using obtain receiver clock data recovery circuit output the first pattern data and
Second pattern data;Compensated information is determined according to the first pattern data and the second pattern data;It is adjusted and is adjudicated according to compensated information
The mode of the decision feedback equalization coefficient of feedback equalizer, by the decision feedback equalization for adaptively adjusting decision feedback equalizer
Coefficient has achieved the purpose that carry out adaptive equalization to data to be received, has increased the equivalent eye figure in clock data recovery circuit front end
Noise immunity, and then solve the ropy technology of receiving end signal as caused by the Dissipation change of channel is more complicated and ask
Topic has reached the technical effect for improving receiving end signal quality.
Optionally, the first pattern data include at least: pattern 1:0011, pattern 2:1100.
Fig. 4 is the equivalent eye figure of H1- circuit-switched data according to an embodiment of the present invention, and Fig. 5 is H1+ according to an embodiment of the present invention
The equivalent eye figure of circuit-switched data, for pattern 1:0011, clock data recovery circuit can correctly judge code from H1+ circuit-switched data
Type 1:0011, and what clock data recovery circuit judged from H1- circuit-switched data may be 0011 or 0001, as shown in Figure 6;
For pattern 2:1100, clock data recovery circuit can correctly judge pattern 2:1100 from H1- circuit-switched data, and clock number
What is judged from H1- circuit-switched data according to restoring circuit may be 1100 or 1110, as shown in Figure 7.
Optionally, determine that compensated information includes: to the first pattern data according to the first pattern data and the second pattern data
It is calculated with the second pattern data according to pre-set design conditions, exports compensated information.
It may determine that and work as according to the pattern that clock data recovery circuit is judged from H1+ circuit-switched data and H1- circuit-switched data
The compensating coefficient of leading decision feedback equalizer, and corresponding compensated information is exported, the truth table of compensated information is judged according to pattern
It is as follows:
Optionally, determine that compensated information includes: in the first pattern data according to the first pattern data and the second pattern data
For pattern 1, when the second pattern data are 0011, compensated information is high level;It is pattern 1, the second pattern in the first pattern data
When data are 0001, compensated information is low level;When the first pattern data are pattern 2, and the second pattern data are 1100, compensation
Information is high level;When the first pattern data are pattern 2, and the second pattern data are 1110, compensated information is low level.
When clock data recovery circuit judges pattern data bit pattern 1:0011 from H1+ circuit-switched data, from H1- circuit-switched data
In judge pattern data are as follows: 0011, then increase the decision feedback equalization coefficient of decision feedback equalizer, export high level;When
Clock data recovery circuit judges pattern data bit pattern 1:0011 from H1+ circuit-switched data, judges code from H1- circuit-switched data
Type data are as follows: 0001, then reduce the decision feedback equalization coefficient of decision feedback equalizer, exports low level;When clock data is extensive
Compound circuit judges pattern data bit pattern 2:1100 from H1- circuit-switched data, and pattern data are judged from H1+ circuit-switched data are as follows:
1100, then increase the decision feedback equalization coefficient of decision feedback equalizer, exports high level;When clock data recovery circuit from
Pattern data bit pattern 2:1100 is judged in H1- circuit-switched data, and pattern data are judged from H1+ circuit-switched data are as follows: 1110, then subtract
The decision feedback equalization coefficient of small decision feedback equalizer exports low level.
It optionally, include: to believe compensation according to the decision feedback equalization coefficient that compensated information adjusts decision feedback equalizer
Breath carries out Accumulating generation self-adapting signal;The decision feedback equalization coefficient of decision feedback equalizer is adjusted by self-adapting signal,
Wherein, the feedback reception end of decision feedback equalizer receives the self-adapting signal.
In embodiments of the present invention, the code judged from H1+ circuit-switched data and H1- circuit-switched data according to clock data recovery circuit
After type data determine compensated information, compensated information is subjected to Accumulating generation self-adapting signal, wherein accumulation calculating can pass through
Integrator is completed, and Fig. 8 is integrator structure schematic diagram according to an embodiment of the present invention, as shown in figure 8, compensated information passes through integral
The input terminal of device is input to integrator, and integrator adds up the compensated information of input and previous self-adapting signal, generates
Current self-adapting signal, and self-adapting signal is exported to decision feedback equalizer, decision feedback equalization coefficient is adjusted
It is whole.
Fig. 9 is the schematic diagram of decision feedback equalization coefficient establishment process according to an embodiment of the present invention, as shown in figure 9, logical
Adaptive equilibrium method provided in an embodiment of the present invention is crossed, the decision feedback equalization coefficient of decision feedback equalizer is constantly adjusted,
Finally decision feedback equalization coefficient is made to tend towards stability, and shaken between two values.
To achieve the goals above, according to another aspect of the present invention, the embodiment of the invention also provides a kind of storage Jie
Matter, the storage medium include the program of storage, wherein equipment where controlling the storage medium in described program operation is held
Row adaptive equilibrium method described above.
To achieve the goals above, according to another aspect of the present invention, the embodiment of the invention also provides a kind of processor,
The processor is for running program, wherein described program executes adaptive equilibrium method described above when running.
Other side according to an embodiment of the present invention provides a kind of adaptive equalization device of receiver, Tu10Shi
The schematic diagram of adaptive equalization device according to an embodiment of the present invention, as shown in Figure 10, which includes:
Acquiring unit 10, for obtaining the first pattern data and second code that the clock data recovery circuit of receiver exports
Type data, wherein the first pattern data and the second pattern data are by clock data recovery circuit respectively from the first circuit-switched data and
It extracts and obtains in two circuit-switched datas, the first circuit-switched data and the second circuit-switched data are successively passed through the linear equalization of receiver by data to be received
The compensation of device and decision feedback equalizer obtains, and the bandwidth of linear equalizer is the 1/4 of the rate of data to be received;
Determination unit 20 determines compensated information according to the first pattern data and the second pattern data;
Adjustment unit 30, for adjusting the decision feedback equalization coefficient of decision feedback equalizer according to compensated information.
Fig. 3 is according to a kind of functional block diagram of adaptive equilibrium method of the present embodiment, as shown in figure 3, differential data is logical
It crosses linear equalizer and enters decision feedback equalizer and clock recovery circuitry, the bandwidth that wherein linear equalizer uses is data speed
The 1/4 of rate can carry out effective compensation due to the high pass characteristic of linear equalizer to the decaying of high-frequency signal in the channel, but
In the higher situation of signal rate, linear equalizer is also exaggerated noise while compensating to high-frequency signal, is based on
This reason inserts the decision feedback equalizer based on advanced feedback (Look-Ahead) structure behind linear equalizer,
Further data can be compensated, without amplifying noise, the high speed differential data through overcompensation is extensive by clock data
When compound circuit is reset, parallel data is obtained.In receiving end, the output data to clock recovery circuitry is detected, and is judged current
The compensating coefficient of decision feedback equalizer, and self-adapting signal is accordingly generated, the decision-feedback for adjusting decision feedback equalizer is equal
Weigh coefficient.
In embodiments of the present invention, using obtain receiver clock data recovery circuit output the first pattern data and
Second pattern data;Compensated information is determined according to the first pattern data and the second pattern data;It is adjusted and is adjudicated according to compensated information
The mode of the decision feedback equalization coefficient of feedback equalizer, by the decision feedback equalization for adaptively adjusting decision feedback equalizer
Coefficient has achieved the purpose that carry out adaptive equalization to data to be received, has increased the equivalent eye figure in clock data recovery circuit front end
Noise immunity, and then solve the ropy technology of receiving end signal as caused by the Dissipation change of channel is more complicated and ask
Topic has reached the technical effect for improving receiving end signal quality.
Optionally, the first pattern data include at least: pattern 1:0011, pattern 2:1100.
Fig. 4 is the equivalent eye figure of H1- circuit-switched data according to an embodiment of the present invention, and Fig. 5 is H1+ according to an embodiment of the present invention
The equivalent eye figure of circuit-switched data, for pattern 1:0011, clock data recovery circuit can correctly judge code from H1+ circuit-switched data
Type 1:0011, and what clock data recovery circuit judged from H1- circuit-switched data may be 0011 or 0001, as shown in Figure 6;
For pattern 2:1100, clock data recovery circuit can correctly judge pattern 2:1100 from H1- circuit-switched data, and clock number
What is judged from H1- circuit-switched data according to restoring circuit may be 1100 or 1110, as shown in Figure 7.
Optionally it is determined that unit includes: computing module, it is used for the first pattern data and the second pattern data according to preparatory
The design conditions of setting are calculated, and compensated information is exported.
It may determine that and work as according to the pattern that clock data recovery circuit is judged from H1+ circuit-switched data and H1- circuit-switched data
The compensating coefficient of leading decision feedback equalizer, and corresponding compensated information is exported, the truth table of compensated information is judged according to pattern
It is as follows:
Optionally it is determined that unit includes: the first determining module, for being pattern 1, the second pattern number in the first pattern data
When according to being 0011, determine that compensated information is high level;Second determining module, for being pattern 1, second code in the first pattern data
When type data are 0001, determine that compensated information is low level;Third determining module, for being pattern 2 in the first pattern data, the
When two pattern data are 1100, determine that compensated information is high level;4th determining module, for being pattern in the first pattern data
2, when the second pattern data are 1110, determine that compensated information is low level.
When clock data recovery circuit judges pattern data bit pattern 1:0011 from H1+ circuit-switched data, from H1- circuit-switched data
In judge pattern data are as follows: 0011, then increase the decision feedback equalization coefficient of decision feedback equalizer, export high level;When
Clock data recovery circuit judges pattern data bit pattern 1:0011 from H1+ circuit-switched data, judges code from H1- circuit-switched data
Type data are as follows: 0001, then reduce the decision feedback equalization coefficient of decision feedback equalizer, exports low level;When clock data is extensive
Compound circuit judges pattern data bit pattern 2:1100 from H1- circuit-switched data, and pattern data are judged from H1+ circuit-switched data are as follows:
1100, then increase the decision feedback equalization coefficient of decision feedback equalizer, exports high level;When clock data recovery circuit from
Pattern data bit pattern 2:1100 is judged in H1- circuit-switched data, and pattern data are judged from H1+ circuit-switched data are as follows: 1110, then subtract
The decision feedback equalization coefficient of small decision feedback equalizer exports low level.
Optionally, adjustment unit includes: generation module, for carrying out Accumulating generation self-adapting signal to compensated information;It adjusts
Mould preparation block, for adjusting the decision feedback equalization coefficient of decision feedback equalizer by self-adapting signal, wherein decision-feedback is equal
The feedback reception end of weighing apparatus receives the self-adapting signal.
In embodiments of the present invention, the code judged from H1+ circuit-switched data and H1- circuit-switched data according to clock data recovery circuit
After type data determine compensated information, compensated information is subjected to Accumulating generation self-adapting signal, wherein accumulation calculating can pass through
Integrator is completed, and Fig. 8 is integrator structure schematic diagram according to an embodiment of the present invention, as shown in figure 8, compensated information passes through integral
The input terminal of device is input to integrator, and integrator adds up the compensated information of input and previous self-adapting signal, generates
Current self-adapting signal, and self-adapting signal is exported to decision feedback equalizer, decision feedback equalization coefficient is adjusted
It is whole.
Figure 11 is the structural schematic diagram according to an embodiment of the present invention using adaptive equilibrium method, as shown in figure 11, In
In the embodiment of the present invention, firstly, decision feedback equalizer compensates data to be received under initial compensation coefficient, and export
Two paths of data, into clock data recovery circuit, clock data recovery circuit obtains when two paths of data is judged and reset
Parallel data, pattern interference detector obtain the pattern data of clock recovery circuitry output, and according to clock data recovery circuit
The compensating coefficient of current decision feedback equalizer is determined to the judging result of two paths of data, and exports corresponding compensated information, is mended
Information is repaid after integrator accumulation calculating, inputs to decision feedback equalizer, adjusts the decision-feedback of decision feedback equalizer
Equalizing coefficient changes the compensating coefficient of decision feedback equalizer, and continuous repetition by the above process has reached in data receiver
End carries out the purpose of adaptive equalization, and it is of poor quality to solve the receiving end signal as caused by the Dissipation change of channel is more complicated
The technical issues of.
In the above embodiment of the invention, it all emphasizes particularly on different fields to the description of each embodiment, does not have in some embodiment
The part of detailed description, reference can be made to the related descriptions of other embodiments.
In several embodiments provided herein, it should be understood that disclosed technology contents can pass through others
Mode is realized.Wherein, the apparatus embodiments described above are merely exemplary, such as the division of the unit, Ke Yiwei
A kind of logical function partition, there may be another division manner in actual implementation, for example, multiple units or components can combine or
Person is desirably integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Between coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING or communication link of unit or module
It connects, can be electrical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
On unit.It can some or all of the units may be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can for personal computer, server or network equipment etc.) execute each embodiment the method for the present invention whole or
Part steps.And storage medium above-mentioned includes: that USB flash disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
Reservoir (RAM, Random Access Memory), mobile hard disk, magnetic or disk etc. be various to can store program code
Medium.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (10)
1. a kind of adaptive equilibrium method of receiver characterized by comprising
Obtain the first pattern data and the second pattern data of the clock data recovery circuit output of the receiver, wherein institute
The first pattern data and the second pattern data are stated by the clock data recovery circuit respectively from the first circuit-switched data and second
It extracts and obtains in circuit-switched data, first circuit-switched data and second circuit-switched data successively pass through the receiver by data to be received
The compensation of linear equalizer and decision feedback equalizer obtain, the bandwidth of the linear equalizer is the data to be received
The 1/4 of rate, wherein the data to be received are high speed differential data;
Compensated information is determined according to the first pattern data and the second pattern data;
Accumulating generation self-adapting signal is carried out to the compensated information;
The decision feedback equalization coefficient of the decision feedback equalizer is adjusted by the self-adapting signal, wherein the judgement
The feedback reception end of feedback equalizer receives the self-adapting signal;
Wherein, the first pattern data and the institute of the clock data recovery circuit output are obtained by pattern interference detector
The second pattern data are stated, and first circuit-switched data and second circuit-switched data are sentenced according to the clock data recovery circuit
Disconnected result determines the compensating coefficient of the decision feedback equalizer, exports the compensated information corresponding with the compensating coefficient,
The compensating coefficient is changed by the decision feedback equalization coefficient that the self-adapting signal adjusts the decision feedback equalizer
Become.
2. the method according to claim 1, wherein according to the first pattern data and the second pattern number
Include: according to determining compensated information
The first pattern data and the second pattern data are calculated according to pre-set design conditions, output is mended
Repay information.
3. method according to claim 1 or 2, which is characterized in that the first pattern data include at least: pattern 1:
0011, pattern 2:1100.
4. according to the method described in claim 3, it is characterized in that, according to the first pattern data and the second pattern number
Include: according to determining compensated information
When the first pattern data are pattern 1, and the second pattern data are 0011, the compensated information is high level;
When the first pattern data are pattern 1, and the second pattern data are 0001, the compensated information is low level;
When the first pattern data are pattern 2, and the second pattern data are 1100, the compensated information is high level;
When the first pattern data are pattern 2, and the second pattern data are 1110, the compensated information is low level.
5. a kind of adaptive equalization device of receiver, which is characterized in that the device includes:
Acquiring unit, the first pattern data and the second pattern that the clock data recovery circuit for obtaining the receiver exports
Data, wherein the first pattern data and the second pattern data are by the clock data recovery circuit respectively from first
It extracts and obtains in circuit-switched data and the second circuit-switched data, first circuit-switched data and second circuit-switched data are successively passed through by data to be received
The compensation of the linear equalizer and decision feedback equalizer of crossing the receiver obtains, and the bandwidth of the linear equalizer is described
The 1/4 of the rate of data to be received, wherein the data to be received are high speed differential data;
Determination unit, for determining compensated information according to the first pattern data and the second pattern data;
Adjustment unit, for carrying out Accumulating generation self-adapting signal to the compensated information;It is adjusted by the self-adapting signal
The decision feedback equalization coefficient of the decision feedback equalizer, wherein the feedback reception end of the decision feedback equalizer receives
The self-adapting signal;
Wherein, described device is also used to obtain described the of clock data recovery circuit output by pattern interference detector
One pattern data and the second pattern data, and according to the clock data recovery circuit to first circuit-switched data and described
The judging result of second circuit-switched data determines the compensating coefficient of the decision feedback equalizer, exports corresponding with the compensating coefficient
The compensated information, the compensating coefficient are equal by the decision-feedback that the self-adapting signal adjusts the decision feedback equalizer
Weighing apparatus coefficient is changed.
6. device according to claim 5, which is characterized in that the determination unit includes:
Computing module, for the first pattern data and the second pattern data according to pre-set design conditions into
Row calculates, and exports compensated information.
7. device according to claim 5 or 6, which is characterized in that the pattern data include at least: pattern 1:0011,
Pattern 2:1100.
8. device according to claim 7, which is characterized in that the determination unit includes:
First determining module, for determining when the first pattern data are pattern 1, and the second pattern data are 0011
The compensated information is high level;
Second determining module, for determining when the first pattern data are pattern 1, and the second pattern data are 0001
The compensated information is low level;
Third determining module, for determining when the first pattern data are pattern 2, and the second pattern data are 1100
The compensated information is high level;
4th determining module, for determining when the first pattern data are pattern 2, and the second pattern data are 1110
The compensated information is low level.
9. a kind of storage medium, which is characterized in that the storage medium includes the program of storage, wherein is located in described program
Equipment perform claim where controlling the storage medium when reason device operation requires 1 to connecing described in any one of claim 4
The adaptive equilibrium method of receipts machine.
10. a kind of processor, which is characterized in that the processor is for running program, wherein right of execution when described program is run
Benefit require 1 to the receiver described in any one of claim 4 adaptive equilibrium method.
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