CN112272009B

CN112272009B - Equalizer circuit

Info

Publication number: CN112272009B
Application number: CN202011222942.6A
Authority: CN
Inventors: 臧剑栋; 罗璞; 刘军; 付东兵; 王健安; 陈光炳; 唐枋; 殷鹏
Original assignee: Chongqing Jixin Technology Co ltd; CETC 24 Research Institute
Current assignee: Chongqing Jixin Technology Co ltd; CETC 24 Research Institute
Priority date: 2020-11-05
Filing date: 2020-11-05
Publication date: 2023-09-05
Anticipated expiration: 2040-11-05
Also published as: CN112272009A

Abstract

The invention proposes an equalizer circuit comprising: an equalizer; the sampler is used for sampling the output signal of the equalizer to obtain a four-phase clock sampling signal; the clock recovery circuit is used for acquiring an adaptive phase control signal according to the four-phase clock sampling signal, recovering a four-phase clock according to the adaptive phase control signal, outputting the four-phase clock to the sampler and controlling the sampling of the sampler; the equalizer self-adaptive circuit is used for generating a gain control signal according to the self-adaptive phase control signal and outputting the gain control signal to the equalizer to adjust the gain of the equalizer.

Description

Equalizer circuit

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to an equalizer circuit.

Background

In the spectrum balancing method, adaptive equalization is achieved by comparing the high frequency and low frequency components of the data power and generating a feedback signal until the power spectrum is balanced. While equalizer adaptation in this approach can be implemented independent of timing recovery, implementation requires complex analog circuitry whose performance can be affected by process variations. In the spectrum equalization method, the spectrum of the compensation data is decomposed into PH and PL regions based on fm (fm≡0.28/Tb where Tb is the bit period of the data). For a well-compensated signal, PL and PH have the same amount. The value of fm is determined from the pseudo-random binary data. Fig. 6 schematically shows an optimized spectrum balancing method. When fm' is lower than fm, this means that the current PL fraction is smaller than the actual case. The converter should therefore improve the ratio of PL to PH to cover the gap between the current spectrum and the actual spectrum. When fm' is greater than fm, the converter bias current trend is opposite. By using the mechanism, the equalization system can realize true self-adaption and compensate large-range transmission data.

Digital signal processing using a least mean square or zero-breaking algorithm may also be used for adaptive equalization. This provides flexibility and ease of programming, but the speed limitations and complexity of the required analog-to-digital converter limit the applicability of this scheme to high speed applications. The sign LMS algorithm is widely used for coefficient adaptation due to its simplicity of implementation. However, instability and the possibility of convergence to secondary advantages caused by implementation and modeling imperfections are two of its major drawbacks. The modified sign LMS algorithm achieves BER-based coefficient adaptation by maximizing the voltage margin.

Adaptive equalization may also be implemented using an Eye Opening Monitor (EOM). The EOM evaluates the data quality by periodically observing the filter output and provides information about the equalization filter performance. Using this information, the equalizer can determine the optimal filter conditions. For these methods, a synchronous sampling clock circuit and a high-speed comparator are indispensable. Furthermore, it may be difficult to recover the clock signal from the initially closed eye diagram, thereby limiting its applicability.

The histogram method is an EOM-based adaptation method, based on a simple observation that the sharpest eye pattern produces the largest peak in the histogram obtained by asynchronous undersampling. For the case of over-equalization, the equalizer output has an enhanced high frequency component, which tends to expand the data amplitude distribution around the peak, as shown in fig. 7 (a). For the case of inequality, the distribution in the histogram is spread out as shown in fig. 7 (c). With optimal equalization, the distribution is concentrated at the peak as shown in fig. 7 (b). Based on these observations, we can easily determine the equalizer condition that results in the best eye quality by simply searching the histogram with the largest peak. Asynchronous undersampling allows reliable data acquisition as long as a sufficient number of samples are acquired and the sampling clock is not a subharmonic of the data clock. Such asynchronous undersampling techniques have been used for performance monitoring in optical communications. However, they cannot determine the optimal sampling time for the minimum BER. Tracking the maximum marginal point may minimize BER performance, but on-chip implementation requires significant memory.

The basic principle of the zero forcing (Zero Forcing Solution, ZFS) algorithm is to find a suitable set of equalizer coefficients such that the unit impulse response of the transmission line and equalizer cascade is only non-0 at the sampling instants and 0 at the other instants. Symbol-based zero-forcing (S-ZF) algorithms, which are improved on zero-forcing algorithms, are commonly used in adaptive equalizers, and the S-ZF algorithm finds sequences that are representative of ISI, taking into account that ISI is mainly related to the manner in which different symbol sequences are combined, and detecting such sequences can yield the cancellation of ISI.

Disclosure of Invention

In view of the above problems in the prior art, the present invention provides an equalizer circuit, which mainly solves the problems of high complexity and limited speed of adaptive control of an equalizer.

In order to achieve the above and other objects, the present invention adopts the following technical scheme.

An equalizer circuit, comprising:

an equalizer;

the sampler is used for sampling the output signal of the equalizer to obtain a four-phase clock sampling signal;

the clock recovery circuit is used for acquiring an adaptive phase control signal according to the four-phase clock sampling signal, recovering a four-phase clock according to the adaptive phase control signal, outputting the four-phase clock to the sampler and controlling the sampling of the sampler;

and the equalizer self-adaptive circuit is used for generating a gain control signal according to the self-adaptive phase control signal, outputting the gain control signal to the equalizer and adjusting the gain of the equalizer.

Optionally, the equalizer comprises a resistor sequence, one or more resistors in the resistor sequence are selectively connected through the gain control signal, and an access resistor value of the equalizer is controlled to adjust the gain of the equalizer.

Optionally, the clock recovery circuit includes:

the phase detection unit is used for receiving the input four-phase clock sampling signals, performing exclusive-or processing on the four-phase clock sampling signals and generating the adaptive phase control signals;

and the clock recovery unit is used for obtaining a four-phase clock according to the adaptive phase control signal.

Optionally, the clock recovery unit includes:

the clock recovery controller is used for acquiring a recovery control signal according to the self-adaptive phase control signal;

and the phase selection phase interpolator is used for carrying out phase selection and interpolation according to the recovery control signal to acquire the four-phase clock.

Optionally, the equalizer adaptation circuit comprises:

the intersymbol interference detection module is used for detecting the deviation value of the adaptive phase control signal;

the voter module is used for acquiring deviation change information in a plurality of periods according to the deviation value output by the intersymbol interference detection module;

the filtering module is used for filtering the output of the voter module to obtain a binary representation of deviation change;

the counting module is used for recording the number of addition and subtraction operations to be executed according to the binary representation;

the bandwidth and gain control module is used for selecting a preset input value according to the number of the addition and subtraction operations to be executed, and executing the corresponding addition and subtraction operations to generate a specified output signal;

and the decoding module is used for converting the appointed output signal into the gain control signal.

Optionally, the generating manner of the adaptive phase control signal is as follows:

where d90_3, d180, d270, d0 represent phase clock sampling signals with phases 90, 180, 270,0, respectively, and d90_2 and d90_3 differ by one clock.

Optionally, the calculation mode of the intersymbol interference detection module is as follows:

where hi denotes that the equalizer output signal is greater than the reference frequency spectrum and low denotes that the equalizer output signal is less than the reference frequency spectrum; e2 (n-1) represents an adaptive phase control signal obtained in a previous clock cycle.

Optionally, the voter module includes a first decision maker, a second decision maker, a third decision maker, a first trigger, a second trigger, and a third trigger;

the first decision device receives the output of the intersymbol interference detection module, and the output end is respectively connected with the input end of the second decision device and the input end of the first trigger; the output end of the first trigger is connected with the input end of the second decision device; the output end of the second decision device is connected with the input end of the second trigger; the output end of the second trigger is respectively connected with the input end of the third trigger and the input end of the third decision device; the output end of the third trigger is connected with the input end of the third decision device; the output end of the third decision device is connected with the input end of the filtering module.

Optionally, the filtering module includes a clock generator, an analog-to-digital converter, and a fourth determiner; the clock generator is respectively connected with the analog-to-digital converter and the fourth decision device; the input end of the analog-to-digital converter is connected with the output end of the voter module; the output end of the analog-to-digital converter is connected with the input end of the fourth decision device; and the output end of the fourth decision device is connected with the counting module.

Optionally, the output end of the decision device comprises two output pins, and when the two output pins are at a high level, the subsequent one-subtracting operation is required to be executed; when the values are 0, the subsequent operation does not need to be executed; when the two output pins are high and low, the operation of adding one is needed to be executed subsequently.

As described above, the equalizer circuit of the present invention has the following advantageous effects.

The bandwidth can be adjusted in a self-adaptive mode, unnecessary calculation amount is reduced, and the efficiency and accuracy of equalizer adjustment are improved.

Drawings

Fig. 1 is a schematic circuit diagram of an equalizer circuit according to an embodiment of the present invention.

FIG. 2 is a diagram of a four-phase clock sampling signal according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a connection structure of an equalizer adaptation circuit according to an embodiment of the invention.

Fig. 4 is a schematic diagram of a connection structure of a voter module according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a filter module according to an embodiment of the invention.

Fig. 6 is a spectrum diagram of an optimized spectral equalization method.

Fig. 7 is a schematic diagram of an equalization scenario.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

Referring to fig. 1, the present invention provides an equalizer circuit, which includes an equalizer 01, a sampler 02, a clock recovery circuit, and an equalizer adaptive circuit 06.

In one embodiment, equalizer 01 may be an existing equalizer, without limitation. The sampler 02 samples the output signal of the equalizer 01. The equalizer 01 outputs differential signals, and four-phase clock sampling signals DS0, DS90, DS180 and DS270 are obtained by sampling through the sampler 02. Wherein DS0 corresponds to a value obtained by sampling a 0-phase clock, DS90 corresponds to a value obtained by sampling a 90-degree phase clock, and the like, to obtain a four-phase clock sampling signal.

In an embodiment, the input of the clock recovery circuit is connected to the output of the sampler 02 and provides a four-phase clock to the sampler 02 for controlling the sampling process. Specifically, the clock recovery circuit comprises a phase detection unit 03 and a clock recovery unit, wherein the input end of the phase detection unit 03 is connected with the output end of the sampler 02; the output of the phase detection unit 03 is connected to the input of the clock recovery unit and the input of the equalizer adaptation circuit 06, respectively.

In an embodiment, the clock recovery unit comprises a clock recovery controller 04 and a phase selective phase interpolator 05. The input end of the clock recovery controller 04 is connected with the output end of the phase detection unit 03; the output end of the clock recovery controller 04 is connected with the input end of the phase selection phase interpolator 05; the output of the phase selective phase interpolator 05 is connected to the clock input of the sampler 02.

Referring to fig. 3, in one embodiment, the equalizer adaptation circuit 06 includes an intersymbol interference detection module 061, a voter module 062, a filter module 063, a counter module 064, a bandwidth and gain control module, and a decoding module 067. The input end of the intersymbol interference detection module 061 is connected with the output end of the phase detection unit 03; the output end of the intersymbol interference detection module 061 is connected with the input end of the voter module 062; the output end of the voter module 062 is connected with the input end of the filter module 063; the output end of the filter module 063 is connected with the input end connected with the counter module 064; the output end of the counter module 064 is connected with the input end of the bandwidth and gain control module; the output end of the bandwidth and gain control module is connected with the decoder 067; the output of decoder 067 is connected to equalizer 01.

In one embodiment, the bandwidth and gain control module includes a bandwidth and gain controller 065 and a counter 066, an input end of the bandwidth and gain controller 065 is connected to an output end of the counter module 064, an output end of the bandwidth and gain controller 065 is connected to an input end of the counter 066, and an output end of the counter 066 is connected to an input end of the decoder 067.

Referring to fig. 4, in an embodiment, the voter module 062 includes a first decision maker 0621, a second decision maker 0623, a third decision maker 0625, a first trigger 0622, a second trigger 0624, and a third trigger 0626; the input end of the first decision device 0621 is connected with the output end of the intersymbol interference detection module 061; the output end of the first decision device 0621 is connected with the input end of the first trigger 0622 and the input end of the second decision device 0623 respectively; the output end of the first trigger 0622 is connected with the input end of the second decision device 0623; the output end of the second decision device 0623 is connected with the input end of the second trigger 0624; the output end of the second trigger 0624 is connected with the input end of the third trigger 0626 and the input end of the third decision device 0625 respectively; the output end of the third trigger 0626 is connected with the input end of the third decision device 0625; the output of the third decision device 0625 is connected to the input of the filter module 063.

Referring to fig. 5, in one embodiment, the filter module 063 includes a clock generator 0631, an analog-to-digital converter 0632, and a fourth decision device 0633; the clock generator 0631 is respectively connected with the analog-digital converter 0632 and the fourth decision device 0633; the input end of the analog-to-digital converter 0632 is connected with the output end of the voter module 062; the output end of the analog-to-digital converter 0632 is connected with the input end of the fourth decision device 0633; the output of the fourth decision device 0633 is connected to the counting module 064.

According to the structural design of the equalizer circuit, the control process is as follows:

the sampler 02 inputs the sampled DS0, DS90, DS180, and DS270 to a phase detection unit, and the phase detection unit performs exclusive or on the four-phase clock sampling signals to obtain an adaptive phase control signal, and inputs the adaptive phase control signal to a clock recovery unit and an equalizer adaptive circuit 06, respectively.

Specifically, referring to fig. 2, the manner in which the phase detection unit generates the adaptive phase control signal can be expressed as:

The specific exclusive or calculation mode can be adjusted according to the actual application requirements, and only one calculation mode is illustrated here by way of example.

The clock recovery controller 04 (CDR) derives a recovery control signal PSPI [5 ] from d2, d1, e2, e 1:0] for controlling the phase selection phase interpolator 05 to select and interpolate according to the bits, recovering the four-phase clock, and feeding back to the sampler 02 to control the sampling process. The clock recovery controller 04 and the phase selective phase interpolator 05 may be of conventional design.

After the intersymbol interference detection module 061 (ISI detection) receives the adaptive phase control signals d2, d1, e2, e1, it determines whether the output of the equalizer 01 is larger or smaller, and the specific determination process is as follows:

where hi denotes that the equalizer 01 output signal is greater than the reference spectrum, low denotes that the equalizer 01 output signal is less than the reference spectrum; e2 (n-1) represents an adaptive phase control signal obtained in a previous clock cycle.

Through e2, e1 and operation, the method is equivalent to judging whether the front bit and the rear bit are overturned or not, and edge information is obtained; the data information is obtained by d2, d 1.

After the big and small information is obtained, the big and small data are formed into data pairs [ hi1, low1], [ hi2, low2], and the data pairs are input into a voter module 062, so that the big and small information in a plurality of periods is obtained. The voter module 062 can effectively avoid frequent flipping, and reduce power consumption.

Further, the filter module 063 generates a set of signals B [1] based on the large and small information over several periods: 0, the decision device comprises two output pins, B1 and B0 are respectively output, when the two output pins are at high level, the subsequent operation of subtracting one is needed to be executed; when the values are 0, the subsequent operation does not need to be executed; when the two output pins are high and low, the operation of adding one is needed to be executed subsequently.

The output of the filter module 063 is provided to a counter module 064, which may employ an 18-bit counter, resulting in a sequence q <17 that is required to perform an add-subtract operation: 0> representing the number of one-plus-one-minus-one over a period of time, wherein the one-minus-one can be represented in the form of a complement. The sequence input bandwidth and gain controller 065 triggers the corresponding bandwidth control signal rx_ afe _adpt_bw and bit selection control signal rx_ afe _adpt_th to select several bits of data from the preset multi-bit input information to be added. For example, 9 bits of the preset 18-bit input are selected by the value of rx_ afe _adpt_bw, the smaller the value of rx_ afe _adpt_bw, the lower the number of bits selected, the faster the rate and the greater the bandwidth. rx_ afe _adpt_th represents selecting several bits of data from the selected 9 bits of data to be added. Referring to fig. 5 specifically, a correspondence between the bandwidth control signal rx_ afe _adpt_bw and corresponding preset input data is shown, where N66, N65, N68, N64, N308, N311, N468, N469, N259 represents the selected 9-bit input data; n638 and N637 denote outputs obtained by adding data. See, for example, tables 1 and 2.

TABLE 1

rx_afe_adpt_bw

N66

N65

N68

N64

N308

N311

N468

N469

N259

000

q9

q8

q7

q6

q5

q4

q3

q2

q1

001

q10

q9

q8

q7

q6

q5

q4

q3

q2

010

q11

10

q9

q8

q7

q6

q5

q4

q3

011

q12

q11

q10

q9

q8

q7

q6

q5

q4

100

q13

q12

q11

q10

q9

q8

q7

q6

q5

101

q14

q13

q12

q11

q10

q9

q8

q7

q6

110

q15

q14

q13

q12

q11

q10

q9

q8

q7

111

q16

q15

q14

q13

q12

q11

q10

q9

q8

TABLE 2

The bandwidth and gain controller 065 inputs N638, N637 into a 4bit counter, further filters out the excess, and reduces the computation. The gain control signal Rx_rjlx_o [14 ] can be obtained by the decoder having the output of the 4-bit counter in one-to-one correspondence with the gain control signal: 0]. Equalizer 01 comprises a set of parallel set resistor sequences, which when rx_rjlx_o [14:0], selecting one or more corresponding resistors in the connected resistor sequence according to the signal, and further adjusting the resistance value of the access equalizer 01 to realize the self-adaptive adjustment of bandwidth and gain.

Compared with the prior art, the equalizer circuit does not need to find a representative sequence to detect and adjust, reduces the calculated amount, can be used for high-frequency bands such as 5GHz, 2.5GHz and 1.25GHz, and improves the applicability of the circuit; the adjustable bandwidth can be used for the adaptive process of the continuous time linear equalizer. The product has high industrial value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. An equalizer circuit, comprising:

an equalizer;

the clock recovery circuit is used for acquiring an adaptive phase control signal according to the four-phase clock sampling signal, recovering a four-phase clock according to the adaptive phase control signal, outputting the four-phase clock to the sampler, and controlling the sampling of the sampler, and the clock recovery circuit comprises: the phase detection unit is used for receiving the input four-phase clock sampling signals, performing exclusive-or processing on the four-phase clock sampling signals and generating the adaptive phase control signals; the clock recovery unit is used for obtaining a four-phase clock according to the self-adaptive phase control signal;

an equalizer adaptive circuit for generating a gain control signal from the adaptive phase control signal and outputting the gain control signal to the equalizer to adjust the gain of the equalizer, the equalizer adaptive circuit comprising: the intersymbol interference detection module is used for detecting the deviation value of the adaptive phase control signal; the voter module is used for acquiring deviation change information in a plurality of periods according to the deviation value output by the intersymbol interference detection module; the filtering module is used for filtering the output of the voter module to obtain a binary representation of deviation change; the counting module is used for recording the number of addition and subtraction operations to be executed according to the binary representation; the bandwidth and gain control module is used for selecting a preset input value according to the number of the addition and subtraction operations to be executed, and executing the corresponding addition and subtraction operations to generate a specified output signal; and the decoding module is used for converting the appointed output signal into the gain control signal.

2. The equalizer circuit of claim 1, wherein the equalizer comprises a resistor sequence, wherein one or more resistors in the resistor sequence are selectively connected by the gain control signal, and wherein an access resistance value of the equalizer is controlled to adjust a gain of the equalizer.

3. The equalizer circuit of claim 1, wherein the clock recovery unit comprises:

4. The equalizer circuit of claim 1, wherein the adaptive phase control signal is generated by:

where d90_3, d180, d270, d0 represent phase clock sampling signals with phases 90, 180, 270,0, respectively, and d90_2 differs from d90_3 by one clock, and d1, d2, e1, and e2 represent adaptive phase control signals, respectively.

5. The equalizer circuit of claim 4, wherein the intersymbol interference detection module is configured to:

6. The equalizer circuit of claim 1, wherein the voter module comprises a first decision device, a second decision device, a third decision device, a first flip-flop, a second flip-flop, a third flip-flop;

7. The equalizer circuit of claim 1, wherein the filtering module comprises a clock generator, an analog-to-digital converter, and a fourth determiner; the clock generator is respectively connected with the analog-to-digital converter and the fourth decision device; the input end of the analog-to-digital converter is connected with the output end of the voter module; the output end of the analog-to-digital converter is connected with the input end of the fourth decision device; and the output end of the fourth decision device is connected with the counting module.

8. The equalizer circuit of claim 6 or 7, wherein the output of the decision device comprises two output pins, wherein when both of the output pins are at a high level, the output pins indicate that a subtracting operation is required to be performed subsequently; when the values are 0, the subsequent operation does not need to be executed; when the two output pins are high and low, the operation of adding one is needed to be executed subsequently.