CN112532550B

CN112532550B - Automatic tuning system for Ethernet receiving end equalizer

Info

Publication number: CN112532550B
Application number: CN202011384156.6A
Authority: CN
Inventors: 段有楠; 邱建峰; 戚晨希
Original assignee: Suzhou Centec Communications Co Ltd
Current assignee: Suzhou Centec Communications Co Ltd
Priority date: 2020-12-01
Filing date: 2020-12-01
Publication date: 2022-08-26
Anticipated expiration: 2040-12-01
Also published as: CN112532550A

Abstract

The invention provides an automatic tuning system for an Ethernet receiving end equalizer, which comprises: the receiving end equalizer is used for receiving the original signal and performing signal compensation; the clock data recovery module is used for receiving the original signal compensated by the receiving end equalizer and recovering clock data; an eye scan module for sampling the clock data to obtain eye data; and the equalization adjusting module is used for obtaining a parameter adjusting result based on the eye diagram data and configuring the receiving end equalizer by using the parameter adjusting result. The invention determines the parameter adjusting result of the receiving end equalizer through the eye pattern data and carries out automatic adjustment and optimization, so that the signal transmission loss is properly compensated and the receiving end data is correctly recovered under the condition that the current link condition is uncertain, thereby reducing the error rate of the ten-gigabit Ethernet communication and improving the system reliability.

Description

Automatic tuning system for Ethernet receiving end equalizer

Technical Field

The invention relates to the technical field of network equipment, in particular to an automatic tuning system for an equalizer at an Ethernet receiving end.

Background

In an ethernet communication system, due to different capabilities of transmitting ends of devices or different conditions of media connected between ports, various losses or distortions may exist in signals acquired by a receiving end SerDes compared with original signals, and if the loss is large to a certain extent, the receiving end cannot recover data signals, which may cause error codes or loss of data. Therefore, the receiving-side SerDes is required to have the capability of compensating for signal loss. This is the task that the equalizer at the receiving end performs. Common equalizers include VGA/CTLE/DFE, etc.

In an Ethernet link with a lower speed (lower than 10.3125G), requirements on a transmitting end, a channel and the like are not high, and correct clock data can be recovered in Serdes only by roughly adjusting a corresponding receiving end equalizer or even without equalizing. However, in an ethernet link of ten-thousand megabits or more, a receiving end is very dependent on an equalizer, and whether the equalizer can reasonably compensate loss directly affects the error rate of the system. Especially, in some connecting lines of non-optical media, such as DAC or PCB backplane wiring, even some ethernet devices that need to adapt to temperature-varying environment, since the characteristics of the media may have great difference at high temperature and low temperature, the equalizer is required to adapt to the change of the channel and perform automatic tuning, thereby reducing the error rate of the system and improving the reliability of the device.

FIG. 1 is a prior art system diagram. Firstly, requiring the opposite terminal device to continuously send PRBS code type data, after the signal enters the receiving terminal, the signal is sequentially processed by two equalizers of CTLE/DFE to recover the PRBS code, and the error code statistics is carried out. And respectively controlling the CTLE/DFE according to the current error code condition, increasing the compensation force until a group of configurations meeting the PRBS error code rate requirement are found, and finishing the adjustment. This approach has the disadvantages of:

1) the system has strict requirements on the data format of the transmitting end. The PRBS is a pseudo-random sequence and is generated by an algorithm, and a receiving end can work out a modular sequence through the algorithm as long as the receiving end uses the same pattern as the sending end, so that wrong code words can be compared. In practice, however, not all devices are able to transmit the PRBS code.

2) And the PRBS is sent to mean that the user data cannot be transmitted, which shows that the system cannot be re-optimized in the process that the link is established and the user data starts to be transmitted, and only can satisfy the connection with quite stable link characteristics and is once optimized when the establishment is started. This risks scene adaptation to temperature variations.

3) The PRBS statistics of error conditions need to be accumulated for a certain time. Too short a PRBS detection does not accurately reflect the system error rate. The system does not indicate how long a process takes. However, from practical experience, it is common that only 1 false statistic occurs within a few seconds. If the detection is in milliseconds, this error is probably missed, and the current equalization is deemed ok, but the actual effect is poor. If the detection requires seconds, the error can be detected, but the time is too long.

In other prior art techniques, a way to adjust the CTLE based on eye height openness is provided. Firstly, a lookup table of the CTLE is correspondingly found based on an estimated signal intensity, then, configurations which can enable the CDR to be locked are searched in a traversing mode in the table, and then, the CTLE value is sequentially traversed to find the optimal configuration. This approach has the disadvantages of:

1) only aiming at the adjustment mode of the CTLE equalizer, and not adjusting the VGA;

2) if abnormal processing is lacked, for example, a transmission code pattern mutation occurs in the adjustment process, and a large number of signals are connected with 0 to 1, the CDR may not be locked normally, and thus the optimal configuration of the CTLE cannot be found.

Disclosure of Invention

First, terms appearing in the present invention are explained:

1. eye pattern: the receiving end signal is superposed with a displayed graph on the oscilloscope, so that the overall characteristic of the signal is reflected, the quality degree of the system signal can be estimated, the horizontal axis represents the period/time, and the vertical axis represents the amplitude

2. CTLE: Continuous-Time Linear Equalizer, a high pass filter that compensates for high frequency loss in a channel by suppressing low frequencies and amplifying high frequencies

3. VGA: voltage Gain Amplifier, an equalizer that linearly amplifies the amplitude of an input signal

4. DFE: Decision-Feedback Equalizer, an Equalizer, automatically adjusting signal compensation based on Feedback circuit

5. Inserting loss: insertion loss. Refers to the signal loss, usually referred to as attenuation, caused by the insertion of cables or components between the transmitter and receiver. The insertion loss is expressed in corresponding decibels (dB) of the received signal level.

6. A SerDes: the SERDES is a short for an english SERializer/DESerializer, and it converts a plurality of low-speed parallel signals into high-speed serial signals at a transmitting end, passes through a transmission medium, and finally restores the high-speed serial signals to the low-speed parallel signals at a receiving end again. The gigabit ethernet commonly uses SerDes technology to complete the transmission of signals.

7. DAC: direct Attach Cable, generally translated as Direct-connected copper Cable, has copper core as internal material and much lower price than optical fiber

8. PRBS: Pseudo-Random Binary Sequence, which is generally used to test high-speed serial channels, mainly to test bit error rate

9. CDR: clock Data Recovery is the core module of the SerDes to correctly recover the Clock and Data from the Data that has undergone channel distortion.

In an ethernet link of ten-gigabit or more, due to different characteristics of a sending end and a connecting medium of equipment, an equalizer at a receiving end needs to reasonably compensate signals so as to reduce the error rate of a system. In view of the above, to solve or partially solve the above problems, the present invention provides an automatic equalizer tuning system for ethernet receiving end, which automatically tunes an equalizer, and dynamically adjusts parameters of the local equalizer based on comprehensive judgment of eye diagram level of the receiving end under the condition that the current link status is uncertain, so as to properly compensate signal transmission loss and correctly recover data of the receiving end.

According to an aspect of the present invention, there is provided an ethernet receiving end equalizer automatic tuning system, the system comprising:

the receiving end equalizer is used for receiving the original signal and performing signal compensation;

the clock data recovery module is used for receiving the original signal compensated by the receiving end equalizer and recovering clock data;

an eye scan module to sample the clock data to obtain eye data;

and the equalization adjusting module is used for obtaining a parameter adjusting result based on the eye diagram data and configuring the receiving end equalizer by using the parameter adjusting result.

In one embodiment, the receiving end equalizer includes a continuous time linear equalizer CTLE, a voltage gain amplifier VGA, and a decision feedback equalizer DFE, and the original signal is subjected to the CTLE, VGA, and DFE in sequence to complete signal compensation.

In an embodiment, the equalization adjustment module is specifically configured to:

presetting initial conditions of the receiving end equalizer;

carrying out rough blending and insertion loss estimation on the initial conditions;

determining a state of the DFE;

and performing fine adjustment on the CTLE.

In an embodiment, the presetting of the initial condition of the receiving end equalizer specifically includes:

configuring a universal initial value for the equalizer at the receiving end, and judging whether the eye pattern is opened at the moment; if so,

then the step of coarse adjustment and insertion loss estimation to the initial condition is operated; if not, the user can not select the specific application,

the initial value is modified and then the verification is continued as to whether the eye diagram is open.

In one embodiment, the values configured for the receiving-end equalizer include CTLE high frequency compensation values, CTLE low frequency compensation values, VGA values, DFE values.

In an embodiment, the rough adjustment and insertion loss estimation on the initial condition specifically includes:

configuring a plurality of groups of balance compensation preset values according to the size of the insertion loss;

initializing eye pattern data;

configuring the receiving end equalizer according to the preset equalization compensation value;

calling the eye pattern scanning module to obtain current eye pattern data;

traversing the multiple groups of preset equalization compensation values to configure the eye diagram data after the eye diagram data takes effect, and determining a group of preset equalization compensation values corresponding to the maximum eye diagram data;

and configuring the equalizer at the receiving end by using a group of preset equalization compensation values when the eye pattern data is maximum.

In one embodiment, the DFE values in the plurality of sets of equalization compensation default values are configured as fixed values during coarse and insertion loss estimation of the initial conditions.

In one embodiment, determining the state of the DFE specifically includes:

turning off the DFE and obtaining eye pattern data;

judging whether the eye pattern data are larger than an eye pattern preset value or not; if not, the user can not select the specific application,

turning on the DFE and setting the DFE to an adaptive state; if so,

the step of fine tuning the CTLE is run.

In an embodiment, the fine adjustment of the CTLE specifically includes:

after the VGA value and the CTLE high-frequency compensation value are fixed, traversing eye pattern data when the CTLE low-frequency compensation value fluctuates in a preset range near the current value;

and configuring the CTLE with the CTLE low-frequency compensation value corresponding to the obtained maximum eye diagram data.

In an embodiment, the clock data recovery module is further configured to send the recovered clock data to the user side while sending the recovered clock data to the eye pattern scanning module.

The automatic tuning system of the Ethernet receiving end equalizer provided by the invention determines the tuning result of the receiving end equalizer by using the eye diagram data, and automatically tunes the serdes receiving end equalizer by combining the modes of coarse tuning and fine tuning, so that the signal transmission loss is properly compensated and the receiving end data is correctly recovered under the condition that the current link condition is uncertain, thereby reducing the error rate of the gigabit Ethernet communication and improving the reliability of the system.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is also possible for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a diagram of a system provided by prior art 1;

fig. 2 is a block diagram of an automatic tuning system of an equalizer at an ethernet receiving end according to an embodiment of the present invention;

fig. 3 is a logic diagram of an automatic tuning system for an equalizer at an ethernet receiving end according to an embodiment of the present invention;

fig. 4 is a flowchart of an adjustment algorithm of an equalization adjustment module in an automatic tuning system of an equalizer at an ethernet receiving end according to an embodiment of the present invention;

fig. 5 is a flowchart of a method for automatically adjusting preset conditions of a system by an equalizer at an ethernet receiving end according to an embodiment of the present invention;

fig. 6 is a flowchart of a coarse adjustment and insertion loss estimation method for an automatic tuning system of an equalizer at an ethernet receiving end according to an embodiment of the present invention;

fig. 7 is a flowchart of a method for determining a DFE state by an automatic tuning system of an equalizer at an ethernet receiving end according to an embodiment of the present invention;

fig. 8 is a flowchart of a fine adjustment method of an automatic tuning system for an equalizer at an ethernet receiving end according to an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2 and fig. 3, a specific embodiment of the system for automatically tuning an equalizer at a receiving end of an ethernet according to the present invention is described. In this embodiment, the system 30 includes a receiving-end equalizer 301, a clock data recovery module 302, an eye scan module 303, and an equalization adjustment module 304.

The receiving end equalizer 301 is used for receiving an original signal and performing signal compensation. Specifically, the receiving-end equalizer 301 may include a continuous-time linear equalizer CTLE, a voltage gain amplifier VGA, and a decision feedback equalizer DFE, and the original signal is subjected to the CTLE, VGA, and DFE in sequence to complete signal compensation.

The clock data recovery module 302 is configured to receive the original signal compensated by the receiving end equalizer and recover clock data. The recovered clock data is divided into two paths, and the clock data recovery module can send the recovered clock data to the eye pattern scanning module and can also send the recovered clock data to the user side. Therefore, when automatic tuning is carried out, the transmission of user data can not be interrupted, and the re-tuning in the user data transmission process can be realized.

The eye pattern scanning module 303 is configured to sample the clock data to obtain eye pattern data; the equalization adjustment module 304 is configured to obtain a parameter adjustment result based on the eye diagram data, and configure the receiving end equalizer using the parameter adjustment result.

The whole set of receiving end equalizer CTLE/VGA/DFE, wherein the DFE is a decision feedback equalizer and comprises 5 TAPs, the self-adaptive adjustment of the DFE is completed by ASIC logic inside the module, and the DFE can be enabled or closed by the outside or be provided with a forced value to bypass the self-adaptation. The values of the CTLE and the VGA are configured by a balance adjusting module and can also be configured by the outside, wherein the CTLE comprises two taps of C and R which respectively compensate the high-frequency part and the low-frequency part of a signal, and the VGA only has one Tap. The value ranges of the VGA/CTLE _ C/CTLE _ R are all 0-15, and the larger the value is, the larger the compensation force is. The clock data recovery module is used for completing the work of locking the clock signal by the ASIC logic.

Referring to fig. 4, the equalization adjustment module is specifically configured to:

and S51, presetting the initial condition of the receiving end equalizer.

Referring to fig. 5, because the eye scan module has different adaptability to different code patterns, and the more random signal is more stable and reliable, to ensure the adjustment effect, the signal code pattern of the transmitting end should be continuous and sufficiently random, and the long-connection 0-connection 1 condition is avoided. In this embodiment, the reliable code pattern includes an ethernet PCS IDLE code, a user random ethernet packet, and a PRBS.

In a specific presetting process, firstly configuring a universal initial value for the equalizer at the receiving end, and judging whether the eye pattern is opened at the moment; if yes, the following step S52 is executed; if not, the initial value is modified and then whether the eye pattern is opened or not is continuously verified.

In this embodiment, the values configured for the receiving end equalizer include a CTLE high frequency compensation value, a CTLE low frequency compensation value, a VGA value, and a DFE value, and the clock data recovery module 302 can normally operate by presetting these values, and the eye diagram at this time is slightly opened.

In one embodiment, the initial value setting: VGA =5 CTLE _ C =8 CTLE _ R =10 DFE enables adaptation, which enables the clock data recovery module to work normally for signals with link attenuation in the range of 0-25 dB.

And S52, performing coarse adjustment and insertion loss estimation on the initial conditions.

Referring to fig. 6, the steps of coarse tuning and loss estimation specifically include:

firstly, configuring a plurality of groups of preset equalization compensation values according to the size of the insertion loss. For example,

according to application scenes, dividing link insertion loss into 5 grades according to the size:

1, gear 1: 0 to 12dB

2, gear: 12-15 dB

3, gear 3: 15-18 dB

4, gear 4: 18-20 dB

5, gear: >20dB

The insertion loss refers to the insertion loss of Bump-Bump, namely, the insertion loss starts from a pin of a sender serdes in a chip, passes through chip packaging, PCB routing, a connector and a cable, and reaches a connector of an opposite end, the PCB routing, the chip packaging and the pin of the serdes in the chip, and the sum of all losses on the same line.

For the 5 th gear, the compensation force of the equalizer is increasingly greater, and it is determined through experiments that specific configuration values are shown in table 1, where table 1 is a specific configuration value:

serial number	Attenuation range	{VGA, CTLE_C, CTLE_R}	DFE {Tap 1~5}
				1	0~12dB	{6 , 14, 4 }	{0 , 0, 0, 0, 0}
2	12~15dB	{6 , 14, 10}	{0 , 0, 0, 0, 0}
				3	15~18dB	{4 , 14, 12}	{0 , 0, 0, 0, 0}
4	18~20dB	{4 , 14, 12}	{10, 0, 0, 0, 0}
				5	>20dB	{4 , 14, 12}	{20, 5, 0, 0, 0}

In the coarse adjustment stage, because the self-adaptation of the DFE is not controlled by the balance adjustment module, 5 taps of the DFE are configured into fixed values in order to avoid the influence of the self-adaptation of the DFE on the quality judgment of the VGA and the CTLE. All the DFEs of 1-3 groups are 0, namely, enough gain can be obtained only by VGA and CTLE for smaller attenuation. For larger attenuation, only VGA and CTLE are not enough, so 4-5 groups of DFEs have some compensation effects, and then the 5 groups of preset equalization compensation values are stored.

Next, the eye diagram data is initialized:

the index i =0, the eye maximum max-eye =0, the eye maximum is the index max-idx =0, and the current eye cur-eye = 0.

Thirdly, configuring the equalizer at the receiving end according to the preset equalization compensation value, and calling the eye pattern scanning module to acquire current eye pattern data; and after traversing the multiple groups of preset equalization compensation values to configure the eye diagram data after the eye diagram data is validated, determining a group of preset equalization compensation values corresponding to the maximum eye diagram data.

The traversal method is to judge whether i is equal to 5, if so, the value of the equalizer is configured to be the maximum eye value; if not, configuring the value of the equalizer to the ith group; reading the eye height and the eye width, and recording the current eye value cur-eye; judging whether the current eye value cur-eye is larger than the maximum eye value max-eye, if so, taking the current eye value cur-eye as the maximum eye value max-eye, and if not, i + +;

and circulating the traversal until i =5, and ending the traversal.

And setting and configuring 1-5 equalizers to take effect in sequence, and calling an eye pattern scanning module to obtain and record the current eye height and eye width after each configuration is completed. After 5 sets of traversal are completed, find the set of eye diagram data (i.e., the value of eye height + eye width) that is the largest, and reset the equalizer to the set of values. By this method, it is possible to determine the range where the current insertion loss is roughly located, while the equalizer configuration is also matched to the current link conditions.

And finally, configuring the equalizer at the receiving end according to a group of preset equalization compensation values when the eye pattern data is maximum.

S53, determining the state of the DFE.

Referring to fig. 7, specifically, the DFE is first turned off and eye pattern data is obtained; judging whether the eye pattern data are larger than an eye pattern preset value or not; if not, opening the DFE and setting the DFE to be in a self-adaptive state; and if so, executing a step of finely adjusting the CTLE.

For links with particularly desirable signal quality, sufficient gain can be obtained by only VGA and CTLE without introducing DFE compensation. So a decision needs to be made to turn off the DFE if the eye quality after coarse tuning is good enough not to let it participate in the equalization. Instead, the DFE is left in an adaptive state for subsequent adjustments.

In the above determination process, the predetermined value of the eye pattern compared after turning off the DFE needs to be determined according to the specific situation of the system. In one embodiment, the eye height values in the eye diagram data may be compared, for example, the eye height of the whole eye is about 360 mv.

And S54, performing fine adjustment on the CTLE.

Referring to fig. 8, in the fine adjustment process, specifically, after the VGA value and the CTLE high-frequency compensation value are fixed, the eye diagram data when the CTLE low-frequency compensation value CTLE fluctuates in a preset range near the current value is traversed; and configuring the CTLE according to the CTLE low-frequency compensation value corresponding to the obtained maximum eye diagram data.

In an exemplary adjustment process, the CTLE high frequency compensation value is defined as CTLE _ C and the CTLE low frequency compensation value is defined as CTLE _ R. The adjustment method is to make a traversal of the CTLE _ R in the range of plus or minus 3 of the current value, each time adding a value, and then reading and recording the current (eye height + eye width). This finds the group where (eye height + eye width) is the largest and resets CTLE _ R to this value. Thus, one-time automatic tuning of the equalizer is completed, and the tuning process does not affect normal data transmission to the user. The detailed steps are as follows:

step S81: initializing a local variable;

fine tuning start value = (current CTRE-R-3), fine tuning end value end = (current CTRE-R + 3), value of CTRE-R = start, eye maximum value max-eye =0, value of CTLE-R with maximum eye value-max = 0.

Step S82: judging value>end

If not, the step S83 is operated; if yes, step S88 is executed.

Step S83: and (5) making the CTLE-R into value.

Step S84: read (eye height + eye width) and record cur-eye.

Step S85: judging cur-eye>max-eye

If so, step S86 is executed, and if not, step S87 is executed.

Step S86: cur-eye = max-eye, value-max = value.

Step S87: value + +.

Step S88: and the CTLE-R is configured to be value-max.

The automatic tuning system of the Ethernet receiving end equalizer provided by the invention determines the tuning parameter result of the receiving end equalizer by using the eye diagram data, and automatically tunes the serdes receiving end equalizer by combining the coarse tuning and fine tuning modes, so that the signal transmission loss is properly compensated and the receiving end data is correctly recovered under the condition that the current link condition is uncertain, thereby reducing the error rate of the gigabit Ethernet communication and improving the system reliability.

The systems, apparatuses, modules or units described in the above embodiments may be specifically implemented by a computer chip or an entity, or implemented by a product with certain functions.

For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the modules may be implemented in the same one or more software and/or hardware implementations in implementing one or more embodiments of the present description.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

As will be appreciated by one of skill in the art, embodiments of one or more embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

One or more embodiments of the present description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. One or more embodiments of the specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. An automatic tuning system for an equalizer at an ethernet receiving end, the system comprising:

an eye scan module to sample the clock data to obtain eye data;

the equalization adjustment module is used for obtaining a parameter adjustment result based on the eye diagram data and configuring the receiving end equalizer by using the parameter adjustment result;

the receiving end equalizer comprises a Continuous Time Linear Equalizer (CTLE), a Voltage Gain Amplifier (VGA) and a Decision Feedback Equalizer (DFE), and the original signal completes signal compensation after sequentially passing through the CTLE, the VGA and the DFE;

the equalization adjustment module is specifically configured to:

presetting initial conditions of the receiving end equalizer;

determining a state of the DFE;

performing fine adjustment on the CTLE;

wherein determining the state of the DFE specifically comprises:

turning off the DFE and obtaining eye pattern data;

turning on the DFE and setting the DFE to an adaptive state; if so,

the step of fine tuning the CTLE is run.

2. The system according to claim 1, wherein the presetting of the initial conditions of the receiving-end equalizer specifically comprises:

the initial value is modified and verification is continued as to whether the eye is open.

3. The Ethernet receive end equalizer automatic tuning system of claim 2, wherein the values configured for the receive end equalizer comprise CTLE high frequency compensation values, CTLE low frequency compensation values, VGA values, DFE values.

4. The system according to claim 3, wherein the rough adjustment and insertion loss estimation for the initial conditions comprises:

initializing eye pattern data;

calling the eye pattern scanning module to obtain current eye pattern data;

5. The system of claim 4, wherein DFE values in the plurality of sets of equalizer compensation preset values are configured as fixed values when coarse and insertion loss estimates are made for the initial conditions.

6. The system according to claim 3, wherein the fine tuning of the CTLE comprises:

after the VGA value and the CTLE high-frequency compensation value are fixed, eye diagram data when the CTLE low-frequency compensation value fluctuates in a preset range near the current value are traversed;

7. The system of claim 1, wherein the clock data recovery module is further configured to send the recovered clock data to the user side at the same time as sending the recovered clock data to the eye scan module.