JP3099867B2 - Amplitude equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is mainly used for digital microwave communication using a multilevel quadrature amplitude modulation system, and attenuates the amplitude of a specific frequency component due to superposition of a direct wave and an interference wave on a propagation path. And an amplitude equalizer having a function of equalizing.

[0002]

2. Description of the Related Art Conventionally, as an example of this type of amplitude equalizer, there is an adaptive automatic equalizer disclosed in Japanese Patent Application Laid-Open No. 3-220924. FIG. 3 is a circuit block diagram showing a basic configuration of the adaptive automatic equalizer.

[0003] This adaptive automatic equalizer, as shown in the figure,
Primary distortion equalizer 11, resonance type equalizer 12, switch 13,
It comprises a three-wave detector 18, a logic circuit 19, a demodulator 14, an I-channel transversal equalizer 15, a Q-channel transversal equalizer 16, and a phase determining means 17. Here, it has a function of equalizing primary distortion included in the input signal by the primary distortion equalizer 11 or equalizing secondary distortion included in the input signal by the resonance type equalizer 12. Here, as a method of controlling the equalizer, the first-order distortion equalizer 11 is controlled by the transversal equalizers 15 and 1.
6, the center tap value of each of the orthogonal I and Q channels is used.
The phase information of the signals before and after the transversal equalizer 16 obtained in step 7 is used. Accordingly, when the non-minimum phase fading which cannot be equalized in the resonance type equalizer 12, that is, fading in which the interference wave is advanced from the main wave in the two-wave interference fading is detected, the waveform equalizing operation is stopped. Control.

Another example of an amplitude equalizer is disclosed in
-46829 discloses a demodulation device. FIG. 4 is a circuit block diagram showing a basic configuration of the demodulation device.

[0005] The demodulator adaptive amplitude equalizer 21 comprising a control signal generating means 23 to provide a connected adaptive equalization means 22 and the control signal to the input terminal T _I, demodulator 2
4, disconnection detection circuit 25, and two output terminals T _O 1 and T _O
2 is provided with a transversal equalizer 26 which is connected to the transversal equalizer 26. Here, the disconnection detection circuit 25 detects a signal disconnection from the demodulator 4, and when the disconnection is detected, the equalizing operation of the adaptive equalizer 22 and the transversal equalizer 26 is reset. By this reset operation, when deep fading occurs in the propagation path and the demodulated signal in the demodulator 24 is interrupted due to loss of synchronization or the like, it is possible to easily perform synchronization pull-in at the time of re-locking.

Further, the disadvantage that the equalizer of the resonance type equalizer 12 in the non-minimum phase fading in the adaptive automatic equalizer shown in FIG. Another example of an amplitude equalizer that repeatedly performs a reset operation in order to facilitate synchronization at the time of re-locking when demodulation output is abnormal due to loss of synchronization of the demodulator 24 in the demodulation device is disclosed in JP-A-4-2227.
The automatic adaptive equalizer according to Japanese Patent Application Laid-Open Publication No. HEI 9-86, 1989. FIG.
FIG. 2 is a circuit block diagram showing a basic configuration of the automatic adaptive equalizer.

As shown, the automatic adaptive automatic equalizer includes a variable amplitude equalizer 10 including a secondary amplitude distortion equalizer 1 and a primary amplitude distortion equalizer 2, a demodulation circuit 3, and a wave type. The control circuit includes an equalizing circuit 4, two reset circuits 6, 7, and a control signal generating circuit 8. However, here, the out-of-synchronization detector and the oscillator are illustrated in the form of being included in the demodulation circuit 3, and the waveform equalization circuit 4 as a decision feedback equalizer is generally based on the point of the feasibility of the circuit configuration. The circuit configuration disclosed in consideration of the use of the band and digital processing type is modified and arranged at the subsequent stage of the demodulation circuit 3.
Also, the variable amplitude equalizer 10 here is configured by applying the one proposed in Japanese Patent Application No. 54-156610 as an example and changing the delay amount of the delay line.

Here, a secondary amplitude distortion equalizer 1 for secondary amplitude distortion equalization and a primary amplitude distortion equalizer 2 for primary amplitude distortion equalization are provided. , 2 are connected to reset circuits 6 and 7 for inputting and outputting a control signal, and perform a reset operation in order to easily pull in the synchronization at the time of re-pulling in the event of abnormal demodulation output due to the loss of pull-in of the demodulation circuit 3. Repeat. Thus, even if the amplitude is changed, the delay characteristic with respect to the frequency is always constant. Therefore, the minimum phase in the propagation path, that is, fading in which the interference wave is delayed from the main wave in two-wave interference fading, or non-minimum. The same equalization characteristics can be obtained regardless of the occurrence of any phase fading. Further, the control signal generating circuit 8 includes each of the amplitude distortion equalizing circuits 1 and
2 is performed, and the control means here is disclosed in Japanese Patent Application No. 58-0.
No. 68635 discloses a control technique for detecting a secondary amplitude distortion and a primary amplitude distortion included in an eye pattern after demodulation identification and minimizing these. Further, the waveform equalization circuit 4 as a transversal equalizer uses a decision feedback type equalizer having a relatively simple circuit configuration and a large equalization capability. This decision feedback equalizer uses a reference signal obtained by determining a transversal filter output instead of directly using an equalizer input signal for a tap temporally before a center tap of a transversal filter. In particular, the equalizing effect at the time of fading in the minimum phase due to two-wave interference fading is extremely large.
Incidentally, a well-known document relating to this decision feedback type equalizer is described in “Application of Digital Signal Processing” edited by the Institute of Electronics and Communication Engineers, pp. 56-5-20. 163.

[0009]

In the case of the automatic adaptive equalizer shown as another example of the above-mentioned amplitude equalizer, if fading that exceeds the equalizing capability of the amplitude distortion equalizing circuit occurs on the propagation path, the amplitude becomes smaller. In some cases, the distortion equalization circuit malfunctions and the quality of the transmission signal (received signal) is degraded.

More specifically, in this automatic adaptive type equalizer, fading that exceeds the equalizing capability of the amplitude distortion equalizing circuit occurs. For example, the frequency spectrum of the transmission signal changes with respect to the center frequency fc as shown in FIG. FIG. 7 (a) is a diagram illustrating a received signal in the second-order amplitude distortion equalizing circuit, which is changed from one mode S1a as shown in FIG. 7A by the frequency characteristic of the propagation path and received as another mode S1b as shown in FIG. The amplitude characteristics are shown in the form S1c, 1 as shown in FIG.
The amplitude characteristic of the received signal in the next amplitude distortion equalization circuit is changed to the form S1d as shown in FIG.
As a result, the frequency spectrum relating to the output of the variable amplitude equalizer changes to the form S1e as shown in FIG. 10A with respect to the center frequency fc. Here, since the amount of fading exceeds the equalizing capability of the amplitude equalizer, a residual distortion shown as a shaded portion occurs in the form S1e.

Similarly, the frequency spectrum of the transmission signal is changed from the form S2a as shown in FIG. 6B with respect to the center frequency fc by the frequency characteristic of the propagation path, as shown in FIG.
When received as another mode S2b as shown in FIG. 8B, the amplitude characteristic of the received signal in the secondary amplitude distortion equalization circuit is changed to the mode S2c as shown in FIG. The amplitude characteristic of the received signal in the circuit is changed to the form S2d as shown in FIG. As a result, the frequency spectrum related to the output of the variable amplitude equalizer changes to the form S2e as shown in FIG. 10B with respect to the center frequency fc.

That is, in this amplitude equalizer, a control signal generating circuit 8 for controlling each of the amplitude distortion equalizing circuits 1 and 2 detects the amplitude distortion component of the demodulated signal of the demodulator 3 and outputs the second amplitude distortion. 1
10 is controlled so as to minimize the respective next-order amplitude distortions.
In the case where a residual distortion as shown by a hatched portion in (a) occurs, the variable amplitude equalizer detects this as a residual primary distortion component and at the same time detects it as a residual secondary distortion component. Since the secondary amplitude distortion equalization circuit provides a concave (convex downward) frequency characteristic as shown in FIG. 8B to equalize the frequency spectrum, the frequency spectrum related to the output of the variable amplitude equalizer Is finally added to form S2e as shown in FIG. 10 (b).

Therefore, in this amplitude equalizer, when the second-order amplitude distortion equalizing circuit provides the concave frequency characteristic shown in FIG. 8B, the center frequency fc component of the received signal decreases, and as a result, The signal quality deteriorates.

Incidentally, when residual distortion occurs in the output of such a variable amplitude equalizer, the amplitude distortion equalizing circuit that detects the malfunction may be malfunctioned, especially when a decision feedback type equalizer is used as the waveform equalizer. Is known to be noticeable. This is because the equalization effect of the decision feedback equalizer is extremely large, so even if fading exceeding the capability of the amplitude distortion equalizer circuit occurs and residual distortion occurs at the output of the amplitude distortion equalizer circuit, This is because the transmission signal can be reproduced and identified by the waveform equalizing operation of the waveform equalizing circuit.

However, the configuration S1 shown in FIG.
Compared with e, the form S2e as shown in FIG. 10B is provided with a downwardly convex frequency characteristic, so that when this is processed as an in-circuit signal, the waveform equalization in the waveform equalization circuit is performed. The operation is not performed sufficiently, and the quality of the transmission signal is significantly deteriorated.

The present invention has been made to solve such a problem, and its technical problem is that even when fading that exceeds the equalization capability of an amplitude distortion equalization circuit occurs on a propagation path, a variable amplitude An object of the present invention is to provide an amplitude equalizer that can prevent a malfunction of an equalization operation of a received signal of an equalizer and can improve the quality of a transmission signal.

[0017]

According to the present invention, in an amplitude equalizer used in a multilevel quadrature amplitude modulation system, an Nth-order amplitude distortion (where N is a natural number and ), A demodulation circuit that demodulates the equalized received signal and outputs a demodulated signal, and a control signal for controlling the variable amplitude equalizer according to the demodulated signal. A control signal generation circuit for generating a demodulated signal, a waveform equalization circuit for performing waveform equalization on the time axis of the demodulated signal, a residual distortion detection circuit for detecting residual distortion of the demodulated signal and outputting a reset instruction signal, and a reset. An amplitude equalizer having a reset circuit for outputting a reset signal for resetting the control signal in response to the instruction signal is obtained.

According to the present invention, in the above-mentioned amplitude equalizer, the variable amplitude equalizer includes a K-th order amplitude distortion equalizing circuit based on K of 1 or more and N or less. The circuit detects a residual distortion of the demodulated signal and outputs a reset instruction signal in accordance with a value of a J-order amplitude distortion based on J (where J ≠ K) of 1 or more and N or less that remains. An amplitude equalizer that inputs a control signal from the control signal generation circuit to the K-order amplitude distortion equalization circuit in response to the reset instruction signal and resets the equalization of the K-order amplitude distortion equalization circuit is obtained.

Further, according to the present invention, in any one of the above amplitude equalizers, the waveform equalization circuit outputs a tap coefficient signal indicating a plurality of weighted tap coefficients in a time series. The distortion detection circuit resets by comparing the residual amplitude distortion amount of the demodulated signal obtained by calculating the weight of the tap coefficient based on the tap coefficient signal with a specified value that depends on the equalizing capability of the variable amplitude equalizer. An amplitude equalizer that outputs an instruction signal is obtained.

[0020]

According to the amplitude equalizer of the present invention, the residual value of the first-order distortion at the output of the variable amplitude equalizer based on the tap coefficient signal indicating the weighted state of the plurality of tap coefficients in the time series in the waveform equalizing circuit. Is large, the residual distortion of the primary distortion is detected by the residual distortion detection circuit, and the control signal from the control signal generation circuit is used to reset the secondary amplitude distortion equalization circuit. A reset instruction signal is sent to the circuit. Due to this reset function, deep fading occurs in a transmission signal input as a reception signal, and large first-order distortion occurs. Even when the residual value of the first-order distortion is large, malfunction of the secondary amplitude distortion equalization circuit can be prevented. .
For this reason, distortion addition in the amplitude distortion equalization circuit in the variable amplitude equalizer is prevented, and the quality of the transmission signal is improved.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to one embodiment of the present invention.

This amplitude equalizer receives a tap coefficient signal 105 indicating a weighted state of a plurality of tap coefficients in a time series in the waveform equalizing circuit 4 as compared with the conventional one shown in FIG. And a residual distortion detection circuit 5 for transmitting a reset instruction signal 106 is provided. Other components are common, and include a variable amplitude equalizer 10 including a secondary amplitude distortion equalization circuit 1 and a primary amplitude distortion equalization circuit 2, a demodulation circuit 3, a wave type equalization circuit 4, and two The circuit includes reset circuits 6 and 7 and a control signal generation circuit 8, and is also applied in a multilevel quadrature amplitude modulation method.

The demodulation circuit 3 includes a variable amplitude equalizer 1
Carrier synchronization, demodulation, and identification are performed on the received signal 101 that has undergone amplitude equalization at 0, and a demodulated signal 104 is output. The waveform equalizing circuit 4 shapes the waveform of the demodulated signal 104, removes intersymbol interference, performs waveform equalization on the time axis, and outputs the output signal 102.
And outputs a tap coefficient signal 105 indicating a plurality of weighted tap coefficients in the time series described above. The control signal generation circuit 8 sends out control signals 108 and 109 to the secondary amplitude distortion equalization circuit 1 and the primary amplitude distortion equalization circuit 2 in the variable amplitude equalizer 10 to receive the reception signal 101.
Is controlled so as to minimize the second-order amplitude distortion and the first-order amplitude distortion included in. The residual distortion detection circuit 5 has a function of inputting the tap coefficient signal 105 and detecting a primary amplitude distortion component included in the demodulated signal 104 input to the waveform equalization circuit 4, and having a primary amplitude distortion of a specified value. Is exceeded, a reset instruction signal 106 for resetting the secondary amplitude distortion equalization circuit 1 is sent to the reset circuit 6. The reset circuit 6 inputs and outputs a control signal 108 for secondary amplitude distortion equalization from the control signal generation circuit 8, and the reset circuit 7 receives a control signal 109 for primary amplitude distortion equalization from the control signal generation circuit 8. The reset circuit 6 outputs a reset signal 107 upon input of the reset instruction signal 106 from the residual distortion detection circuit 5 to reset the demodulation operation of the demodulation circuit 3 and the waveform equalization operation of the waveform equalization circuit 4. At the same time, the primary amplitude distortion equalization circuit 2 is reset via the secondary amplitude distortion equalization circuit 1 and the reset circuit 7 to return the control signals 108 and 109 to their initial values.

FIG. 2 is a circuit block diagram showing a detailed configuration of the residual distortion detection circuit 5. The residual distortion detection circuit 5 includes a predetermined number of lines for inputting a tap coefficient signal 105 including weights of tap coefficients for five taps on the orthogonal side of each I-CH and Q-CH orthogonal to each other; An arithmetic circuit including a subtractor 31 and an adder 32 inserted in each line, a register 34 and a comparator 33 are provided. However, as long as the output of the tap coefficient is three or more taps including the center tap, any value can be applied.

The calculation method here is based on the tap coefficient signal 10
5 is input to the arithmetic circuit, and the first-order amplitude distortion amount of the residual distortion included in the demodulated signal 104 is calculated by calculating each tap coefficient before and after the center tap.

More specifically, the operation here is performed by the subtractor 3
1 and the adder 32.
The primary amplitude distortion amount proposed in -068635 is Im
According to the absolute value of (−N) −Im (+ N), where N = 1, 2, the primary amplitude distortion here is the value obtained by adding Ich and Qch, that is, CI ⁱ (− 1) -CI ⁱ (+
1), the absolute value of CI ⁱ (−2) −CI ⁱ (+2), the absolute value of CQ ⁱ (−1) −CQ ⁱ (+1),
The value obtained by adding the absolute value of CQ ⁱ (−2) −CQ ⁱ (+2) is used. This added output is input to a comparator 33, and is compared with a value of a register 34 predetermined by the equalization capability of each of the amplitude distortion equalization circuits 1 and 2, and the comparison result is sent to a reset circuit 6 as a reset instruction signal 106. Is done.

By the way, in the amplitude equalizer having such a configuration, even if fading which exceeds the equalization capability of the amplitude distortion equalization circuits 1 and 2 occurs, a malfunction of the equalization operation of the variable amplitude equalizer 10 is prevented. Can be prevented.

That is, also here, the frequency spectrum of the transmission signal changes from the form S1a as shown in FIG. 6A with respect to the center frequency fc by the frequency characteristic of the propagation path, and is shown in FIG. 7A. A case in which the data is received as such another mode S1b will be described.

In this case, the amplitude characteristic of the received signal 101 is 2
The waveform is shaped by the first-order amplitude distortion equalization circuit 1 and the first-order amplitude distortion equalization circuit 2, and at this time, the first-order distortion in the received signal 101 cannot be completely equalized by the first-order amplitude distortion equalization circuit 2. Therefore, at the output of the variable amplitude equalizer 10, the frequency spectrum is shown in FIG.
Residual distortion as shown in the form S1e shown in FIG. Therefore, the residual distortion detection circuit 5 computes and calculates the primary amplitude distortion component of the residual distortion by computing each tap coefficient of the transversal filter. As a result, the residual distortion detecting circuit 5 resets the secondary amplitude distortion equalizing operation when the primary amplitude component exceeds the threshold value determined in advance by the equalizing capability of the secondary amplitude distortion equalizing circuit 1. Is output.

As described above, when the secondary amplitude distortion equalizing operation is reset, a concave frequency characteristic due to a malfunction of the secondary distortion amplitude distortion equalizing circuit 1 due to residual distortion is not given. The frequency spectrum of the output of the device 10 remains in the form S1e shown in FIG. Therefore,
The output of the variable amplitude equalizer 10 is received by the waveform equalizing circuit 4 since the waveform equalizing operation of the waveform equalizing circuit 4 is sufficiently performed as compared with the form S2e shown in FIG. Good quality of the signal 101 is maintained.

Incidentally, when the demodulation output is abnormal due to the de-synchronization of the demodulation circuit 3 or the like, the secondary amplitude distortion equalization circuit 1, the primary amplitude distortion equalization circuit 2, And the reset operation is repeatedly performed on the waveform equalization circuit 4.

In the embodiment, the variable amplitude equalizer 10 comprises the secondary amplitude distortion equalizer 1 and the primary amplitude distortion equalizer 2, but the variable amplitude equalizer 10 generally comprises
N-order amplitude distortion (where N is a natural number) on the frequency axis of 1 is variably equalized, and a K-order amplitude distortion equalization circuit based on K of 1 or more and N or less is included. Can be. In this case, the residual distortion detection circuit 5 outputs the demodulated signal 1
The residual strain of No. 04 is detected and the remaining J is 1 or more and N or less.
(However, a reset instruction signal is output according to the value of the J-order amplitude distortion based on J ≠ K), and the reset circuit corresponding to the K-order amplitude distortion equalization circuit to which the reset instruction signal is input is a control signal generation circuit 8. It is only necessary to have a basic function of inputting a control signal to the K-th order amplitude distortion equalization circuit from the controller and resetting the equalization of the K-order amplitude distortion equalization circuit.

[0034]

As described above, according to the amplitude equalizer of the present invention, even if fading that exceeds the equalization capability of the amplitude distortion equalization circuit occurs on the propagation path, the variable amplitude equalizer can be used. Since a residual distortion detection circuit for detecting residual distortion of the output is provided and the operation of the amplitude distortion equalization circuit in the variable amplitude equalizer is controlled based on the distortion detection result, the amplitude distortion equalization circuit is provided. Erroneous operation of the equalizing operation in the first embodiment can be prevented. As a result, the quality of the transmission signal (received signal) is improved.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to one embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a detailed configuration of a residual distortion detection circuit provided in the amplitude equalizer shown in FIG.

FIG. 3 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to a conventional example.

FIG. 4 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to another conventional example.

FIG. 5 is a circuit block diagram showing a basic configuration of an amplitude equalizer according to another conventional example.

FIG. 6 shows a frequency spectrum of a transmission signal received and input to the amplitude equalizer shown in FIG. 1 or 5;
(A) relates to one example of one embodiment, and (b) relates to another example of one embodiment.

7 shows a frequency spectrum of a received signal received and input to the amplitude equalizer shown in FIG. 1 or FIG. 5,
(A) relates to an example which has changed from the form of FIG. 6 (a), and (b) relates to another example which has changed from the form of FIG. 6 (b).

8 is a diagram illustrating a second example provided in the amplitude equalizer shown in FIG. 1 or FIG.
7A shows amplitude characteristics of a received signal in the next-order amplitude distortion equalization circuit, where FIG. 7A shows an example corresponding to the form of FIG. 7A and FIG. 7B shows an example according to the form of FIG. 7B. It concerns another example.

FIG. 9 is a diagram illustrating a configuration of the amplitude equalizer shown in FIG. 1 or FIG.
7A shows amplitude characteristics of a received signal in the next-order amplitude distortion equalization circuit, where FIG. 7A shows an example corresponding to the form of FIG. 7A and FIG. 7B shows an example according to the form of FIG. 7B. It concerns another example.

10 shows a frequency spectrum related to the output of a variable amplitude equalizer provided in the amplitude equalizer shown in FIG. 1 or FIG. 5, wherein FIG. 10A shows an example of a change from the form of FIG. FIG. 7B relates to another example that has changed from the form of FIG. 7B.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Secondary amplitude distortion equalization circuit 2 Primary amplitude distortion equalization circuit 3 Demodulation circuit 4 Waveform equalization circuit 5 Residual distortion detection circuit 6, 7 Reset circuit 8 Control signal generation circuit 10 Variable amplitude equalizer 31 Subtractor 32 Addition Unit 33 comparator 34 register 101 reception signal 102 output signal 104 demodulation signal 105 tap coefficient signal 106 reset instruction signal 107 reset signal 108, 109 control signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03H 15/00-15/02 H03H 19/00 H03H 21/00 H04B 1/76-3/44 H04B 3 / 50-3/60 H04B 7/005-7/015 H04L 27/00-27/30

Claims (3)

(57) [Claims] 1. An amplitude equalizer used in a multilevel quadrature amplitude modulation system, wherein a variable amplitude or the like for variably equalizing N-order amplitude distortion (N is a natural number) on a frequency axis of a received signal. An equalizer, a demodulation circuit for demodulating the equalized received signal and outputting a demodulated signal, and a control signal generating circuit for generating a control signal for controlling the variable amplitude equalizer in accordance with the demodulated signal A waveform equalization circuit that performs waveform equalization on the time axis of the demodulated signal, a residual distortion detection circuit that detects a residual distortion of the demodulated signal and outputs a reset instruction signal, and responds to the reset instruction signal. A reset circuit for outputting a reset signal for resetting the control signal. 2. The amplitude equalizer according to claim 1, wherein said variable amplitude equalizer includes a K-order amplitude distortion equalization circuit based on K equal to or larger than 1 and equal to or smaller than N, and wherein said residual distortion detection is performed. The circuit detects the residual distortion of the demodulated signal and outputs the reset instruction signal according to the value of the J-order amplitude distortion based on J (where J ≠ K) which is 1 or more and N or less, and outputs the reset instruction signal. The circuit inputs the control signal from the control signal generation circuit to the K-order amplitude distortion equalization circuit in response to the reset instruction signal, and resets the equalization of the K-order amplitude distortion equalization circuit. And an amplitude equalizer. 3. The amplitude equalizer according to claim 1, wherein said waveform equalization circuit outputs a tap coefficient signal indicating a plurality of weighted tap coefficients in a time series, and said residual distortion The detection circuit compares the residual amplitude distortion amount of the demodulated signal obtained by calculating the weight of the tap coefficient based on the tap coefficient signal with a specified value depending on the equalization capability of the variable amplitude equalizer. An amplitude equalizer for outputting the reset instruction signal.