CN109379307A - A kind of continuous-time equalizer circuit of high-speed serial communication - Google Patents
A kind of continuous-time equalizer circuit of high-speed serial communication Download PDFInfo
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- CN109379307A CN109379307A CN201811358584.4A CN201811358584A CN109379307A CN 109379307 A CN109379307 A CN 109379307A CN 201811358584 A CN201811358584 A CN 201811358584A CN 109379307 A CN109379307 A CN 109379307A
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- signal
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- serial communication
- time equalizer
- speed serial
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
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- Computer Networks & Wireless Communication (AREA)
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- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The invention discloses a kind of continuous-time equalizer circuit of high-speed serial communication, the equalizer carries out independent equilibrium using DC channel and the structure of alternating current path two-way equilibrium, and merges in output end, to carry out system equalization to receiving end signal.Trsanscondutance amplifier is used in DC channel, and high-pass filter and trsanscondutance amplifier are respectively equipped in alternating current path.For the present invention on the basis of conventional equalizer structure, the balanced device of proposition can be directed to DC current gain respectively, and the gain that zero pole point position and high-frequency signal compensate is independently controlled, and increases the freedom degree of balanced device control, application is more flexible；The present invention is using digital control, and the antinoise of digital signal and interference performance are stronger when having better accuracy, and controlling, and control precision is more preferable, easily controllable；Equaliser structure of the invention is compact, can provide more flexible and more accurate signal equalization using multi-channel parallel as high performance equalizer.
Description
Technical field
The present invention relates to a kind of balanced device, in particular to the continuous-time equalizer circuit of a kind of high-speed serial communication belongs to
In IC design and the field of test technology.
Background technique
Continuous-time equalizer main function applied to high-speed serial communication (SerDes) is that thermal compensation signal passes through channel
Loss of signal and decaying after (cable transmission signal), so that receiving end be made to carry out clock and data recovery (CDR, Clock Data
The bit error rate (BER, Bit Error Rate) is reduced when Recovery).In document A0.18-um CMOS 3.5-Gb/s
Continuous-Time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain
Control Method, document A 10-Gb/s Receiver With Series Equalizer and On-Chip ISI
Monitor in 0.11-um CMOS and document A 20-Gb/s Adaptive Equalizer in 0.13-um CMOS
The continuous-time equalizer of the trsanscondutance amplifier using analog voltage control is proposed in Technology.
However when being applied to different channel progress serial communications, have the following problems:
First, the precision problem of analog signal control, the DC current gain that need to be compensated, when being communicated for high-speed digital signal
Power spectrum compensation frequency range etc. is all made of analog voltage signal and is controlled, and control levels of precision is insufficient.
Second, which can control DC current gain and frequency bandwidth control, carry out to the signal of transmission
Compensation, however the gain compensation value in high fdrequency component is unfavorable for individually controlling by the above two association, to cause to compensate
Effect is not good enough.
Compensation control in document is as shown in Figure 1.
High-speed digital signal serial communication is widely used in electronic system, such as USB data transmission, and solid state hard disk data are transmitted,
The occasions such as high-speed wired communication.Usual situation is transmitted using differential signal, and the module of the communication system can be divided into transmitting
It holds (TX), receiving end (RX), and the transmission medium channel (Channel) of both connections.Due to channel have skin effect and
Dielectric loss, therefore there is loss and decaying in signal, and the frequency dependence with signal of decaying in transmission process.
When receiving end receives deamplification it may first have to pass through signal equalization, compensates the decaying of channel, it is basic herein
On carry out and reducing the reception bit error rate for the clock and data recovery for receiving data again.Fig. 2 is the framework of balanced device, needle
The different frequency spectrum component of signal is compensated, is decoded to obtain preferable thermal compensation signal for data.
Summary of the invention
In order to solve the problems such as compensating the independent control gain compensation for controlling precision and high fdrequency component as described above, this
Invention proposes a kind of circuit structure of continuous-time equalizer, by independent to input signal progress DC channel and alternating current path
It compensates and is controlled with gain, and accurately controlled using numerically controlled mode, to improve the balanced effect of balanced device
Fruit.
The present invention adopts the following technical scheme:
A kind of continuous-time equalizer circuit of high-speed serial communication, the equalizer using DC channel with exchange
The structure of access two-way equilibrium carries out independent equilibrium, and merges in output end, so that it is equal to carry out system to receiving end signal
Weighing apparatus.
Further, trsanscondutance amplifier is used in DC channel, and high-pass filter is respectively equipped in alternating current path
And trsanscondutance amplifier.
Further, the continuous-time equalizer circuit of the high-speed serial communication includes continuous-time equalizer, is connect
Power indication circuit is received, voltage is converted to current module, and receives clock and data recovery module.
Further, it receives signal RX in enter after continuous-time equalizer, carries out signal equalization, referred to by power
Show that circuit carries out the signal detection and assessment of receiving end, and generates a voltage signal corresponding with power is received, the voltage
Signal is input to voltage and is converted to current module, is converted to current module as voltage and converts voltages into needed for switching current and opens
OFF signal, to controlling including gain, poles and zeros assignment for balanced device, the signal after equilibrium is by reception clock and data recovery mould
Block carries out clock and data recovery, to obtain the lower reception data of the bit error rate, and carries out follow-up data processing.
Further, the ssystem transfer function of entire balanced device are as follows:
Further, the reception power indication circuit is realized by gilbert mixer, and gilbert mixer produces
Raw signal is input to the voltage and is converted to current module, after which carries out analog-to-digital conversion, is carried out by digital module
Reason, filters out noise and interference, and switching signal shc, shr, sdc and sac needed for generating balanced device.
Further, in DC channel, the tail current of trsanscondutance amplifier carries out digital control, switching signal by switch
It is multistation digital signal for sdc, can control multiple current sources；In alternating current path, the circuit and direct current of trsanscondutance amplifier are logical
Similar in road, switching signal sac is multistation digital signal, can control multiple current sources, the high-pass filtering in alternating current path
Device, two groups of long numbers switch shr and shc, respectively controls resistance value and capacitance.
The continuous-time equalizer that the present invention describes can be used as equalizer unit, by more balanced devices in parallel, from
And carry out increasingly complex precise equalization.The invention has the following beneficial effects:
(1) for the present invention on the basis of conventional equalizer structure, the balanced device of proposition can be directed to DC current gain respectively, and zero
Pole location (i.e. bandwidth needed for high-frequency signal compensation) and the gain of high-frequency signal compensation are independently controlled, and are increased
The freedom degree of balanced device control, application are more flexible.
(2) balanced device that the present invention describes is using digital control, digital signal when having better accuracy, and controlling
Antinoise and interference performance it is stronger, control precision it is more preferable, it is easily controllable.
(3) equaliser structure that the present invention describes is compact, can provide more flexible using multi-channel parallel as high performance equalizer
More accurate signal equalization.
(4) equaliser scheme that theory and practice proves that the present invention describes is feasible.
Detailed description of the invention
Fig. 1 is the compensation control figure in background technology document.
Fig. 2 is the signal equalization theoretical diagram of balanced device.
Fig. 3 is the equalizer bay composition that the present invention describes.
Fig. 4 is the balanced device amplitude-frequency response figure that the present invention describes.
Fig. 5 is the receiving terminal circuit block diagram that the present invention describes.
Fig. 6 is the equalizer figure that the present invention describes.
Fig. 7 is the balanced device amplitude-frequency response that describes of the present invention and digital control.
Fig. 8 is the power indication circuit diagram that the present invention describes.
Fig. 9 is the V-I Converter figure that the present invention describes.
Figure 10 is the loss of signal and attenuation characteristic figure that the present invention describes.
Figure 11 is the amplitude-frequency response figure for the balanced device that the present invention describes.
Figure 12 is the DC current gain figure for the digital switch sdc control that the present invention describes.
Figure 13 is the high-frequency gain figure for the digital switch sac control that the present invention describes.
Figure 14 is the zero point z and the pole p1 location drawing for the digital switch shc control that the present invention describes.
Figure 15 is the zero point z and the pole p1 location drawing for the digital switch shr control that the present invention describes.
Figure 16 is frequency response curve after the equilibrium that the present invention describes.
Figure 17 is the signal eye diagram that receiving end receives after loss of signal and decaying that the present invention describes.
Figure 18 is the signal eye diagram of receiving end after equilibrium that the present invention describes.
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.
One, design philosophy of the invention
On the basis of conventional equalizer structure, the present invention using DC channel and alternating current path two-way equilibrium structure into
Row is independent balanced, and merges in output end, to carry out system equalization to receiving end signal.Its circuit block diagram such as Fig. 3 institute
Show, trsanscondutance amplifier is used in DC channel, there is high-pass filter and trsanscondutance amplifier respectively in alternating current path.
The present invention proposes that the theory analysis of the above circuit structure is as follows:
When being communicated due to high speed signal, the parasitic capacitance effect in circuit is inevitable, therefore in DC channel
The transmission function of trsanscondutance amplifier can indicate are as follows:
High-pass filter (HPF) transmission function in alternating current path are as follows:
The transmission function of trsanscondutance amplifier in alternating current path are as follows:
Therefore, the ssystem transfer function of entire balanced device are as follows:
The complete transmission function of whole system is comprising three poles and two zero points, which is difficult to analyze.
It is assumed that the trsanscondutance amplifier of DC channel and alternating current path has approximate parameter, then the transmission function of balanced device can be close at this time
Like the system for being two poles and a zero point, wherein zero point is z, and pole is respectively p1 and p2.The specific location of zero pole point closes
System is as shown in figure 4, the frequency response curve can be used for carrying out signal equalization.
Two, concrete scheme of the invention
For circuit structure proposed by the present invention, the realization of physical circuit is carried out using following scheme.
The circuit framework for receiving balanced device is as shown in Figure 5.Including continuous-time equalizer (Continuous), receive
Power indication circuit (Power Indicator), voltage are converted to current module (V-I Converter), and receive clock
Data recovery module (CDR).
Detailed circuit operation principle is as follows:
After receiving signal RX in and entering continuous-time equalizer, signal equalization is carried out, at this time by power indication circuit
The signal detection and assessment of receiving end are carried out, and generates a voltage signal corresponding with power is received, the voltage signal is defeated
Enter to after V-I Converter module, switching signal needed for converting voltages into switching current as the module, to balanced device
Gain, poles and zeros assignment etc. are controlled, to preferably carry out signal equalization.When signal after equilibrium is carried out by CDR module
Clock data are restored, to obtain the lower reception data of the bit error rate, and carry out follow-up data processing.
Continuous-time equalizer circuit structure proposed by the present invention is as shown in Figure 6.The circuit include direct current with exchange two
Access.
In DC channel, the tail current of trsanscondutance amplifier is digital control by switch progress, and switching signal sdc is more
Position digital signal can control multiple current sources.In alternating current path, the circuit of trsanscondutance amplifier is similar with DC channel,
Switching signal is sac, is multistation digital signal, can control multiple current sources.High-pass filter (HPF) in alternating current path,
Control resolution ratio, two groups of long numbers switch shr and shc, respectively to resistance value and capacitance are improved in order to be combined control
It is controlled.
By theory analysis, the transmission function of the physical circuit derives as follows:
The transmission function can simplify after approximation as two levels of a zero point z and two poles p1 and p2 composition
System.
Therefore, the frequency response of the continuous-time equalizer is as shown in Figure 7.
Wherein, DC current gain part is carried out digital control by multi-position switch sdc, zero point z and the position pole p1 (corresponding high frequency
The compensation bandwidth of component) it is digital control by multi-position switch shc and shr progress, pole location p2 and high-frequency gain are by multi-position switch
Sac carries out digital control.
The circuit of power indication module is realized that circuit diagram is as shown in Figure 8 by gilbert mixer.
The derivation of the mixer are as follows:
It is assumed that input signal are as follows:
vi=ancos(ωt)
=ancos(2πft)
The self-mixing function of the signal at this time are as follows:
Wherein, self-mixing generates DC component and AC compounent.AC compounent frequency is twice of the signal frequency, in height
In fast serial communication, since transmission frequency is very high, the component dead resistance and capacitor of two frequency multiplication parts of the frequency
It filters out.
The load RL of the gilbert mixer can be multiplexed with equalizer section.
In V-I Converter module, gilbert mixer generate signal be input to the module, the voltage signal into
It after row analog-to-digital conversion, is handled by digital module, filters out noise and interference, and switching signal shc needed for generating balanced device,
Shr, sdc and sac.As shown in Figure 9.
Three, implementation and verifying of the invention
By taking the transmission of solid-state disk data as an example, feasibility of the invention is demonstrated.
Transmission channel is transmitted using cable, and loss and attenuation characteristic are as shown in Figure 10；The amplitude-frequency response of balanced device
As shown in figure 11；The DC current gain of digital switch sdc control is as shown in figure 12；The high-frequency gain of digital switch sac control is as schemed
Shown in 13；The zero point z of digital switch shc control and the position pole p1 are as shown in figure 14；Digital switch shr control zero point z and
The position pole p1 is as shown in figure 15；Frequency response curve after equilibrium, the gain in passband is more steady, can achieve good
Good portfolio effect, as shown in figure 16.
After loss of signal and decaying, the signal eye diagram that receiving end receives is as shown in figure 17；After equilibrium, receive
The signal eye diagram at end is as shown in figure 18.
The above verifying illustrates that technical solution of the present invention is feasible.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention.It is all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (7)
1. a kind of continuous-time equalizer circuit of high-speed serial communication, it is characterised in that: the equalizer uses direct current
Access and the structure of alternating current path two-way equilibrium carry out independent equilibrium, and merge in output end, thus to receiving end signal
Carry out system equalization.
2. the continuous-time equalizer circuit of high-speed serial communication according to claim 1, it is characterised in that: logical in direct current
Trsanscondutance amplifier is used in road, and high-pass filter and trsanscondutance amplifier are respectively equipped in alternating current path.
3. the continuous-time equalizer circuit of high-speed serial communication according to claim 1 or 2, it is characterised in that: described
The continuous-time equalizer circuit of high-speed serial communication includes continuous-time equalizer, receives power indication circuit, voltage conversion
For current module, and reception clock and data recovery module.
4. the continuous-time equalizer circuit of high-speed serial communication according to claim 3, it is characterised in that: receive signal
RX in enters after continuous-time equalizer, carry out signal equalization, by power indication circuit carry out receiving end signal detection and
Assessment, and a voltage signal corresponding with power is received is generated, which is input to voltage and is converted to current module,
Switching signal needed for current module converts voltages into switching current is converted to as voltage, what it is to balanced device includes gain, zero
Pole distribution is controlled, and the signal after equilibrium carries out clock and data recovery by reception clock and data recovery module, to obtain
The lower reception data of the bit error rate, and carry out follow-up data processing.
5. the continuous-time equalizer circuit of high-speed serial communication according to claim 1 or 2, it is characterised in that: entire
The ssystem transfer function of balanced device are as follows:
6. the continuous-time equalizer circuit of high-speed serial communication according to claim 1 or 2, it is characterised in that: described
It receives power indication circuit to be realized by gilbert mixer, the signal that gilbert mixer generates is input to voltage conversion
It is handled by digital module after the voltage signal carries out analog-to-digital conversion for current module, filters out noise and interference, and generate
Switching signal shc, shr, sdc and sac needed for balanced device.
7. the continuous-time equalizer circuit of high-speed serial communication according to claim 1, it is characterised in that:
In DC channel, the tail current of trsanscondutance amplifier is digital control by switch progress, and switching signal sdc is long number
Word signal can control multiple current sources；In alternating current path, the circuit of trsanscondutance amplifier is similar with DC channel, switch
Signal is sac, is multistation digital signal, can control multiple current sources, the high-pass filter in alternating current path, two groups of long numbers
Word switch shr and shc, respectively control resistance value and capacitance.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811358584.4A CN109379307B (en) | 2018-11-15 | 2018-11-15 | Continuous time equalizer circuit for high-speed serial communication |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811358584.4A CN109379307B (en) | 2018-11-15 | 2018-11-15 | Continuous time equalizer circuit for high-speed serial communication |
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| CN109379307A true CN109379307A (en) | 2019-02-22 |
| CN109379307B CN109379307B (en) | 2021-08-31 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116055268A (en) * | 2023-03-30 | 2023-05-02 | 苏州浪潮智能科技有限公司 | Continuous time linear equalization circuit, chip interconnection physical interface circuit and receiving end |
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| US20040175176A1 (en) * | 2001-12-20 | 2004-09-09 | Lo Victor Yeeman | System and method of space-time equalization to mitigate effects of fading and scintillation for wireless communication |
| CN101167248A (en) * | 2005-04-28 | 2008-04-23 | 英特尔公司 | Continuous-time equalizer |
| CN101729079A (en) * | 2008-10-13 | 2010-06-09 | 电子科技大学 | LINC transmitter |
| CN102780663A (en) * | 2012-07-09 | 2012-11-14 | 清华大学 | Continuous time balance circuit applied to high-speed serial interface |
| CN106301229A (en) * | 2016-08-17 | 2017-01-04 | 灿芯半导体(上海)有限公司 | Data receiver circuit |
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2018
- 2018-11-15 CN CN201811358584.4A patent/CN109379307B/en active Active
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| US20040175176A1 (en) * | 2001-12-20 | 2004-09-09 | Lo Victor Yeeman | System and method of space-time equalization to mitigate effects of fading and scintillation for wireless communication |
| CN101167248A (en) * | 2005-04-28 | 2008-04-23 | 英特尔公司 | Continuous-time equalizer |
| CN101729079A (en) * | 2008-10-13 | 2010-06-09 | 电子科技大学 | LINC transmitter |
| CN102780663A (en) * | 2012-07-09 | 2012-11-14 | 清华大学 | Continuous time balance circuit applied to high-speed serial interface |
| CN106301229A (en) * | 2016-08-17 | 2017-01-04 | 灿芯半导体(上海)有限公司 | Data receiver circuit |
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| CN116055268A (en) * | 2023-03-30 | 2023-05-02 | 苏州浪潮智能科技有限公司 | Continuous time linear equalization circuit, chip interconnection physical interface circuit and receiving end |
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| CN109379307B (en) | 2021-08-31 |
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