CN202583376U - I/O detection system of FPGA development board - Google Patents
I/O detection system of FPGA development board Download PDFInfo
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- CN202583376U CN202583376U CN 201220081971 CN201220081971U CN202583376U CN 202583376 U CN202583376 U CN 202583376U CN 201220081971 CN201220081971 CN 201220081971 CN 201220081971 U CN201220081971 U CN 201220081971U CN 202583376 U CN202583376 U CN 202583376U
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Abstract
The utility model discloses an I/O detection system of an FPGA development board. The I/O detection system comprises an I/O open circuit detection system and an I/O short circuit detection system. The I/O detection system of the FPGA development board includes an I/O unit, an input unit and an output unit, the input unit is electrically connected with the I/O unit, the output unit is electrically connected with the I/O unit, and the I/O unit includes a plurality of I/O ports. The I/O detection system of the FPGA development board connects the input unit and the output unit with the I/O unit electrically, the bidirectional port characteristic of the I/O ports of the I/O unit together with the input unit outputting a signal and the output unit receiving a signal is used to detect the I/O open circuit and short circuit, reducing the amount of work of detection, and improving the degree of accuracy of detection.
Description
Technical field
The utility model relates to the hardware failure detection technology, especially relates to a kind of FPGA development board I/O detection system.
Background technology
Along with the fast development of integrated circuit technology and manufacture level, the scale of System on Chip/SoC is increasing, integrated transistor more and more; Frequency of operation is increasingly high; Chip area is more and more littler, adopts fpga chip to carry out the special IC design, both can solve the deficiency that custom circuit lacks dirigibility; Can grasp the final function of chip again through relevant hardware environment, improve the success ratio of disposable design.
At present, FPGA is widely used in Electronic Design, because FPGA often will carry out data input and output exchange with external memory storage and CPU, can save pin resource separately exponentially and utilize the design of two-way I/O port to carry out exchanges data.
Whether traditional detection I/O port opens a way or the method for short circuit is artificially to detect by instruments such as multimeters, the time and efforts of labor not only, and cause easily and detect careless omission, be unfavorable for the mass detection of product.
Summary of the invention
The utility model is to provide a kind of to the defective that the above-mentioned background technology exists to reduce the testing amount and improve the FPGA development board I/O detection system that detects degree of accuracy.
For realizing above-mentioned purpose, the utility model discloses a kind of FPGA development board I/O detection system, said FPGA development board I/O detection system is an I/O open circuit detection system; Said I/O open circuit detection system comprises I/O unit, input block and output unit; Said input block and said I/O unit electrically connect, and said output unit and said I/O unit electrically connect, and said I/O unit comprises some I/O ports; Said input block is input as high level, and said I/O port short circuit together.
Further, said high level voltage is 3.3V.
The utility model discloses a kind of FPGA development board I/O detection system; Said FPGA development board I/O detection system is an I/O short-circuit detecting system; Said I/O short-circuit detecting system comprises I/O unit, input block and output unit, and said input block and said I/O unit electrically connect, said output unit and the electric connection of said I/O unit; Said I/O unit comprises some I/O ports; Said I/O port is a bidirectional port, and said input block comprises some input ports, and said input port electrically connects with said I/O port one end respectively; Said output unit comprises some output ports, and said output port electrically connects with the said I/O port other end respectively.
Further, said I/O port is array distribution or column distribution.
Further, in a clock period, wherein an I/O port is output I/O port, and all the other adjacent I/O ports are input I/O port.
In sum; The utility model FPGA development board I/O detection system is through electrically connecting input block and output unit respectively with the I/O unit; Utilize the bidirectional port characteristic of I/O unit I/O port; Cooperate input block output signal and output unit to receive signal and come I/O open circuit and short-circuit capability are detected, reduced the workload that detects, improved the degree of accuracy that detects simultaneously.
Description of drawings
Fig. 1 is the structural representation of the utility model example I/O open circuit detection system.
Fig. 2 is the structural representation of the utility model example I/O short-circuit detecting system.
Embodiment
For further understanding characteristic, technological means and the specific purposes that reached, the function of the utility model, the utility model is described in further detail below in conjunction with accompanying drawing and embodiment.
As depicted in figs. 1 and 2; The utility model FPGA development board I/O detection system comprises I/O open circuit detection system 100 and I/O short-circuit detecting system 200; Said I/O open circuit detection system 100 comprises I/O unit 110, input block 120 and output unit 130; Said I/O unit 110 comprises some I/O port ones 11, and said I/O port one 11 is a bidirectional port, and said I/O port one 11 is array distribution or column distribution; Said input block 120 electrically connects with said I/O unit 110, detects level in order to said I/O unit 110 to be provided; Said output unit 130 electrically connects with said I/O unit 110, in order to detect said I/O unit 110 output levels.
Said input block input 120 is 3.3V high level VCC, and said I/O port one 11 short circuits together.When the utility model was implemented, said output unit 130 testing result output low levels represented that the I/O port ones 11 of said output unit 130 correspondences are opened a way; Said output unit 130 testing results output high level signal representes that the I/O port one 11 of said output unit 130 correspondences is normal.
Said I/O short-circuit detecting system 200 comprises I/O unit 210, input block 220 and output unit 230; Said I/O unit 210 comprises some I/O ports 211; Said I/O port 211 is a bidirectional port; Said I/O port 211 is array distribution or column distribution, and said input block 220 electrically connects with said I/O unit 210, detects level in order to said I/O unit 210 to be provided; Said output unit 230 electrically connects with said I/O unit 210, in order to detect said I/O unit 210 output levels.
Said input block 220 comprises some input ports 221, and said input port 221 electrically connects with said I/O port 211 1 ends respectively; Said output unit 230 comprises some output ports 231, and said output port 231 electrically connects with said I/O port 211 other ends respectively.When the utility model was implemented, in a clock period, wherein an I/O port 211 was output I/O port; All the other adjacent I/O ports 211 are input I/O port; When output I/O port is a high level, when input I/O port also is high level, represent that two adjacent I/O ports are that short circuit connects.
In sum; The utility model FPGA development board I/O detection system is through electrically connecting input block and output unit respectively with the I/O unit; Utilize the bidirectional port characteristic of I/O unit I/O port; Cooperate input block output signal and output unit to receive signal and come I/O open circuit and short-circuit capability are detected, reduced the workload that detects, improved the degree of accuracy that detects simultaneously.
The above embodiment has only expressed a kind of embodiment of the utility model, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model scope.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the utility model design, can also make some distortion and improvement, these all belong to the protection domain of the utility model.Therefore, the protection domain of the utility model should be as the criterion with accompanying claims.
Claims (5)
1. FPGA development board I/O detection system; It is characterized in that: said FPGA development board I/O detection system is an I/O open circuit detection system (100); Said I/O open circuit detection system (100) comprises I/O unit (110), input block (120) and output unit (130); Said input block (120) electrically connects with said I/O unit (110), and said output unit (130) electrically connects with said I/O unit (110), and said I/O unit (110) comprises some I/O ports (111); Said input block (120) is input as high level (VCC), and said I/O port (111) short circuit together.
2. FPGA development board I/O detection system according to claim 1 is characterized in that: said high level (VCC) voltage is 3.3V.
3. FPGA development board I/O detection system; It is characterized in that: said FPGA development board I/O detection system is an I/O short-circuit detecting system (200); Said I/O short-circuit detecting system (200) comprises I/O unit (210), input block (220) and output unit (230); Said input block (220) electrically connects with said I/O unit (210); Said output unit (230) electrically connects with said I/O unit (210), and said I/O unit (210) comprises some I/O ports (211), and said I/O port (211) is a bidirectional port; Said input block (220) comprises some input ports (221), and said input port (221) electrically connects with said I/O port (211) one ends respectively; Said output unit (230) comprises some output ports (231), and said output port (231) electrically connects with said I/O port (211) other end respectively.
4. FPGA development board I/O detection system according to claim 3, it is characterized in that: said I/O port (211) is array distribution or column distribution.
5. FPGA development board I/O detection system according to claim 3 is characterized in that: in a clock period, wherein an I/O port (211) is output I/O port, and all the other adjacent I/O ports (211) are input I/O port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220081971 CN202583376U (en) | 2012-03-07 | 2012-03-07 | I/O detection system of FPGA development board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220081971 CN202583376U (en) | 2012-03-07 | 2012-03-07 | I/O detection system of FPGA development board |
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| Publication Number | Publication Date |
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| CN202583376U true CN202583376U (en) | 2012-12-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220081971 Expired - Fee Related CN202583376U (en) | 2012-03-07 | 2012-03-07 | I/O detection system of FPGA development board |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106443423A (en) * | 2016-08-30 | 2017-02-22 | 中国电子科技集团公司第五十八研究所 | Virtex architecture-based FPGA (programmable logic device) chip line pair fault test method |
| CN106444485A (en) * | 2016-08-31 | 2017-02-22 | 中车青岛四方机车车辆股份有限公司 | Device and method for detecting circuit |
| CN106771967A (en) * | 2016-12-07 | 2017-05-31 | 深圳市科陆物联信息技术有限公司 | Core board test device and method |
| CN110632498A (en) * | 2019-09-19 | 2019-12-31 | 西安广和通无线通信有限公司 | Test method and system |
| CN114563654A (en) * | 2022-01-19 | 2022-05-31 | 上海合宙通信科技有限公司 | GPIO test method and device |
-
2012
- 2012-03-07 CN CN 201220081971 patent/CN202583376U/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106443423A (en) * | 2016-08-30 | 2017-02-22 | 中国电子科技集团公司第五十八研究所 | Virtex architecture-based FPGA (programmable logic device) chip line pair fault test method |
| CN106443423B (en) * | 2016-08-30 | 2019-10-11 | 中国电子科技集团公司第五十八研究所 | Two times of line fault test methods of fpga chip based on Virtex framework |
| CN106444485A (en) * | 2016-08-31 | 2017-02-22 | 中车青岛四方机车车辆股份有限公司 | Device and method for detecting circuit |
| CN106444485B (en) * | 2016-08-31 | 2020-06-16 | 中车青岛四方机车车辆股份有限公司 | Apparatus for detecting line and method for detecting line |
| CN106771967A (en) * | 2016-12-07 | 2017-05-31 | 深圳市科陆物联信息技术有限公司 | Core board test device and method |
| CN110632498A (en) * | 2019-09-19 | 2019-12-31 | 西安广和通无线通信有限公司 | Test method and system |
| CN114563654A (en) * | 2022-01-19 | 2022-05-31 | 上海合宙通信科技有限公司 | GPIO test method and device |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Free format text: FORMER OWNER: DONGGUAN BOYONG TECHNOLOGY CO., LTD. Effective date: 20130328 Owner name: DONGGUAN BOYONG TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: DONGGUAN XIANGFENG ELECTRONICS TECHNOLOGY INDUSTRIAL CO., LTD. Effective date: 20130328 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: 523850 DONGGUAN, GUANGDONG PROVINCE TO: 523000 DONGGUAN, GUANGDONG PROVINCE |
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| TR01 | Transfer of patent right |
Effective date of registration: 20130328 Address after: Industrial Road, Dongguan Songshan Lake high tech Industrial Development Zone 523000 Guangdong province No. 6 Songhu Huake incubator building 611 room 2 Patentee after: Dongguan Boyong Electronic Technology Co., Ltd. Address before: 523850 Guangdong Province, Dongguan city Changan town Xiagang Zhen'an Technology Park Patentee before: Dongguan Xiangfeng Electronic Technology Industrial Co., Ltd. Patentee before: Dongguan Boyong Electronic Technology Co., Ltd. |
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| ASS | Succession or assignment of patent right |
Owner name: SHENZHEN BOYONG TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: DONGGUAN BOYONG TECHNOLOGY CO., LTD. Effective date: 20150526 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 523000 DONGGUAN, GUANGDONG PROVINCE TO: 518054 SHENZHEN, GUANGDONG PROVINCE |
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| TR01 | Transfer of patent right |
Effective date of registration: 20150526 Address after: 518054 Guangdong city of Shenzhen province Qianhai Shenzhen Hong Kong cooperation zone before Bay Road No. 1 building 201 room A (located in Shenzhen Qianhai business secretary Co. Ltd.) Patentee after: SHENZHEN BOYONG TECHNOLOGY CO., LTD. Address before: Industrial Road, Dongguan Songshan Lake high tech Industrial Development Zone 523000 Guangdong province No. 6 Songhu Huake incubator building 611 room 2 Patentee before: Dongguan Boyong Electronic Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121205 Termination date: 20170307 |