WO2021238838A1

WO2021238838A1 - Method and circuit for measuring retention time of time sequence unit

Info

Publication number: WO2021238838A1
Application number: PCT/CN2021/095441
Authority: WO
Inventors: 彭敏强; 叶升
Original assignee: 中兴通讯股份有限公司
Priority date: 2020-05-29
Filing date: 2021-05-24
Publication date: 2021-12-02
Also published as: CN113740717A

Abstract

A method and circuit for measuring the retention time of a time sequence unit. The method comprises: determining a first period value, a second period value and a third period value of a clock signal separately, wherein the first period value is a critical period of the clock signal when a time sequence unit (170) to be measured is able to correctly receive a data signal under a first test path, the second period value is a critical period of the clock signal when a delay detection module (140) is able to correctly receive the data signal under a second test path, and the third period value is a critical period of the clock signal when the delay detection module (140) is able to correctly receive the data signal under a third test path (S210); and determining the retention time of the time sequence unit according to the first period value, the second period value and the third period value (S220).

Description

Measuring method and measuring circuit of retention time of sequential unit

Technical field

This application relates to the technical field of digital integrated circuits, and in particular to a method and circuit for measuring the retention time of a sequential unit.

Background technique

The hold time of the sequential unit is one of the important factors that affect the stable transmission of signal data. When designing the timing cell library, the accurate measurement of the retention time of the timing cell directly affects the performance, production and manufacturing of the chip. Usually adopt the clock phase fine adjustment method or adopt multiple buffers as the minimum measurement scale equivalent measurement hold time. However, these methods have many shortcomings, such as limited by the adjustable range of the clock phase and the delay of the buffer, the measured clock path and data path are different, and the performance of this difference is more obvious under different test voltages. This will cause a very large measurement error in the hold time of the sequential unit.

Summary of the invention

The embodiment of the application provides a circuit for measuring the retention time of a sequential unit, which includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a first clock phase controller, a second clock phase controller, A data signal transmission module, a clock signal transmission module, a timing unit to be tested, and a control module. The clock signal generation module is respectively connected to the first selection module, the delay detection module and the control module; the delay detection module Are respectively connected to the first selection module, the second selection module, and the control module; the first selection module is respectively connected to the control module, the first clock phase controller, and the second clock phase The controller is connected; the second selection module is respectively connected to the control module, the data signal transmission module and the clock signal transmission module; the first clock phase controller is connected to the control module and the data signal respectively The signal transmission module is connected; the second clock phase controller is connected to the control module and the clock signal transmission module respectively; the data signal transmission module is connected to the timing unit to be tested and the control module respectively; The clock signal transmission module is respectively connected to the timing unit to be tested and the control module; and the timing unit to be tested is connected to the control module, and the first clock phase controller is used to output a first pulse signal and is The data signal transmission module provides a clock signal, the second clock phase controller is used to output a second pulse signal and provide a clock signal for the clock signal transmission module, and the control module is used to control the first selection module and The second selection module respectively forms a first test path, a second test path, and a third test path to determine the retention of the timing unit based on the first test path, the second test path, and the third test path Time, wherein the first test path includes the clock signal generation module, the first clock phase controller, the second clock phase controller, the data signal transmission module, the clock signal transmission module, The timing unit to be tested and the control module, and the second test path includes the clock signal generation module, the delay detection module, the first clock phase controller, the data signal transmission module, and the Control module, and the third test path includes the clock signal generation module, the delay detection module, the second clock phase controller, the clock signal transmission module, and the control module.

The embodiment of the present application also provides a method for measuring the retention time of a sequential unit. The measurement method is suitable for the circuit for measuring the retention time of a sequential unit described in the embodiment of the present application. The measurement circuit includes a clock signal generation module and a second A selection module, a second selection module, a delay detection module, a first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, a sequence unit to be tested and a control module, the control module controls The first selection module and the second selection module respectively form a first test path, a second test path, and a third test path, and the first test path includes the clock signal generation module and the first clock phase Controller, the second clock phase controller, the data signal transmission module, the clock signal transmission module, the sequence unit to be tested, and the control module, the second test path includes the clock signal generation Module, the delay detection module, the first clock phase controller, the data signal transmission module, and the control module, and the third test path includes the clock signal generation module, the delay detection module, For the second clock phase controller, the clock signal transmission module, and the control module, the method includes: respectively determining a first period value, a second period value, and a third period value of the clock signal, wherein the The first period value is the critical period of the clock signal when the timing unit under test can correctly receive the data signal under the first test path, and the second period value is the critical period of the clock signal under the second test path. The critical period of the clock signal when the delay detection module can correctly receive the data signal, and the third period value is when the delay detection module can correctly receive the data signal under the third test path The critical period of the clock signal; and determining the retention time of the sequential unit according to the first period value, the second period value, and the third period value.

Regarding the above embodiments and other aspects of the application and their implementation manners, more descriptions are provided in the description of the drawings, the specific implementation manners, and the claims.

Description of the drawings

FIG. 1 is a schematic diagram of the retention time of a sequential unit in the related art;

2 is a schematic structural diagram of a circuit for measuring the retention time of a sequential unit according to an embodiment of the present application;

FIG. 3 is a timing diagram of a holding time measurement signal of a timing unit according to an embodiment of the present application;

4 is another schematic diagram of the structure of a circuit for measuring the retention time of a sequential unit according to an embodiment of the present application;

Fig. 5 is a flowchart of a method for measuring the retention time of a sequential unit according to an embodiment of the present application;

Fig. 6 is a flowchart of a method for determining the period value of a clock signal according to an embodiment of the present application; and

Fig. 7 is a schematic diagram of measuring the period value of a clock signal according to an embodiment of the present application.

Detailed ways

Hereinafter, the embodiments of the present application will be described with reference to the accompanying drawings. In the case of no conflict, the embodiments in the application and the features in the embodiments can be combined with each other arbitrarily.

FIG. 1 is a schematic diagram of the retention time of a sequential unit in the related art.

Referring to FIG. 1, the hold time (th) of a sequential unit (such as a flip-flop) refers to the time during which the data signal needs to remain stable after the rising edge of the clock signal of the sequential unit arrives. If the hold time th is not enough, the data will not be effectively read and converted to output. The hold time th refers to the minimum stable time.

In the related technology, the retention time of the sequential unit is obtained by simulation through the spice tool when the unit library is designed, but this is only a theoretical calculation value. If the theoretical calculation value is larger than the actual value in the chip, give The back-end timing closure adds unnecessary difficulties; and if the theoretical calculation value is too small, it may cause timing problems after the chip is produced, and the chip cannot reach the actual operating frequency. Therefore, after completing the timing cell library design, keep the time It is very important to maintain consistency between the theoretical value and the actual value. In order to ensure that the actual value of the hold time is consistent with the theoretical value, it is usually necessary to measure and verify the hold time.

In a related technical solution, a method for measuring the hold time based on the fine adjustment of the clock phase is proposed. For example, through the fine adjustment of the clock phase, two accurately adjusted clocks with phase deviation are used as clocks. The data is sent to the sequence unit to be tested to identify the hold time sequence violation (hold violation) to determine the hold time of the sequence unit. However, the accuracy of this measurement is limited by the minimum step length of the clock phase adjustable, and the clock has differences in different transmission paths, and the performance of this difference is different under different test voltages, so the error of the measurement results is very large. Big.

In another related technical solution, it is proposed to use a buffer with a small delay as the minimum measurement scale, and construct buffers with different numbers of differences for the clock path and the data path of the timing unit to determine whether to maintain The time is equivalent to the number of buffers with the smallest measurement scale. The accuracy of this method is limited by the delay of the buffer as the minimum measurement scale. There are also differences between the measured clock path and the data path, and the performance of this difference will increase significantly under different voltages, thus leading to the measurement The error of the result is very large.

Generally, the measurement of the hold time of the sequential unit has nothing to do with the period or frequency of the clock signal.

In view of this, this application proposes a measuring circuit and a measuring method for the retention time of a sequential unit. First, the control module controls the first clock phase controller to output the first pulse signal and provides the clock signal for the data signal transmission module to control the second The clock phase controller outputs the second pulse signal and provides the clock signal for the clock signal transmission module, so that the measurement of the retention time of the sequential unit is correlated with the period or frequency of the clock signal; then the first selection module and the second selection are controlled by the control module The modules respectively form the first test path, the second test path and the third test path, and then respectively determine the critical period of the clock signal when the sequence unit to be tested under the first test path can correctly receive the data signal (denoted as the first period) Value), the critical period of the clock signal when the delay detection module can correctly receive the data signal under the second test path (denoted as the second period value), and the delay detection module can correctly receive the data signal under the third test path The critical period of the clock signal at time (denoted as the third period value), and finally the retention time of the sequential unit is determined according to the first period value, the second period value and the third period value. It can be seen that the first clock phase controller and the second clock phase controller make the hold time timing violation test under the first test path correlate with the cycle or frequency of the clock signal (that is, related to the first cycle value), so that Makes the determination of the retention time of the sequence unit only related to the first period value, the second period value and the third period value, and is not limited by the adjustment range of the clock phase and the delay of the buffer, and overcomes the difference in the test The problem of large measurement errors caused by the difference in voltage, thereby improving the accuracy of the measurement.

Fig. 2 is a schematic structural diagram of a circuit for measuring the retention time of a sequential unit according to an embodiment of the present application.

2, the test circuit includes a clock signal generation module 110, a first selection module 120, a second selection module 130, a delay detection module 140, a first clock phase controller 10, a second clock phase controller 20, and a data signal transmission module 150. The clock signal transmission module 160, the timing unit 170 to be tested, and the control module 180.

The clock signal generating module 110 is respectively connected with the first selection module 120, the delay detection module 140 and the control module 180. The delay detection module 140 is respectively connected with the first selection module 120, the second selection module 130 and the control module 180. The first selection module 120 is connected to the control module 180, the first clock phase controller 10, and the second clock phase controller 20, respectively. The second selection module 130 is respectively connected with the control module 180, the data signal transmission module 150 and the clock signal transmission module 160. The first clock phase controller 10 is connected to the control module 180 and the data signal transmission module 150 respectively. The second clock phase controller 20 is connected to the control module 180 and the clock signal transmission module 160 respectively. The data signal transmission module 150 is respectively connected with the sequence unit 170 to be tested and the control module 180. The clock signal transmission module 160 is respectively connected with the timing unit 170 and the control module 180 to be tested. The timing unit 170 to be tested is connected to the control module 180.

The first clock phase controller 10 is used to output a first pulse signal and provide a clock signal for the data signal transmission module 150. The second clock phase controller 20 is used to output a second pulse signal and provide a clock signal for the clock signal transmission module 160.

The control module 180 is used to control the first selection module 120 and the second selection module 130 to form a first test path, a second test path, and a third test path, respectively, so as to be based on the first test path, the second test path, and the third test path. Determine the hold time of the sequential unit. The first test path includes a clock signal generation module 110, a first clock phase controller 10, a second clock phase controller 20, a data signal transmission module 150, a clock signal transmission module 160, a timing unit 170 to be tested, and a control module 180. The second test path includes a clock signal generation module 110, a delay detection module 140, a first clock phase controller 10, a data signal transmission module 150, and a control module 180. The third test path consists of a clock signal generation module 110, a delay detection module 140, a second clock phase controller 20, a clock signal transmission module 160, and a control module 180.

FIG. 3 is a timing diagram of a holding time measurement signal of a timing unit according to an embodiment of the present application.

Referring to FIG. 3, the clock signal sent by the clock signal generation module 110 may be a pulse signal with two rising edges (as shown in the p1 curve in FIG. 3), which have rising edges at T0 and T2, respectively, and at T1 and T3, respectively. Has a falling edge. The pulse signal with two rising edges is input to the first clock phase controller 10 and the second clock phase controller 20 respectively. The signal output by the first clock phase controller 10 is the first pulse signal whose first rising edge is cut off, and only the second rising edge can pass (p2 curve in Fig. 3). The first pulse signal is at time T2 There is a rising edge; the signal output by the second clock phase controller 20 is the second rising edge that is truncated, and only the second pulse signal that can pass the first rising edge (as shown in the p3 curve in Figure 3), the second pulse The signal has a rising edge at T0. In FIG. 3, curve p4 is a timing diagram of the data signal output at the output terminal of the second sending register 151 (see FIG. 4), and curve p5 is a timing diagram of the signal output at the output terminal of the timing unit 170 under test. The first pulse signal may be a clock signal provided to the data signal transmission module 150, and the second pulse signal may be a clock signal provided to the clock signal transmission module 160.

In an embodiment, the first selection module 120 is used to control one of the clock signal generation module 110 and the delay detection module 140 to be connected to the first clock phase controller 10 and the second clock phase controller 20, respectively. The second selection module 130 is used to control one of the data signal transmission module 150 and the clock signal transmission module 160 to be connected to the delay detection module 140.

For example, when the control module 180 controls the first selection module 120 to control the clock signal generation module 110 to be connected to the first clock phase controller 10 and the second clock phase controller 20 respectively, the test circuit enters the hold of the sequence unit 170 to be tested. Time critical point test mode, that is, the formation includes a clock signal generation module 110, a first clock phase controller 10, a second clock phase controller 20, a data signal transmission module 150, a clock signal transmission module 160, and a sequence unit 170 to be tested And the first test path of the control module 180.

For example, when the control module 180 controls the first selection module 120 to control the delay detection module 140 to be connected to the first clock phase controller 10 and the second clock phase controller 20 respectively, and controls the second selection module 130 to control data signal transmission When one of the module 150 and the clock signal transmission module 160 is connected to the delay detection module 140, the test circuit enters the delay comparison mode of the clock signal transmission path and the data signal transmission path. The data signal transmission path includes the clock signal generation module 110 and the delay detection module. The second test path of the detection module 140, the first clock phase controller 10, the data signal transmission module 150, and the control module 180, and the clock signal transmission path includes the clock signal generation module 110, the delay detection module 140, and the second clock phase control The third test path of the device 20, the clock signal transmission module 160, and the control module 180.

Fig. 4 is another structural diagram of a circuit for measuring the retention time of a sequential unit according to an embodiment of the present application.

2 and 4, the clock signal generation module 110 includes a clock frequency modulation unit 111 and a clock pulse control unit 112. The clock frequency modulation unit 111 is connected to the clock pulse control unit 112, and the clock pulse control unit 112 is respectively connected to the delay detection module 140 (shown as the first sending register 141 and the receiving register 142 in FIG. 4) and the first selection module 120. The input terminal A1 is connected, and the control module 180 is connected to the clock frequency modulation unit 111 and the clock pulse control unit 112 respectively.

In the embodiment, the clock frequency modulation unit 111 may be a phase locked loop (PLL), which is used as a clock source. The clock frequency has high precision, high stability, low jitter, and can be finely adjusted. The clock pulse control unit 112 may be a clock generation circuit (on-chip-clock, OCC) for outputting a clock pulse signal.

In an embodiment, the delay detection module 140 includes a first launch register (launch register) 141 and a receiving register (capture register) 142. The first input terminal of the first sending register 141 is connected to the clock signal generating module 110, the second input terminal of the first sending register 141 is connected to the external data signal data1, and the output terminal of the first sending register 141 is connected to the first selection module 120 The second input terminal A2 is connected. The first input terminal of the receiving register 142 is connected to the clock signal generating module 110, the second input terminal of the receiving register 142 is connected to the output terminal of the second selection module 130, and the output terminal of the receiving register 142 is connected to the control module 180.

In the embodiment, the test circuit is in the second test path and the third test path, the first sending register 141 is used as the starting point of data signal transmission, and the receiving register 142 is used as the end point of data signal transmission. For example, in the second test path, the control module 180 controls the second input terminal A2 of the first selection module 120 to be turned on, that is, the output terminal of the first sending register 141 of the delay detection module 140 is controlled to phase with the first clock respectively. The controller 10 and the second clock phase controller 20 are connected, and the control module 180 also controls the second input terminal B2 of the second selection module 130 to be connected to the receiving register 142 of the delay detection module 140, that is, the clock signal generation module 110 , The second test path composed of the first sending register 141, the first clock phase controller 10, the data signal transmission module 150 (shown as the second sending register 151 in FIG. 4), the receiving register 142 and the control module 180. When testing under the second test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first sending register 141, and the external data signal data1 is input to the second input terminal of the first sending register 141. The signal data1 is output by the first sending register 141 and transmitted to the receiving register 142 via the data signal transmission module 150.

For example, in the third test path, the control module 180 controls the second input terminal A2 of the first selection module 120 to be turned on, that is, the output terminal of the first sending register 141 of the delay detection module 140 is controlled to phase with the first clock respectively. The controller 10 and the second clock phase controller 20 are connected, and the control module 180 also controls the first input B1 of the second selection module 130 to be connected to the receiving register 142 of the delay detection module 140, that is, the clock signal generation module 110 The third test path is composed of the first sending register 141, the second clock phase controller 20, the clock signal transmission module 160 (shown as the first buffer module b1 in FIG. 4), the receiving register 142 and the control module 180. When testing under the third test path, the clock signal output by the clock signal generation module 110 is input to the first input terminal of the first sending register 141, and the external data signal data1 is input to the second input terminal of the first sending register 141. The signal data1 is output by the first sending register 141, and transmitted to the receiving register 142 via the clock signal transmission module 160.

In an embodiment, the data signal transmission module 150 includes a second sending register 151. The first input terminal of the second sending register 151 is connected to the first clock phase controller 10, the second input terminal of the second sending register 151 is connected to the external data signal data1, and the output terminal of the second sending register 151 is connected to the second selection module respectively. The second input terminal B2 of 130 is connected to the second input terminal of the sequence unit 170 to be tested.

In an embodiment, the external data signal data1 input at the second input terminal of the second sending register 151 is used to provide a data signal during the first test path test. For example, in the first test path, the control module 180 controls the first input terminal A1 of the first selection module 120 to be turned on, that is, the output terminal of the signal generation module 110 is connected to the first clock phase controller 10 and the second clock phase respectively. The controller 20 is turned on to form a clock signal generation module 110, a first clock phase controller 10, a data signal transmission module 150, a second clock phase controller 20, a clock signal transmission module 160, a timing unit under test 170, and a control module The first test path composed of 180. When testing under the first test path, the first pulse signal output by the first clock phase controller 10 is input to the first input of the second sending register 151, and the first pulse signal is provided during the first test path test. As the clock signal, the external data signal data1 is input to the second input terminal of the second transmission register 151, and the external data signal data1 is output by the second transmission register 151 and then transmitted to the timing unit 170 to be tested.

In the embodiment, the reset terminal of the second sending register 151, the reset terminal of the first sending register 141, the reset terminal of the receiving register 142, and the reset terminal of the sequence unit 170 to be tested are all connected to the control module 180. The reset and clear functions of the second sending register 151, the first sending register 141, the receiving register 142, and the sequence unit 170 to be tested are controlled.

In the embodiment, the clock signal transmission module 160 includes at least one first buffer module b1, the input end of the first buffer module b1 is connected to the second clock phase controller 20, and the output end of the first buffer module b1 is connected to the second select The first input terminal B1 of the module 130 is connected to the first input terminal of the sequence unit 170 to be tested.

In the embodiment, the first buffer module b1 forms a clock signal transmission path, and the first buffer module b1 is used to adjust the delay time of the clock signal transmission module 160. It should be noted that the data signal transmission module 150 may also include a first buffer module b1, that is, a data signal transmission path may be formed by the second sending register 151 and the first buffer module b1, and the first buffer module b1 of the data signal transmission path The number of the first buffer module b1 of the clock signal transmission path can also include more than one, and the specific number can be set according to actual test requirements, which is not specifically limited in this application.

In an embodiment, when the control module 180 controls the first input terminal A1 of the first selection module 120 to be closed and the second input terminal A2 is disconnected, the first input terminal B1 and the second input terminal B2 of the second selection module 130 are both disconnected. When open, the first test path is formed; when the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 is closed, the first input terminal B1 of the second selection module 130 is opened and the first input terminal A2 is closed. When the second input terminal B2 is closed, a second test path is formed; when the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 is closed, the first input terminal B1 of the second selection module 130 When closed and the second input terminal B2 is open, a third test path is formed.

In an embodiment, when the control module 180 controls the first input terminal A1 of the first selection module 120 to be closed and the second input terminal A2 is opened, the first input terminal B1 and the second input terminal B2 of the second selection module 130 are both disconnected. When turned on, the delay detection module 140 is disconnected from the first clock phase controller 10 and the second clock phase controller 20, and the output terminal of the signal generation module 110 is connected to the first clock phase controller 10 and the second clock phase controller 10 and the second clock phase controller respectively. The controller 20 is turned on to form a clock signal generation module 110, a first clock phase controller 10, a data signal transmission module 150 (including a data signal transmission path formed by the second sending register 151), and a second clock phase controller 20 , The first test path composed of the clock signal transmission module 160 (including the clock signal transmission path formed by the first buffer module b1), the sequence unit 170 to be tested and the control module 180. In the first test path, the data signal transmission path has a fixed delay, and the delay value is denoted as T _data , and the clock signal transmission path also has a fixed delay, and the delay value is denoted as T _clk . When testing under the first test path, the signal generation module 110 outputs a pulse signal with two rising edges, and the pulse signal is input to the first clock phase controller 10 and the second clock phase controller 20 respectively. The first pulse signal is output through the first clock phase controller 10, and the second pulse signal is output through the second clock phase controller 20. The first pulse signal is used as the clock signal of the second sending register 151, and the first pulse signal input to the first input terminal of the second sending register 151 is shown in the p2 curve in FIG. 3. The second pulse signal is output to the first input terminal (ie, the clock terminal) of the timing unit 170 to be tested through the first buffer module b1, and the second pulse signal input to the first input terminal of the timing unit 170 to be tested is shown in the curve in Fig. 3 p3, and the signal timing output from the output terminal of the timing unit 170 to be tested is shown in curve p5 in FIG. 3. The first pulse signal is input to the first input terminal of the second sending register 151, and the external data signal data1 is input to the second input terminal of the second sending register 151 (as shown in the curve p4 in Fig. 3), and the clock signal generation module 110 The frequency of the clock signal can be adjusted. Generally, when the frequency of the clock signal is relatively slow, the external data signal data1 can be obtained by the timing unit 170 to be tested after being output by the second sending register 151, but when the frequency of the clock signal reaches a certain threshold, a hold time timing violation will occur. The timing measurement unit 170 will not be able to obtain the external data signal data1 output by the second sending register 151. The period of the clock signal (that is, the critical period) where the hold time timing violation occurs is recorded as Period_hd, and the critical period satisfies the following conditions:

T _clk -T _data =Period_hd-T _h

Among them, T _h is the retention time of the sequence unit to be tested.

In an embodiment, when the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 is closed, the first input terminal B1 of the second selection module 130 is opened and the second input terminal B2 When closed, the first sending register 141 is connected to the first clock phase controller 10, and the first clock phase controller 10 is connected to the data signal transmission module 150 (including the data signal transmission path formed by the second sending register 151) , And connect the data signal transmission module 150 with the receiving register 142, thereby forming a clock signal generating module 110, a first sending register 141, a first clock phase controller 10, a second sending register 151, a receiving register 142, and a control module The second test path composed of 180. The first clock phase controller 10 can be controlled by the control module 180 to be in a through state, that is, the signal output by the first sending register 141 is not turned off. When testing under the second test path, the clock signal output by the clock signal generating module 110 is input to the first input terminal of the first sending register 141, and the external data signal data1 is input to the second input terminal of the first sending register 141, and it passes The clock signal generating module 110 can adjust the frequency of the clock signal. Generally, when the clock signal frequency is relatively slow, the external data signal data1 can be obtained by the receiving register 142 after being output by the first sending register 141 through the first clock phase controller 10 and the second sending register 151. When the clock signal frequency is relatively fast The transmission rate of the data signal can be increased, but when the frequency of the clock signal is too fast, the receiving register 142 will not be able to obtain the external data signal data1 output by the first sending register 141. The period (ie, critical period) of the clock signal when the frequency of the clock signal reaches a certain value so that the receiving register 142 can just obtain the external data signal data1 is recorded as Period_data.

In an embodiment, when the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 is closed, the first input terminal B1 of the second selection module 130 is closed and the second input terminal B2 is closed. When on, the first sending register 141 is connected to the second clock phase controller 20, and the second clock phase controller 20 is connected to the clock signal transmission module 160 (including the clock signal transmission path formed by the first buffer module b1) , And the clock signal transmission module 160 is connected to the receiving register 142, thereby forming the clock signal generating module 110, the first sending register 141, the second clock phase controller 20, the first buffer module b1, the receiving register 142 and the control module The third test path composed of 180. The second clock phase controller 20 may be controlled by the control module 180 to be in a through state, that is, the signal output by the first sending register 141 is not turned off. When testing under the third test path, the clock signal output by the clock signal generating module 110 is input to the first input end of the first sending register 141, and the external data signal data1 is input to the second input end of the first sending register 141, and it passes The clock signal generation module 110 can adjust the frequency of the clock signal. Generally, when the clock signal frequency is relatively slow, the external data signal data1 can be obtained by the receiving register 142 after being output by the first sending register 141 through the second clock phase controller 20 and the first buffer module b1. When the clock signal frequency is relatively fast The transmission rate of the data signal can be increased, but when the frequency of the clock signal is too fast, the receiving register 142 will not be able to obtain the external data signal data1 output by the first sending register 141. The period (ie, critical period) of the clock signal when the frequency of the clock signal reaches a certain value so that the receiving register 142 can just obtain the external data signal data1 is recorded as Period_clk.

The critical period Period_data under the second test path and Period_clk under the third test path meet the following conditions:

T _data -T _clk =Period_data-Period_clk

Combining the critical period of the clock signal with the hold time timing violation occurring under the first test path as the condition satisfied by Period_hd, we can get:

T _h =Period_hd-Period_clk+Period_data

It can be seen that the retention time _{Th of the} sequence unit is only the same as the critical period of the clock signal when the sequence unit 170 to be tested under the first test path can correctly obtain the external data signal data1, which is recorded as Period_hd, and the delay detection module under the second test path 140 can just obtain the critical period Period_data of the clock signal when the external data signal data1 and the third test path delay detection module 140 can just obtain the critical period Period_clk of the clock signal when the external data signal data1 is related, and are related to the data signal transmission path and The difference in the clock signal transmission path, the delay of the buffer, and the test voltage are irrelevant, which can solve the measurement result error caused by the difference between the data signal transmission path and the clock signal transmission path, the delay of the buffer, and the difference in the test voltage. This is a major problem, so that the measurement accuracy of the retention time of the sequence unit 170 to be tested can be improved.

Fig. 5 is a flowchart of a method for measuring the retention time of a sequential unit according to an embodiment of the present application. The method for measuring the retention time of a sequential unit of the present application is applicable to a circuit for measuring the retention time of a sequential unit according to any embodiment of the present application. The measurement circuit includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, a first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, and a timing sequence to be measured Unit and control module. The control module controls the first selection module and the second selection module to form a first test path, a second test path, and a third test path, respectively. The first test path includes a clock signal generation module, a first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, a sequence unit to be tested, and a control module. The second test path includes a clock signal generation module, a delay detection module, a first clock phase controller, a data signal transmission module, and a control module. The third test path includes a clock signal generation module, a delay detection module, a second clock phase controller, a clock signal transmission module, and a control module.

Referring to FIG. 5, the method for measuring the retention time of a sequential unit according to an embodiment of the present application includes the following steps S210 to S220.

In step S210, the first period value, the second period value and the third period value of the clock signal are respectively determined, where the first period value is the clock when the sequence unit to be tested under the first test path can correctly receive the data signal The critical period of the signal, the second period value is the critical period of the clock signal when the delay detection module can correctly receive the data signal under the second test path, and the third period value is the delay detection module can be correct under the third test path The critical period of the clock signal when the data signal is received.

In step S220, the retention time of the sequential unit is determined according to the first period value, the second period value, and the third period value.

In an embodiment, the retention time of the sequential unit is equal to the sum of the first period value and the second period value minus the difference of the third period value, that is, the retention time of the sequential unit = the first period value + the second period value- The third period value.

In an embodiment, the period or frequency of the clock signal output by the clock signal generation module 110 may be controlled by the control module 180 to adjust the frequency of the clock signal under the first test path, the second test path, and the third test path.

In an embodiment, the pulse number and phase of the clock signal output by the clock signal generation module 110 can be controlled by the first clock phase controller 10 to output the first pulse signal, and the clock signal can be controlled by the second clock phase controller 20 Generate the pulse number and phase of the clock signal output by the module 110 to output the second pulse signal, so that the retention of the sequence unit 170 under test can be tested by changing the period of the clock signal output by the clock signal generation module 110 in the first test path Time sequence violation.

In an embodiment, under the first test path, when the timing unit 170 to be tested has a timing violation of the retention time, that is, the timing unit 170 to be tested can just obtain the external output output by the second sending register 151 of the data signal transmission module 150. When the data signal is data1, the measured period value of the clock signal is the first period value Period_hd; in the second test path, the receiving register 142 can just get the first sending register 141 of the delay detection module 140 through the data signal transmission module When the external data signal data1 is output by 150, the measured period value of the clock signal is the second period value Period_data; in the third test path, the receiving register 142 can just obtain the first sending register 141 of the delay detection module 140. When the clock signal transmission module 160 outputs the external data signal data1, the measured period value of the clock signal is the third period value Period_clk. The first period value, the second period value, the third period value, and the retention time of the sequence unit 170 to be tested satisfy the following relationship:

T _h =Period_hd-Period_clk+Period_data

_{Thus, the retention time Th of} the sequence unit to be tested can be determined.

Fig. 6 is a flowchart of a method for determining the period value of a clock signal according to an embodiment of the present application.

According to the method shown in Figure 6, the period value of the clock signal can be determined. The period value can be any one of the first period value, the second period value, and the third period value. As shown in FIG. 6, the method for determining the period value of the clock signal includes the following steps S310 to S350.

S310: Determine the estimated range and period step length of the critical period of the clock signal.

In an embodiment, the method for determining the estimated range of the critical period of the clock signal may include: firstly, the expected value of the critical period of the clock signal can be obtained by theoretical calculation (for example, it can be obtained by simulation by a spice tool); then, determining the period step The cycle step length can be a variable step length; finally, the test is carried out in sequence from small to large according to the cycle step, until the test value of the critical period of the clock signal appears for the first time is inconsistent with the expected value of the critical period. The difference between the period value of the clock signal and the period step length is used as the left interval value of the estimated range of the critical period, denoted as P_min, and the sum of the period value of the clock signal and the period step length at this time is used as the estimation of the critical period The right interval value of the range is denoted as P_max. From this, the critical period range F of the clock signal can be determined, denoted as <P_min, P_max>.

In an embodiment, the period step size may be a fixed period step size s, for example, the period step size s may be 1 ps, 5 ps, 10 ps, and so on. In addition, the smaller the cycle step, the higher the accuracy of the adjustment, and the better the effect of reducing the influence of clock jitter.

In step S320, the estimated range of the critical period is divided into N parts according to the period step length to obtain N+1 test period values.

In the embodiment, for example, the critical period range F can be divided into N parts according to the period step s, and the two interval end values of the critical period range F are added to obtain a total of N+1 test period values, namely, P_max, P_min+ (N-1)*s, P_min+(N-2)*s,...P_min+4*s, P_min+3*s, P_min+2*s, P_min+1*s, and P_min (see Figure 7).

In step S330, N+1 test period values are tested to obtain N+1 test results.

In step S340, M test period values out of N+1 test period values are obtained, and the test result for the M test period values is that the sequence unit or delay detection module to be tested can correctly obtain the data signal, and M is less than or equal to N+1.

In step S350, the period value of the clock signal is determined according to the M test period values.

Referring to FIG. 7, according to the theory of timing analysis, it can be estimated that, in the first test path, when the period of the clock signal is less than a certain value (for example, P_min), if the output of the timing unit 170 under test in the test circuit is The result must be able to sample the hold time timing violation, then the period range less than P_min can be called the estimated stable timing violation area, as shown in the I area in Figure 7; when the period of the clock signal is greater than a certain value (for example, P_max ), if the normal output result can be stably sampled on the sequence unit 170 to be tested in the test circuit, the period area larger than P_max can be called the estimated stable and no timing violation area, as shown in Figure 7 II Area. In the same way, under the second test path and the third test path, there are also areas where timing violations are predicted to occur and areas where timing violations are not predicted to occur.

In the embodiment, firstly, N+1 test period values are tested respectively, and N+1 test results are obtained and recorded. These N+1 test results can include timing violation jumps and non-timing violation jumps that occur with the hold time, and when the test period is less than a certain value, the measurement result shows that timing violations continue to occur; or when the test period is greater than a certain value When the time, the measurement result shows that there is no timing violation continuously. For example, the timing violation transition points k1 and k2, and the non-timing violation transition points k3 and k4 shown in FIG. 7 may appear, and the timing violation continues to occur when the test period is less than P_min+2*s corresponding to point k1; When the test period is greater than P_min+(N-2)*s corresponding to point k4, no timing violation will continue. The period range smaller than P_min+2*s corresponding to point k1 can be called the estimated stable occurrence timing violation area I area, and the period range larger than P_min+(N-2)*s corresponding to point k4 can be called estimated Stable and no timing violation area II. Assuming that there are M timing violation transition points in N+1 test results (for example, the timing violation transition points k1 and k2 shown in Figure 7), use the following formula to calculate:

Among them, Period_avg is the period value of the clock signal, M is less than or equal to N+1, and Period_trigger_i is the test period value corresponding to the i-th timing violation transition point.

The above are only exemplary embodiments of the present application, and are not used to limit the protection scope of the present application. Generally speaking, the various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although the application is not limited thereto.

By way of exemplary and non-limiting examples, a detailed description of the exemplary embodiments of the present application has been provided above. However, considering the accompanying drawings and claims, various modifications and adjustments to the above embodiments are obvious to those skilled in the art, but they do not deviate from the scope of the present disclosure. Therefore, the proper scope of the present disclosure will be determined according to the claims.

Claims

A method for measuring the retention time of a sequential unit, the measurement method is suitable for a circuit for measuring the retention time of a sequential unit, the measurement circuit includes a clock signal generation module, a first selection module, a second selection module, a delay detection module, A first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, a timing unit to be tested, and a control module, the control module controls the first selection module and the second selection module A first test path, a second test path, and a third test path are formed respectively. The first test path includes the clock signal generation module, the first clock phase controller, the second clock phase controller, and the The data signal transmission module, the clock signal transmission module, the timing unit to be tested, and the control module, and the second test path includes the clock signal generation module, the delay detection module, and the first clock A phase controller, the data signal transmission module, and the control module, and the third test path includes the clock signal generation module, the delay detection module, the second clock phase controller, and the clock signal A transmission module and the control module;

The method includes:

The first period value, the second period value, and the third period value of the clock signal are respectively determined, where the first period value is when the sequence unit under test can correctly receive the data signal under the first test path The critical period of the clock signal, the second period value is the critical period of the clock signal when the delay detection module can correctly receive the data signal under the second test path, and the third The period value is the critical period of the clock signal when the delay detection module can correctly receive the data signal under the third test path; and

The retention time of the sequential unit is determined according to the first period value, the second period value, and the third period value.
The method for measuring the retention time of a sequential unit according to claim 1, wherein the retention time of the sequential unit is equal to the sum of the first period value and the second period value minus the third period value Difference.
The method for measuring the retention time of a sequential unit according to claim 1, wherein the value of any one of the first period value, the second period value, and the third period value of the clock signal is determined The steps include:

Determining the estimated range and period step length of the critical period of the clock signal;

Dividing the estimated range of the critical period into N parts according to the period step length to obtain N+1 test period values;

Testing the N+1 test period values to obtain N+1 test results;

Obtain M test period values among the N+1 test period values, and the test result for the M test period values is that the sequence unit to be tested or the delay detection module can correctly obtain the data signal, where: M is less than or equal to N+1; and

According to the M test period values, the period value of the clock signal is determined.
The method for measuring the retention time of a sequential unit according to claim 3, wherein the period step is a fixed period step.
A circuit for measuring the retention time of a sequential unit, including a clock signal generation module, a first selection module, a second selection module, a delay detection module, a first clock phase controller, a second clock phase controller, a data signal transmission module, Clock signal transmission module, sequence unit to be tested and control module,

Wherein, the clock signal generation module is respectively connected to the first selection module, the delay detection module and the control module; the delay detection module is respectively connected to the first selection module, the second selection module and The control module is connected; the first selection module is respectively connected to the control module, the first clock phase controller, and the second clock phase controller; the second selection module is connected to the control module respectively The data signal transmission module is connected to the clock signal transmission module; the first clock phase controller is connected to the control module and the data signal transmission module respectively; the second clock phase controller is connected to the The control module is connected to the clock signal transmission module; the data signal transmission module is connected to the timing unit to be tested and the control module, respectively; the clock signal transmission module is connected to the timing unit to be tested and the control module, respectively The control module is connected; and the sequence unit to be tested is connected to the control module;

The first clock phase controller is used to output a first pulse signal and provide a clock signal for the data signal transmission module, and the second clock phase controller is used to output a second pulse signal and provide a clock for the clock signal transmission module Signal,

The control module is configured to control the first selection module and the second selection module to form a first test path, a second test path, and a third test path, respectively, so as to be based on the first test path and the second test path. The test path and the third test path determine the retention time of the timing unit, wherein the first test path includes the clock signal generation module, the first clock phase controller, the second clock phase controller, The data signal transmission module, the clock signal transmission module, the timing unit to be tested, and the control module, and the second test path includes the clock signal generation module, the delay detection module, and the first The clock phase controller, the data signal transmission module, and the control module, and the third test path includes the clock signal generation module, the delay detection module, the second clock phase controller, and the clock The signal transmission module and the control module.
The circuit for measuring the retention time of a sequential unit according to claim 5, wherein the clock signal generation module includes a clock frequency modulation unit and a clock pulse control unit, the clock frequency modulation unit is connected to the clock pulse control unit, and the The clock pulse control unit is respectively connected to the first input end of the delay detection module and the first selection module, and the control module is respectively connected to the clock frequency modulation unit and the clock pulse control unit.
The circuit for measuring the retention time of a timing unit according to claim 5, wherein the delay detection module includes a first sending register and a receiving register, and the first input terminal of the first sending register and the clock signal generating module Connected, the second input terminal of the first sending register is connected to an external data signal, and the output terminal of the first sending register is connected to the second input terminal of the first selection module,

The first input terminal of the receiving register is connected to the clock signal generating module, the second input terminal of the receiving register is connected to the output terminal of the second selection module, and the output terminal of the receiving register is connected to the Control module connection.
The circuit for measuring the retention time of a sequential unit according to claim 5, wherein the data signal transmission module includes a second sending register, and the first input terminal of the second sending register is connected to the first clock phase controller Connected, the second input terminal of the second sending register is connected to an external data signal, and the output terminal of the second sending register is respectively connected to the second input terminal of the second selection module and the second input terminal of the sequence unit to be tested Two input terminals are connected.
The circuit for measuring the retention time of a sequential unit according to claim 5, wherein the clock signal transmission module includes at least one first buffer module, and an input terminal of the first buffer module is connected to the second clock phase controller Connected, and the output terminal of the first buffer module is respectively connected with the first input terminal of the second selection module and the first input terminal of the sequence unit to be tested.
The circuit for measuring the retention time of the sequential unit according to claim 5, wherein:

In response to the control module controlling the first input terminal of the first selection module to be closed and the second input terminal to be disconnected, the first input terminal and the second input terminal of the second selection module are both disconnected, forming the The first test path;

In response to the control module controlling the first input terminal of the first selection module to be opened and the second input terminal closed, the first input terminal of the second selection module is opened and the second input terminal is closed, forming the The second test path;

In response to the control module controlling the first input terminal of the first selection module to open and the second input terminal to close, the first input terminal of the second selection module to close and the second input terminal to open, the formation of the The third test path.