CN114167264B - Device for detecting digital circuit hold time violations in nuclear radiation environment - Google Patents
Device for detecting digital circuit hold time violations in nuclear radiation environment Download PDFInfo
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- CN114167264B CN114167264B CN202111470529.6A CN202111470529A CN114167264B CN 114167264 B CN114167264 B CN 114167264B CN 202111470529 A CN202111470529 A CN 202111470529A CN 114167264 B CN114167264 B CN 114167264B
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- 230000005855 radiation Effects 0.000 title claims abstract description 34
- 238000001514 detection method Methods 0.000 claims abstract description 81
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- 230000008859 change Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000014759 maintenance of location Effects 0.000 description 5
- 230000035945 sensitivity Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 240000006108 Allium ampeloprasum Species 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
- Y02E30/30—Nuclear fission reactors
Abstract
The invention discloses a device for detecting the hold time violation of a digital circuit in a nuclear radiation environment, which comprises more than two detection circuit modules connected in sequence, wherein each detection circuit module comprises a trigger unit, a buffer unit and a multiplexer unit, each buffer unit comprises a plurality of buffer branches with different stages, each multiplexer unit is respectively connected with each buffer branch, a control end of each multiplexer unit inputs a selection signal to control and select different buffer branches, a clock signal input end of each trigger unit is connected with an input end of each buffer unit for accessing a clock signal, an output end of the last trigger unit is connected with an input end of the next trigger unit, and an output end of the last trigger unit outputs a final detection result. The invention can detect whether the holding time violations occur in the digital circuit working in the nuclear radiation environment, and has the advantages of simple and compact structure, low cost, high detection efficiency and precision, and the like.
Description
Technical Field
The invention relates to the technical field of circuit detection in a nuclear radiation environment, in particular to a device for detecting digital circuit retention time violations in the nuclear radiation environment.
Background
Digital circuits capable of working normally in nuclear radiation environments are required in the fields of strong radiation planetary detection such as a wooden star, nuclear leakage accident handling, electronic monitoring of large-scale hadron collimators and nuclear fusion devices, and the like. The nuclear radiation environment can influence the normal operation of the electronic components, so that the research of the high-dose radiation resistant electronic components is of great significance in dealing with nuclear crisis such as nuclear leakage.
The problem of timing violations of digital circuits in nuclear radiation environments is a great difficulty in developing radiation-resistant electronic components. Currently, most large-scale digital integrated circuits such as a Central Processing Unit (CPU) and a Digital Signal Processor (DSP) are synchronous circuits, and as shown in fig. 1, the synchronous circuits include flip-flops (UFF 0 and UFF 1), combinational logic (Combinational logic) and a clock tree, wherein the setup time requirement can be described by formula (1), and the hold time requirement can be described by formula (2):
T lauch +T ck2q +T dp <T capture +T cycle -T setup (1)
T lauch +T ck2q +T dp >T capture +T hold (2)
wherein T is launch Is the delay of the transmitting clock, T ck2q Is the delay from the clock end (CK) to the output end (Q) of the transmitting trigger, T dp Is the delay of the combinational logic, T capture Is the delay of the capture clock, T cycle Is clock period, T setup Is the setup time of capture flip-flop (T) hold Is the hold time of the capture trigger.
If the formula (2) is satisfied, the holding time constraint is satisfied, the circuit can work normally, and if the formula (2) is not satisfied, the holding time is violated, and the working state of the circuit is abnormal. The synchronous circuit works under the drive of the clock, and is required to meet the establishment time sequence constraint and the maintenance time sequence constraint, otherwise, the circuit has functional failure. The setup time timing constraint requires that the data transmitted by the transmit flip-flop (launch flip-flop) be stable to setup after a delay of a period of combinational logic (combinational logic) until the capture clock (one clock cycle later than the transmit clock) reaches the capture flip-flop, whichThe sample can be correctly sampled by the capture clock; otherwise the capture clock will not sample the correct data and a functional error will occur. As can be seen from the set-up time requirement expression of equation (1), the radiation causes a delay change in the circuit, resulting in a set-up time violation. For example, if the cumulative radiation increases by T dp So that the left side of the formula (1) is larger than the right side, the setup time is violated, and finally a functional error is caused to occur, and the functional error can be caused to occur by increasing T cycle Is solved by means of (i.e. frequency down) the (i.e. frequency down) conversion.
The hold time timing constraint requires that the data transmitted by the transmit flip-flop (launch flip-flop) remain stable for a period of time after the same beat of clock reaches the capture flip-flop after a delay of a period of combinational logic (combinational logic), as described by the hold time requirement of equation (2). I.e. radiation may cause delay changes in the circuit, resulting in hold time violations. For example, cumulative radiation increases T capture Making equation (2) larger to the right than to the left, in which case a hold time violation occurs and eventually results in a functional error in the circuit. However, since the hold time timing constraint is independent of the clock period, the hold time violation cannot be resolved by means of frequency reduction, so that the hazard of the hold time violation is larger than that of the setup time violation, and among the numerous reliability problems caused by radiation, the hold time violation is hard error and is not recoverable by power-off restarting, so that the detection of the hold time violation is a current problem to be solved urgently.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides the device for detecting the hold time violation of the digital circuit in the nuclear radiation environment, which has the advantages of simple and compact structure, low cost and high detection efficiency and precision, and can detect whether the hold time violation occurs in the digital circuit working in the nuclear radiation environment.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
the device for detecting the digital circuit hold time violation in the nuclear radiation environment is characterized by comprising more than two detection circuit modules which are sequentially connected, wherein each detection circuit module comprises a trigger unit, a buffer unit and a multiplexer unit, each buffer unit comprises a plurality of buffer branches with different stages, each multiplexer unit is respectively connected with each buffer branch, a control end of each multiplexer unit inputs a selection signal S to control and select the buffer branch, a clock signal input end of each trigger unit is connected with an input end of each buffer unit for accessing a clock signal CLK, an output end of each trigger unit in the last detection circuit module is connected with an input end of each trigger unit in the next detection circuit module, and a final detection result is output by an output end of each trigger unit in the last detection circuit module.
Further, by adjusting the selection signal S input by each of the multiplexer units, different buffer branches are controlled to be selected, so as to control and change the delay of the path between the clock signal CLK and the output clock signal CLKOUT which are accessed by the buffer units.
Further, whether the holding time violation occurs is judged according to the waveform state of the final detection result.
Further, an inverter is further arranged at the output end of the trigger unit.
Further, the SET end of the trigger unit in each detection circuit module is connected to access to a unified SET signal SET.
Further, the output end of the trigger unit in the last detection circuit module is also connected to the input end of the trigger unit in the first detection circuit module.
Further, the number of the detection circuit modules is an even number.
Further, the trigger unit is a D-trigger.
Compared with the prior art, the invention has the advantages that: according to the invention, the retention time timing constraint margin is controlled by changing the delay of the capture clock, so that the sensitivity of the detection circuit module to retention time violations in a nuclear radiation environment is controlled, and the trigger unit can normally latch data under the condition that the retention time timing constraint is met; when the holding time is violated, the trigger unit can not latch data normally, so that whether the holding time is violated or not is judged according to the output final detection result, and the detection of the holding time violation in the nuclear radiation environment is realized.
Drawings
Fig. 1 is a schematic diagram of a typical digital circuit.
Fig. 2 is a schematic diagram of the structure of an apparatus for detecting a digital circuit hold time violation in the nuclear radiation environment in this embodiment.
Fig. 3 is a schematic diagram of the structure of the detection circuit module in this embodiment.
Fig. 4 is a schematic diagram of the result of detecting that no hold time violation has occurred in the circuit in a specific application embodiment.
Fig. 5 is a schematic diagram of the result of detecting a hold time violation in a circuit in a specific application embodiment.
Legend description: 1. a detection circuit module; 11. a trigger unit; 12. a buffer unit; 13. a multiplexer unit; 14. an inverter.
Detailed Description
The invention is further described below in connection with the drawings and the specific preferred embodiments, but the scope of protection of the invention is not limited thereby.
As shown in fig. 1, the device for detecting a digital circuit hold time violation in the nuclear radiation environment of this embodiment includes two or more detection circuit modules 1 sequentially connected, the detection circuit modules 1 include a trigger unit 11, a buffer unit 12, and a multiplexer unit 13, the buffer unit 12 includes a plurality of buffer branches of different stages, the multiplexer unit 13 is respectively connected to each buffer branch, a control terminal of the multiplexer unit 13 inputs a selection signal S to control the selection buffer branch, a clock signal input terminal of the trigger unit 11 is connected to an input terminal of the buffer unit 12 for accessing a clock signal CLK, an output terminal of the trigger unit 11 in the previous detection circuit module 1 is connected to an input terminal of the trigger unit 11 in the next detection circuit module 1, and an output terminal of the trigger unit 11 in the last detection circuit module 1 outputs a final detection result.
In the embodiment, the delay of the capturing clock, namely, the tcaply in the formula (2), is changed, so that the hold time timing constraint margin is controlled, and the sensitivity of the detection circuit module 1 to hold time violations in the nuclear radiation environment is further controlled, so that the trigger unit 11 can normally latch data under the condition that the hold time timing constraint is satisfied; when the holding time is violated, the trigger unit 11 can not latch data normally, so that whether the holding time is violated or not is judged according to the output final detection result, and the detection of the holding time violation in the nuclear radiation environment can be accurately and efficiently realized.
The embodiment can specifically judge whether the holding time violation occurs according to the waveform state of the final detection result, namely if the signal duty ratio of the final detection result is matched with the preset value, judging that the holding time violation does not occur, and if the signal duty ratio of the final detection result is not matched with the preset value, judging that the holding time violation occurs.
In this embodiment, by adjusting the selection signal S input from each multiplexer unit 13, different buffer branches are controlled and selected to control the delay of changing the path between the clock signal CLK and the output clock signal CLKOUT which are input from the buffer unit 2. Each buffer branch is corresponding to buffers with different stages, and then the buffers with different stages can be controlled and selected by the selection signal S, so that the delay of the paths from CLK to CLKOUT is controlled and changed.
In this embodiment, the output end of the trigger unit 11 is further provided with an inverter 14, and the trigger unit 11 in the previous detection circuit module 1 is connected to the input end of the trigger unit 11 in the next detection circuit module 1 through the inverter 14, so that the output signal of the trigger unit 11 in the previous detection circuit module 1 is output to the trigger unit 11 in the next detection circuit module 1 after being inverted.
In this embodiment, the SET terminal of the trigger unit 11 in each detection circuit module 1 is connected to access a unified SET signal SET, and the trigger unit 11 in each detection circuit module 1 can be controlled to SET by inputting the SET signal SET.
In this embodiment, the output terminal of the flip-flop cell 11 in the last detection circuit module 1 is also connected to the input terminal of the flip-flop cell 11 in the first detection circuit module 1. The flip-flop cell 11 in the particular last detection circuit module 1 is connected in feedback to the input of the flip-flop cell 11 in the first flip-flop cell 11 via an inverter 14. The first and last determination is specifically determined according to the connection sequence, the first trigger unit 11 connected to the input end of the input signal is the first one, and the detection circuit module 1 at the output end is the last one.
In this embodiment, the number of the detection circuit modules 1 is an even number, that is, 2N, where N is greater than or equal to 1, and specific data may be configured according to actual needs.
In this embodiment, the trigger unit 11 is specifically a D-type trigger, and of course, other types of triggers can be adopted according to actual requirements.
In a specific application embodiment, to implement the detection device described above:
firstly, a retention time violation detection circuit basic module is formed by using 1 trigger, 1 inverter, 1 multiplexer and a plurality of buffers according to the connection mode of fig. 3, wherein the inputs are SET, D, CLK and S, and the outputs are QN and CLKOUT; the input of the multiplexer is the signal output by CLK after passing through buffers of different stages, and the output is CLKOUT; by controlling the select signal S of the multiplexer, the delay of CLK to CLKOUT path may be changed.
And then, the even number of basic modules of the hold time violation detection circuits are connected in series, namely, the output signal QN of the basic module of the first hold time violation detection circuit is connected with the input signal D of the basic module of the second hold time violation detection circuit, the output signal CLKOUT of the basic module of the first hold time violation detection circuit is connected with the input signal CLK of the basic module of the second hold time violation detection circuit, the SET input signals SET of the basic modules of all the hold time violation detection circuits are short-circuited, and the multiplexer selection signals S of all the hold time violation detection circuits are short-circuited to form the structure shown in figure 2.
The output of the last hold time violation detection circuit basic block (i.e., #2N in fig. 2) is then connected to the input of the first hold time violation detection circuit basic block (i.e., #1 in fig. 2). The digital circuit holding time violation detection device in the nuclear radiation environment of the embodiment is formed, the input of the whole holding time violation detection device is SET, CLK and S, the output is OUT, wherein the SET is a SET signal, the CLK is an input clock signal, the S is a multiplexer selection signal, the OUT is an output signal, and whether the holding time violation occurs can be judged by observing the waveform of the OUT signal.
The circuit operation state transition table of the detection device formed by the above construction in the case where the hold time timing constraint is satisfied is shown in the following table 1, where D1 represents the trigger input signal D in the first hold time violation detection circuit and Q2 represents the trigger output signal Q in the second hold time violation detection circuit.
Table 1: a circuit operating state transition table.
| D 1 | Q 1 | D 2 | Q 2 | … | D 2N | Q 2N | OUT | ||
| After setting | 0 | 1 | 0 | 1 | … | 0 | 1 | 0 | |
| First racket | 1 | 0 | 1 | 0 | … | 1 | 0 | 1 | |
| Second racket | 0 | 1 | 0 | 1 | … | 0 | 1 | 0 | |
| Third racket | 1 | 0 | 1 | 0 | … | 1 | 0 | 1 | |
| … |
As shown in fig. 2 and the table above, after the SET signal SETs the hold time violation detection circuit, the flip-flop output states from front to back are sequentially inverted; if the hold time constraint in the detection circuit is satisfied, the signal of each flip-flop can be normally latched under clock driving, and after the clock CLK with the duty ratio of 50% is input, the output signal OUT of the hold time violation detection circuit presents an oscillation state of 0101, the frequency of the OUT signal is 1/2 of the clock CLK, and the duty ratio of the OUT signal is 50%, as shown in fig. 4. If the hold time in the detection circuit is violated, a metastable state phenomenon occurs, the signal of the flip-flop cannot be normally latched, the output waveform is distorted, and after a clock CLK with a duty ratio of 50% is input, the duty ratio of the OUT signal is no longer 50%, as shown in fig. 5, so that whether the hold time violation occurs can be judged. The invention controls the sensitivity of the detection circuit to the hold time violations under the nuclear radiation environment by changing the delay of the capture clock and controlling the hold time timing constraint margin, so that the trigger can normally latch data under the condition that the hold time timing constraint is satisfied, and the trigger can not normally latch data when the hold time violations, thereby accurately and efficiently realizing the detection of the hold time violations under the nuclear radiation environment.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. While the invention has been described with reference to preferred embodiments, it is not intended to be limiting. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention shall fall within the scope of the technical solution of the present invention.
Claims (5)
1. The device for detecting the digital circuit hold time violations in the nuclear radiation environment is characterized by comprising more than two detection circuit modules (1) which are sequentially connected, wherein each detection circuit module (1) comprises a trigger unit (11), a buffer unit (12) and a multiplexer unit (13), the output end of each trigger unit (11) is further provided with an inverter (14), each buffer unit (12) comprises a plurality of buffer branches with different levels, each multiplexer unit (13) is respectively connected with each buffer branch, the control end of each multiplexer unit (13) inputs a selection signal S to control and select the corresponding buffer branch, the clock signal input end of each trigger unit (11) is connected with the input end of each buffer unit (12) for accessing a clock signal CLK, the output end of each trigger unit (11) in the last detection circuit module (1) is connected with the input end of each trigger unit (11) in the next detection circuit module (1), and the final result of the detection circuit module (11) is output; and adjusting the selection signals S input by the multipath selector units (13), controlling and selecting different buffer branches to control and change the delay of paths between the clock signals CLK accessed by the buffer units and the output clock signals, judging whether the holding time violations occur according to the waveform state of the final detection result, judging that the holding time violations do not occur if the signal duty ratio of the final detection result is matched with a preset value, and judging that the holding time violations occur if the signal duty ratio of the final detection result is not matched with the preset value.
2. Device for detecting digital circuit hold time violations in the nuclear radiation environment according to claim 1, characterized in that the SET terminal of the flip-flop cell (11) in each detection circuit module (1) is connected to access a unified SET signal SET.
3. Device for detecting a digital circuit hold time violation in a nuclear radiation environment according to claim 1, characterized in that the output of the flip-flop cell (11) in the last of the detection circuit modules (1) is also connected to the input of the flip-flop cell (11) in the first of the detection circuit modules (1).
4. A device for detecting digital circuit hold time violations in a nuclear radiation environment according to any of claims 1-3, characterized in that the number of detection circuit modules (1) is an even number.
5. The apparatus for detecting digital circuit hold time violations in a nuclear radiation environment according to claim 1, characterized in that the flip-flop cell (11) is a D flip-flop.
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