CN105787213A - Repairing method of retention time violation - Google Patents
Repairing method of retention time violation Download PDFInfo
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- CN105787213A CN105787213A CN201610200745.1A CN201610200745A CN105787213A CN 105787213 A CN105787213 A CN 105787213A CN 201610200745 A CN201610200745 A CN 201610200745A CN 105787213 A CN105787213 A CN 105787213A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention relates to a repairing method of retention time violation.The method includes: acquiring the starting point, ending point and violation value of a path with the retention time violation from the result of static time sequence analysis; secondly, selecting the ending point of the path with the retention time violation as the to-be-inserted node of a repairing unit, and inserting one buffer unit or delay unit at the to-be-inserted node during each repairing so as to reduce the influence of the repairing unit insertion on the time sequence of other paths; thirdly, search the physical position for unit placing near the node with the inserted repairing unit, releasing the space required by the repairing unit through the position of the original unit in mobile design, and setting a target function to allow the total cost of the mobile unit to be the lowest so as to achieve low disturbance to the original design; fourthly, generating corresponding repairing logic, placing units and the engineering change order of mobile unit positions; fifthly, rewiring the connection relation with the logic being modified, extracting parasitic parameters, and performing static time sequence analysis to guarantee that the retention time is repaired completely.
Description
Technical field
The present invention relates to a kind of for repairing the method that in high density physical Design, the retention time violates.
Background technology
Along with extensive and super large-scale integration continuous utilization, process constantly reduces, and prevailing technology has reached 40nm, and constantly to the technological development that smaller szie is more advanced.At present, the technique that state-of-the-art process is Intel Company studied in the world, stride into the magnitude of tens nanometers.Increasingly less process replaces the speed of existing technique to be accelerated constantly, this just requires that the engineers of physical Design constantly to shorten the production cycle, could occupy a tiny space in keen competition, relatively later in particular for China's integrated circuit industry starting, the present situation that technology is weak, country is proposed the relevant policies vigorously supporting integrated circuit industry.But constantly reduce and the improving constantly of chip integration of transistor feature size make the design of integrated circuit face unprecedented challenge, no matter it is in above relatively large-sized IC design or in the design of deep submicron integrated circuit, sequence problem is always up problem of greatest concern, no matter it is the performance from design chips or stability consideration, it is desirable that designed chip has a good timing closure effect, subsequent authentication could be passed through and produce the product of high-performance high reliability.
In the process of whole physical Design, the reparation of retention time is a highly important link during sequential is repaired, because the time of setting up can be solved by frequency reducing when repairing completely, reducing the operating frequency of chip, chip still disclosure satisfy that requirement functionally；If but the retention time violate can not repair completely, will result directly in the mistake on chip functions, whole chip just cannot normal operation, so repair the retention time be sequential reparation important step.It is to produce new retention time violation repairing and set up time violation while in the key point repairing the violation of foundation/retention time, repair the retention time violate while will not produce new to set up time violation, this just requires to consider whether corresponding surplus disclosure satisfy that the corresponding requirements that sequential is repaired when repairing the violation of foundations/retention time.Especially multi-mode multiterminal angle (Multi-modemulti-corner now, MMMC) in Time-Series analysis and the process of reparation thereof, the timing condition that under all scenes, (scenario) pays close attention to should be considered, situation will become more complicated, the restorative procedure of its sequential is studied, finds out a kind of method repairing retention time violation rapidly and efficiently and seem that there is independent significance.
Higher for cell density in design, sequential repairs the situation of difficulty, does not have good solution at present temporarily, can only be the cell density reducing in design by the method for density domination in the process of design.In substantial amounts of sequential fix tool, sequential reparation in high density designs neither be highly desirable, the sequential fix tool ICE that such as present stage uses, it it is a reasonable efficient sequential fix tool, retention time violation is repaired, to existing unit before repairing in design without any changes mainly through inserting buffer cell in the strength of data road.In highdensity design, if instrument can not find enough spaces within the scope of the maximum search set and inserts buffer cell, just having some paths cannot repair.As shown in Figure 1, figure showing, prominent unit is terminal (endpoint) unit in the path having the retention time to violate, the local density of its position is higher, there are some spaces about but are not enough to insert a minimum buffer cell and violate to repair the retention time, so the violation instrument on this paths cannot be repaired, in the design of small-scale component-level, last such path can manually be repaired time fewer, but in large-scale design, although most violation repaired by instrument, but remaining violation bar number is still relatively many.Having been manually done relatively difficult, elapsed time is oversize, inefficiency, and it is possible to produce new setting up time violation and iterate and repeatedly could repair completely.
Summary of the invention
For in high density physical Design, existing sequential fix tool can not find enough spaces on the basis of highdensity design and inserts buffer cell, retention time cannot be violated and repair problem completely, the present invention proposes the restorative procedure of violation of a kind of retention time, it is by the position of mobile existing unit, and insert suitable reparation unit, finally repair all of retention time completely and violate.
The technical scheme is that
The restorative procedure that a kind of retention time violates, first, obtains from the result of static timing analysis and there is the path starting point of retention time violation, terminal and violation value；Its two, select the retention time to violate the terminal in path and be inserted into node as what repair unit, repair every time and be inserted into one buffer cell of node city or delay unit, to reduce the insertion reparation unit impact on other path sequential；They are three years old, the physical location that unit is put is searched inserting the near nodal repairing unit, by the position of original unit in mobile design to discharge the space repaired needed for unit, and target setting function makes total Least-cost of mobile unit, and intrinsic disturbance is less；Its four, generate repair logic accordingly, put unit, the engineering changing order of position of mobile unit；Finally, the annexation revising logic is carried out rewiring, then extracts parasitic parameter, carry out static timing analysis and confirm that the retention time repairs completely.
The restorative procedure that a kind of retention time violates, comprises the following steps:
The first step obtains from the result of static timing analysis exists the path starting point of retention time violation, terminal and violation value；
The result of 1.1 pairs of chip makes physical designs carries out static timing analysis, and (a Time-Series analysis scene refers to the mode of operation of chip and a kind of combination at manufacturing process angle to obtain each Time-Series analysis scene.For example, the mode of operation of one chip has function and test both of which, there are three kinds of process corner the worst, typical, best at manufacturing process angle, then just can be combined into " function+the worst ", " function+typical case ", " function+best ", " test+the worst ", " test+typical case " and " test+best " six kinds of Time-Series analysis scenes when static timing analysis.) in retention time violate path report；
1.2 obtain sequential from path report violates signal bound-time, terminal element-interconn ection linear load and violation value on the terminal in path, terminal unit input interconnection line；
Terminal in each scene is the same from path by 1.3 to be merged, and the sequential violation value after merging takes the maximum violation value under all scenes, is designated as ti, the retention time to cover all scenes violates；
1.4 finally obtain violation set of paths VP{vpi{ei,tri,loi,ti}}；
In set: vpiRepresent the i-th paths violated in set of paths, vpi∈ VP, i=1,2,3 ... n；
eiRepresent the terminal violating path；
triRepresent and violate signal bound-time on path termination element-interconn ection line；
loiRepresent the load violating path termination element-interconn ection line；
tiRepresent the violation value violating path.
Second step traversal violates set of paths, and in repair capsule, the retention time in each path violates one by one；
2.1 violate the terminal in path as the insertion node repairing unit using the retention time, select to insert the type of unit, insert and singly repair unit, revise logic connecting relation；
2.1.1 (i=1,2,3 ... n) paths, acquisition is inserted into the coordinate of node unit, namely violates the terminal unit coordinate (x in path to read i-thei,yei)；
2.1.2 the delay unit and the buffer cell that select several little multiple violate the unit list repaired as the retention time.For convenience of description, these unit can be designated as DEL_1, DEL_2, DEL_3, BUF_1, BUF_2, BUF_3 etc. respectively；
2.1.3 look-up table is passed through, the time delay size of unit selected in step 2.1.2 when bound-time tri and load loi is obtained, it is possible to be designated as tdel_1, tdel_2, tdel_3, tbuf_1, tbuf_2, tbuf_3 respectively from the timing sequence library file that technique manufacturer provides；
2.1.4 compare the magnitude relationship of delay value in retention time violation value ti and step 2.1.3, select unit time delay closest to the unit of violation value ti as the reparation unit repairing retention time violation；
2.1.5 connect node being inserted into, namely violate the unit selected by terminal inserting step 2.1.4 in path, revise logic connecting relation；
2.2, inserting near nodal lookup blank position, put insertion unit, eliminate overlap by the unit in mobile design；
2.2.1 to violate centered by path termination unit coordinate, each m row up and down, find in each distance k micrometer range in left and right and put the blank position repairing unit；
2.2.2 blank position is found, if the big reparation cell width of blank position width, then placement unit, it is not necessary to mobile；If the width of blank position is less than the width repairing unit, then need mobile unit to eliminate overlap；
2.2.3 in the process eliminating cells overlap, by acquiring unit attribute, it is impossible to mobile register cell or clock trees unit etc. have the unit of fixed attribute；
2.2.4 can not pass through original unit in mobile design such as the position selected at this and eliminate cells overlap, then abandon this position, return to step 2.2.1, again search blank position；If can not find blank position when 2.2.1 to, then hunting zone is expanded each 2*m row up and down, each 2*k micron in left and right, by that analogy；
2.2.5 obtain and repair unit particular location coordinate (xai, yai) and and insert the position coordinates (xoi, yoi) of original unit in the design of cells overlap；
2.2.6 note repairs the width of unit is wai, is highly hai, and the width of overlapped elements is woi, is highly hoi, thus can calculate being sized to of cells overlap part, such as Fig. 2；
waoverlap=| (xai+wai)-xoi|ifxai<xoi；
waoverlap=| (xoi+woi)-xai|ifxoi<xai；(1)
2.2.7 assume to insert that to repair after unit the initial position of any cell ci in design be (xi, yi), the coordinate after once moving be (x ' i, i), cell width is wi to y ', is highly hi, unit ci is moved, and its distance moved is:
di=| x 'i-xi|+|y′i-yi|(2)
2.2.8 being designated as its disturbed value by the port number of mobile unit, the disturbed value of unit ci is designated as its port number ei；Calculating the cost fm eliminating overlapping mobile unit is:
In formula, ei is the bar number of the mobile unit ci line having influence on, and is the port number of unit ci；
Di is the distance that unit is moved；
2.2.9 repeating step 2.2.1～2.2.8, traversal repairs all positions being inserted into repairing unit that unit is inserted within the scope of near nodal appointment, obtains mobile unit after unit is repaired in insertion and eliminates overlapping cost set F={fm, m=1,2, and 3 ...；
2.2.10 the blank position corresponding to f=min{fm} is chosen as being inserted reparation unit putting position in the design, and move unit elimination cells overlap according to minimum mobile cost, thus obtain being inserted reparation unit final position in the design for (xa ' i, ya ' is i)；
3rd step writes out engineering changing order that placement-and-routing's instrument can read to corresponding file.
3.1 go out to revise the engineering changing order of logic connecting relation according to step 2.1.5；
3.2 write out the order putting reparation unit according to step 2.2, and mobile unit eliminates overlapping order；
3.3 pairs of interconnection lines revising logic connecting relation arrange line weight, write out the order arranging interconnection line weighted value；
4th step runs the engineering changing order of rewiring in placement-and-routing's instrument, and the design revising logic connecting relation is carried out rewiring；
5th step card repairs result；Design after repairing is re-started static timing analysis, until design does not have any retention time to violate, confirms that the retention time violates and repair completely.
The invention has the beneficial effects as follows: repair unit by inserting, mobile unit elimination is inserted and is repaired the cells overlap that unit causes, and reduces to the full extent and repairs the impact that original design sequential is caused by retention time violation, and the retention time in repair capsule violates.
Accompanying drawing explanation
The higher schematic diagram causing the retention time to repair of Tu1Shi local density
Fig. 2 is that reparation model of element schematic diagram is inserted in path to be repaired；
Fig. 3 is the flow chart of the present invention；
Below with reference to the drawings and specific embodiments, the present invention is described in further detail.
Detailed description of the invention
As it is shown on figure 3, be the flow chart of the restorative procedure that the present invention a kind of retention time violates, the present invention comprises the following steps:
The first step obtains from the result of static timing analysis exists the path starting point of retention time violation, terminal and violation value；
The result of 1.1 pairs of chip makes physical design carries out static timing analysis, obtains the path report that the retention time in each scene violates；
1.2 obtain sequential from path report violates signal bound-time, terminal element-interconn ection linear load and violation value on the terminal in path, terminal unit input interconnection line；
Terminal in each scene is the same from path by 1.3 to be merged, and the sequential violation value after merging takes the maximum violation value under all scenes, is designated as ti, the retention time to cover all scenes violates；
1.4 finally obtain violation set of paths VP{vpi{ei,tri,loi,ti}}；
In set: vpiRepresent the i-th paths violated in set of paths, vpi∈ VP, i=1,2,3 ... n；
eiRepresent the terminal violating path；
triRepresent and violate signal bound-time on path termination element-interconn ection line；
loiRepresent the load violating path termination element-interconn ection line；
tiRepresent the violation value violating path；
Second step traversal violates set of paths, and in repair capsule, the retention time in each path violates one by one；
2.1 violate the terminal in path as the insertion node repairing unit using the retention time, select to insert the type of unit, insert and singly repair unit, revise logic connecting relation；
2.1.1 (i=1,2,3 ... n) paths, acquisition is inserted into the coordinate of node unit, namely violates the terminal unit coordinate (x in path to read i-thei,yei)；
2.1.2 the delay unit (* DEL*) and the buffer cell (* BUF*) that select several little multiple violate the unit list repaired as the retention time, and we select six kinds of unit of DEL_1, DEL_2, DEL_3, BUF_1, BUF_2, BUF_3 here.
2.1.3 by look-up table, from the timing sequence library file that technique manufacturer provides, obtain the time delay size of six kinds of unit when bound-time tri and load loi, be designated as tdel_1, tdel_2, tdel_3, tbuf_1, tbuf_2, tbuf_3 respectively；
2.1.4 compare the magnitude relationship of six delay values in retention time violation value ti and 2.1.3, select unit time delay closest to the unit of violation value ti as the reparation unit repairing retention time violation；
2.1.5 connecing node being inserted into, the terminal namely violating path inserts the unit selected by 2.1.4, revises logic connecting relation；
2.2, inserting near nodal lookup blank position, put insertion unit, eliminate overlap by the unit in mobile design；
2.2.1 to violate centered by path termination unit coordinate, each m row up and down, find in each distance k micrometer range in left and right and put the blank position repairing unit；
2.2.2 blank position is found, if the big reparation cell width of blank position width, then placement unit, it is not necessary to mobile；If the width of blank position is less than the width repairing unit, then need mobile unit to eliminate overlap；
2.2.3 in the process eliminating cells overlap, by acquiring unit attribute, it is impossible to mobile register cell or clock trees unit etc. have the unit of fixed attribute；
2.2.4 can not pass through original unit in mobile design such as the position selected at this and eliminate cells overlap, then abandon this position, return to step 2.2.1, again search blank position；If can not find blank position when 2.2.1 to, then hunting zone is expanded each 2*m row up and down, each 2*k micron in left and right, by that analogy；
2.2.5 obtain and repair unit particular location coordinate (xai, yai) and and insert the position coordinates (xoi, yoi) of original unit in the design of cells overlap；
2.2.6 note repairs the width of unit is wai, is highly hai, and the width of overlapped elements is woi, is highly hoi, thus can calculate being sized to of cells overlap part, such as Fig. 2；
waoverlap=| (xai+wai)-xoi|ifxai<xoi；
waoverlap=| (xoi+woi)-xai|ifxoi<xai；(1)
2.2.7 assume to insert that to repair after unit the initial position of any cell ci in design be (xi, yi), the coordinate after once moving be (x ' i, i), cell width is wi to y ', is highly hi, unit ci is moved, and its distance moved is:
di=| x'i-xi|+|y'i-yi|(2)
2.2.8 being designated as its disturbed value by the port number of mobile unit, the disturbed value of unit ci is designated as its port number ei；Calculating the cost fm eliminating overlapping mobile unit is:
In formula, ei is the bar number of the mobile unit ci line having influence on, and is the port number of unit ci；
Di is the unit ci distance moved；
2.2.9 repeating step 2.2.1～2.2.8, traversal repairs all positions being inserted into repairing unit that unit is inserted within the scope of near nodal appointment, obtains mobile unit after unit is repaired in insertion and eliminates overlapping cost set F={fm, m=1,2, and 3 ...；
2.2.10 the blank position corresponding to f=min{fm} is chosen as being inserted reparation unit putting position in the design, and move unit elimination cells overlap according to minimum mobile cost, thus obtain being inserted reparation unit final position in the design for (xa ' i, ya ' is i)；
3rd step writes out engineering changing order that placement-and-routing's instrument can read to corresponding file.
3.1 go out to revise the engineering changing order of logic connecting relation according to step 2.1.5；
3.2 write out the order putting reparation unit according to step 2.2, and mobile unit eliminates overlapping order；
3.3 pairs of interconnection lines revising logic connecting relation arrange line weight, write out the order arranging interconnection line weighted value；
4th step runs the engineering changing order of rewiring in placement-and-routing's instrument, and the design revising logic connecting relation is carried out rewiring；
5th step card repairs result；Design after repairing is re-started static timing analysis, until design does not have any retention time to violate, confirms that the retention time violates and repair completely.
Claims (2)
1. the restorative procedure of a retention time violation, it is characterised in that: first, obtain from the result of static timing analysis and there is the path starting point of retention time violation, terminal and violation value；Its two, select the retention time to violate the terminal in path and be inserted into node as what repair unit, repair every time and be inserted into one buffer cell of node city or delay unit, to reduce the insertion reparation unit impact on other path sequential；They are three years old, the physical location that unit is put is searched inserting the near nodal repairing unit, by the position of original unit in mobile design to discharge the space repaired needed for unit, and target setting function makes total Least-cost of mobile unit, and intrinsic disturbance is less；Its four, generate repair logic accordingly, put unit, the engineering changing order of position of mobile unit；Finally, the annexation revising logic is carried out rewiring, then extracts parasitic parameter, carry out static timing analysis and confirm that the retention time repairs completely.
2. the restorative procedure of a retention time violation, it is characterised in that: comprise the following steps:
The first step obtains from the result of static timing analysis exists the path starting point of retention time violation, terminal and violation value；
The result of 1.1 pairs of chip makes physical design carries out static timing analysis, obtains the path report that the retention time in each Time-Series analysis scene violates；
1.2 obtain sequential from path report violates signal bound-time, terminal element-interconn ection linear load and violation value on the terminal in path, terminal unit input interconnection line；
Terminal in each scene is the same from path by 1.3 to be merged, and the sequential violation value after merging takes the maximum violation value under all scenes, is designated as ti, the retention time to cover all scenes violates；
1.4 finally obtain violation set of paths VP{vpi{ei,tri,loi,ti}}；
In set: vpiRepresent the i-th paths violated in set of paths, vpi∈ VP, i=1,2,3 ... n；
eiRepresent the terminal violating path；
triRepresent and violate signal bound-time on path termination element-interconn ection line；
loiRepresent the load violating path termination element-interconn ection line；
tiRepresent the violation value violating path；
Second step traversal violates set of paths, and in repair capsule, the retention time in each path violates one by one；
2.1 violate the terminal in path as the insertion node repairing unit using the retention time, select to insert the type of unit, insert and singly repair unit, revise logic connecting relation；
2.1.1 (i=1,2,3 ... n) paths, acquisition is inserted into the coordinate of node unit, namely violates the terminal unit coordinate (x in path to read i-thei,yei)；
2.1.2 the delay unit and the buffer cell that select several little multiple violate the unit list repaired as the retention time；
2.1.3 by look-up table, from the timing sequence library file that technique manufacturer provides, the time delay size of each unit selected in step 2.1.2 when bound-time tri and load loi is obtained；
2.1.4 compare the magnitude relationship of delay value in retention time violation value ti and step 2.1.3, select unit time delay closest to the unit of violation value ti as the reparation unit repairing retention time violation；
2.1.5 connect node being inserted into, namely violate the unit selected by terminal inserting step 2.1.4 in path, revise logic connecting relation；
2.2, inserting near nodal lookup blank position, put insertion unit, eliminate overlap by the unit in mobile design；
2.2.1 to violate centered by path termination unit coordinate, each m row up and down, find in each distance k micrometer range in left and right and put the blank position repairing unit；
2.2.2 blank position is found, if the big reparation cell width of blank position width, then placement unit, it is not necessary to mobile；If the width of blank position is less than the width repairing unit, then need mobile unit to eliminate overlap；
2.2.3 in the process eliminating cells overlap, by acquiring unit attribute, it is impossible to mobile register cell or clock trees unit etc. have the unit of fixed attribute；
2.2.4 can not pass through original unit in mobile design such as the position selected at this and eliminate cells overlap, then abandon this position, return to step 2.2.1, again search blank position；If can not find blank position when 2.2.1 to, then hunting zone is expanded each 2*m row up and down, each 2*k micron in left and right, by that analogy；
2.2.5 obtain and repair unit particular location coordinate (xai, yai) and and insert the position coordinates (xoi, yoi) of original unit in the design of cells overlap；
2.2.6 note repairs the width of unit is wai, is highly hai, and the width of overlapped elements is woi, is highly hoi, thus can calculate being sized to of cells overlap part,
waoverlap=| (xai+wai)-xoi|ifxai<xoi；
waoverlap=| (xoi+woi)-xai|ifxoi<xai；(1)
2.2.7 assume to insert that to repair after unit the initial position of any cell ci in design be (xi, yi), the coordinate after once moving be (x ' i, i), cell width is wi to y ', is highly hi, unit ci is moved, and its distance moved is:
di=| x 'i-xi|+|y′i-yi|(2)
2.2.8 being designated as its disturbed value by the port number of mobile unit, the disturbed value of unit ci is designated as its port number ei；Calculating the cost fm eliminating overlapping mobile unit is:
In formula, ei is the bar number of the mobile unit ci line having influence on, and is the port number of unit ci；
Di is the unit ci distance moved；
2.2.9 repeating step 2.2.1～2.2.8, traversal repairs all positions being inserted into repairing unit that unit is inserted within the scope of near nodal appointment, obtains mobile unit after unit is repaired in insertion and eliminates overlapping cost set F={fm, m=1,2, and 3 ...；
2.2.10 the blank position corresponding to f=min{fm} is chosen as being inserted reparation unit putting position in the design, and move unit elimination cells overlap according to minimum mobile cost, thus obtain being inserted reparation unit final position in the design for (xa ' i, ya ' is i)；
3rd step writes out engineering changing order that placement-and-routing's instrument can read to corresponding file
3.1 go out to revise the engineering changing order of logic connecting relation according to step 2.1.5；
3.2 write out the order putting reparation unit according to step 2.2, and mobile unit eliminates overlapping order；
3.3 pairs of interconnection lines revising logic connecting relation arrange line weight, write out the order arranging interconnection line weighted value；
4th step runs the engineering changing order of rewiring in placement-and-routing's instrument, and the design revising logic connecting relation is carried out rewiring；
5th step card repairs result；Design after repairing is re-started static timing analysis, until design does not have the retention time to violate, confirms that the retention time violates and repair completely.
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