CN117131825A - Repair wiring method and device based on setup time - Google Patents
Repair wiring method and device based on setup time Download PDFInfo
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- CN117131825A CN117131825A CN202311405376.6A CN202311405376A CN117131825A CN 117131825 A CN117131825 A CN 117131825A CN 202311405376 A CN202311405376 A CN 202311405376A CN 117131825 A CN117131825 A CN 117131825A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The application provides a repair wiring method and device based on the establishment time, comprising the following steps: acquiring wiring to be repaired of a circuit; predefining an establishment time rule according to the wiring to be repaired; analyzing the wiring to be repaired through the time rule to obtain a first wiring set; performing incremental wiring on the first wiring set to obtain a second wiring set; comparing the time rule with the second wiring set to obtain a third wiring set; and determining the rationality of the wiring to be repaired according to the third wiring set. The application automatically repairs the paths violating the set-up time after the whole wiring by using the incremental wiring mode, and can reduce the number of the time violating paths and improve the time sequence performance of the circuit by using the incremental wiring mode.
Description
Technical Field
The application belongs to the technical field of software of programmable logic devices, and particularly relates to a repair wiring method and device based on setup time.
Background
The wiring is an important link in the FPGA CAD flow, and wiring resources are reasonably distributed to the wire nets in the circuit so as to ensure that the starting points and the ending points of all the wire nets can be connected and certain performance requirements are met. With the wide application of FPGA chips, the requirements on the operation speed of FPGA circuits are also increasing, and the timing has become an important factor for measuring the performance of FPGAs. The FPGA wiring plays a crucial role in the performance of FPGA CAD software. Particularly, as the technology level of integrated circuits is developed to deep submicron and ultra-deep submicron levels, the proportion of wiring channel delay of an FPGA circuit to the total path delay is increased, and the wiring result plays a key role in the time sequence performance of the circuit.
In FPGA sequential circuit design, users often specify timing constraints. The time constraint is established mainly in the following 3 types:
(1) Maximum clock frequency constraint
The most important of these timing constraints are the maximum clock frequency, the input port to register setup time, the register to output port output delay, etc. register setup time constraints. Current routing algorithms only consider the delay of the routing paths being de-optimized during the routing search, without continuously optimizing paths that still violate timing constraints after routing, which results in that these paths that violate timing constraints can never be satisfied unless the user modifies the circuit design or reduces the constraints.
(2) The set-up time Tsu between input IO and register
The setup time Tsu from input IO to the register is also a timing constraint often specified by users in design circuits, which represents the latest time before the data signal arrives at input IO earlier than the external clock signal arrives at clock input IO.
(3) Register to output IO long path constraint Tco
The minimum required output time Tco from register to output IO is also a common long path timing constraint that represents the maximum propagation delay of a data signal from register output to output IO.
In existing sequential circuit designs, the highest clock frequency at which the circuit can operate is often the performance of greatest concern to the user. Typically, a user will specify a maximum clock frequency constraint for the circuit when designing the circuit, which limits the number of registers that must be completed within a given period of the clock frequency. If not, the setup time constraints of the endpoint register are violated and the circuit cannot operate properly at the specified frequency.
Disclosure of Invention
The application provides a repair wiring method and device based on the set-up time to solve all or part of the problems in the prior art, so as to meet the time sequence constraint of a user, reduce the number of illegal paths of the set-up time and improve the time sequence performance of a circuit.
In order to achieve the above purpose, the technical scheme of the application is realized as follows:
an embodiment of the present application provides a method for repairing wiring based on setup time, including:
acquiring wiring to be repaired of a circuit; predefining an establishment time rule according to the wiring to be repaired; analyzing the wiring to be repaired through the time rule to obtain a first wiring set; performing incremental wiring on the first wiring set to obtain a second wiring set; comparing the time rule with the second wiring set to obtain a third wiring set; and determining the rationality of the wiring to be repaired according to the third wiring set.
Based on the above, the set-up time rule includes at least one of:
a first setup time margin;
a first arrival time of the node;
a first required arrival time of the node;
the first path is delayed.
Analyzing the wiring to be repaired through the time rule to obtain a first wiring set, and further comprising:
acquiring a node of a wiring to be repaired;
scanning the node for the first time to obtain a second arrival time of the node;
scanning the node for the second time to obtain a second required arrival time of the node;
determining a second setup time margin according to a second arrival time of the node and a second required arrival time of the node;
and comparing the first establishing time margin with the second establishing time margin to obtain a first wiring set.
Comparing the first setup time margin with the second setup time margin to obtain a first wiring set, and further comprising:
if the second establishing time margin is smaller than the first establishing time margin, determining that the wiring to be repaired belongs to a first wiring set; wherein the first set of wires includes at least wires that violate a setup time rule.
Performing incremental wiring on the first wiring set to obtain a second wiring set, and further comprising:
determining a first wiring resource according to the wiring to be repaired;
determining a fourth wiring set from the first wiring set according to the first wiring resource;
determining a second path delay according to the fourth wiring set;
comparing the first path delay with the second path delay to determine a second wiring set; if the second path delay is greater than the first path delay, the first wiring set belongs to a second wiring set; otherwise, the fourth wiring set belongs to the second wiring set.
Comparing the set-up time rule with the second wiring set to obtain a third wiring set, and further comprising:
if the second wiring set meets the time establishment rule, a third wiring set is obtained; otherwise, determining third path delay according to the second wiring set;
calculating the difference value of the third path delay and the first path delay, and determining a first target connection;
determining a fifth wiring set according to the first target connection;
determining a third setup time margin from the fifth set of wires;
and comparing the third establishing time margin with the first establishing time margin to obtain a third wiring set.
Comparing the third setup time margin with the first setup time margin to obtain a third wiring set, and further including:
if the third setup time margin is greater than the first setup time margin, the fifth wiring set belongs to a third wiring set; otherwise, the second set of wires belongs to the third set of wires. By means of the method, each wiring connection which violates the time constraint is repaired one by one, so that the delay of a wiring path is further reduced, and the time constraint is met.
A second aspect of an embodiment of the present disclosure provides a repair wiring device based on a setup time, the device comprising: the acquisition module is used for acquiring the wiring to be repaired of the circuit; a predefining module predefining an establishing time rule according to the wiring to be repaired; the analysis module is used for analyzing the wiring to be repaired through the time rule to obtain a first wiring set; the building module is used for carrying out incremental wiring on the first wiring set to obtain a second wiring set; the processing module compares the time rule with the second wiring attribute to obtain a third wiring set; and the confirmation module is used for determining the rationality of the wiring to be repaired according to the third wiring set.
A third aspect of an embodiment of the present disclosure provides an electronic device, including: a memory; and a processor, connected to the memory, configured to implement the repair wiring method based on the setup time provided in any of the foregoing first or second aspects by executing computer executable instructions stored on the memory.
A fourth aspect of the disclosed embodiments provides a computer storage medium comprising: the computer storage medium stores computer-executable instructions; after the computer executable instructions are executed, the repair wiring method based on the setup time provided by any of the foregoing first aspect or second aspect can be implemented.
Compared with the prior art, the application has the main beneficial effects that: and after the whole wiring, automatically repairing paths which violate the time constraint establishment so as to meet the time constraint of a user, thereby reducing the number of the time constraint establishment paths and improving the time sequence performance of the circuit.
Drawings
FIG. 1 is a schematic flow chart of a method for repairing wiring based on setup time provided by the application;
fig. 2 is a schematic flow chart of an automatic repair setup time violation path of a setup time-based repair wiring method according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of all setup time-violating connection delta wiring of a setup time-based repair wiring method provided in an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an incremental repair setup time violation connection for a setup time-based repair routing method provided by an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a repair wiring device based on setup time according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure;
Detailed Description
So that the manner in which the features and objects of the present application can be understood in more detail, a more particular description of the application, briefly summarized above, may be had by reference to the appended drawings, which are not necessarily limited to the embodiments described.
As shown in fig. 1, an embodiment of the present disclosure provides a repair wiring method based on a setup time, the method including:
s110: acquiring wiring to be repaired of a circuit;
s120: predefining an establishment time rule according to the wiring to be repaired;
s130: analyzing the wiring to be repaired through the time rule to obtain a first wiring set;
s140: performing incremental wiring on the first wiring set to obtain a second wiring set;
s150: comparing the time rule with the second wiring set to obtain a third wiring set;
s160: and determining the rationality of the wiring to be repaired according to the third wiring set.
The embodiment of the present disclosure provides a repair wiring method based on a setup time, which can be applied to various electronic devices including, but not limited to: an integrated circuit.
Incremental wiring refers to re-wiring only for a net or a connection without changing the wiring paths of the vast majority of other nets, and does not occupy wiring resource points already occupied in the wiring paths of other nets during re-wiring. The purpose of incremental wiring is to extend the wiring path delay of reconnection by re-wiring so as to achieve the delay required by meeting short-time constraint, and by adopting the mode, the wiring paths of other nets are not changed, only the wiring paths needing to be re-wired are changed, and the optimization success rate and efficiency are higher.
FPGA placement and routing is the process of mapping logic circuits onto FPGA specific hardware resources; layout refers to the mapping of logic circuits to physical locations on the FPGA, and routing connects these physical locations to each other through programmable wiring resources within the FPGA. In the wiring process, the function related circuit modules need to be considered to be placed at adjacent positions so as to reduce signal transmission delay; shortening the clock signal transmission path, reducing clock jitter and clock offset; assigning input-output pins to the nearest on-chip I/O resources to reduce signal propagation delay; layout wiring constraints are set according to design requirements. In the present application, paths that violate the setup time constraint are automatically repaired after the global routing to satisfy the timing constraint of the user.
In some embodiments, the S110 may include:
all nets are routed through a timing driven routing algorithm. The cost function of the timing drive wiring is:
(1)
(2)
in the composition of formula (1), where n represents a wiring candidate resource point and b (n) represents a basic cost of the resource point n; h (n) represents the historical cost of resource point n, and the accumulated congestion cost of using point n after each iteration is recorded; p (n) represents the current congestion cost of point n and varies with the number of times that the current point n is reused; delay (n) represents the delay of the source point n and Crit (i, j) represents the criticality of the connection from the start of net i to fan-out j with respect to the critical path. The calculation method of the criticality Crit (i, j) is shown in a formula (2); where Dmax represents the critical path delay, slack (i, j) represents the margin of the fan-out point j of net i, maxCrit andis a parameter value; wherein, the MaxCrit refers to the maximum criticality, and the greater the MaxCrit is, the greater the criticality is; said->Refers to the delay compromise coefficient in connection, < ->The smaller the criticality, the smaller; by said MaxCrit and said +.>To control the impact of the slack on the balance between congestion and delay. As can be seen from the formula (1), the cost function of the timing wiring mainly consists of two parts, namely the timing cost and the congestion cost, and the balance point of the timing wiring and the congestion cost is controlled by a key factor Crit.
In some embodiments, the S120 may include:
the setup time rule includes at least one of:
a first setup time margin;
a first arrival time of the node;
a first required arrival time of the node;
the first path is delayed.
The first setup time margin is equal to a difference of a first required arrival time of the node minus a first arrival time of the node and a first path delay; the value of the first setup time margin value may be a predetermined empirical value or an experimental value such as 0,1,2, or 3.
In some embodiments, the S130 may include:
and obtaining a wiring connection set C with all the setup time margins (slacks) smaller than 0 by adopting a method of setup time analysis. The method for establishing the time analysis is to complete the process of the time analysis through two times of traversing the time chart. Firstly, scanning from top to bottom on a time sequence diagram to calculate the arrival time of each nodeThen scanning from bottom to top to obtain the required arrival time of each node>The slot value for each start-end connection is then calculated.
In some embodiments, the S140 may include:
traversing the first wiring set, namely, each connection in the wiring connection set against the establishment time constraint, and wiring the connection set in an incremental wiring mode. Incremental routing is searching for the shortest path for the connection with the current wire resources remaining. Nodes marking other net routing paths are not available and candidate nodes currently connecting incremental routing can only be searched from among the available nodes. The purpose of the incremental routing is to search for the path of shortest delay.
After the first wiring set is one connection increment wiring in the wiring connection set violating the setup time constraint, calculating the delay of the connection wiring path, if the new delay is reduced compared with the delay before the increment wiring, storing a new wiring result as the wiring result of the current connection, and restarting the setup time analysis to obtain a second wiring set, namely the latest wiring connection set violating the setup time constraint; otherwise, the wiring result before incremental wiring is restored.
And judging that all illegal connections have been subjected to incremental wiring or the maximum optimization times are reached, and stopping optimization if all connections have been subjected to incremental wiring or the maximum optimization times are reached.
In some embodiments, the S150 may include:
if the second wiring set meets the time establishment rule, a third wiring set is obtained; otherwise, determining third path delay according to the second wiring set;
calculating the difference value of the third path delay and the first path delay, and determining a first target connection;
determining a fifth wiring set according to the first target connection;
determining a third setup time margin from the fifth set of wires;
and comparing the third establishing time margin with the first establishing time margin to obtain a third wiring set.
Comparing the third setup time margin with the first setup time margin to obtain a third wiring set, and further including:
if the third setup time margin is greater than the first setup time margin, the fifth wiring set belongs to a third wiring set; otherwise, the second set of wires belongs to the third set of wires.
In particular, the method comprises the steps of,
after the target connection is found, other net sets occupying the shortest path node on the wiring path are obtained, namely the net set affecting the delay of the current target connection. The shortest delay path of the target connection is then taken as its routing path and all net paths in the net set are torn down. And finally, carrying out incremental negotiation wiring on the wire networks needing to be re-wired by adopting a time sequence driving wiring algorithm by using the rest wiring resources. And after incremental negotiation wiring, performing the slot analysis again, and calculating a new fifth wiring set of the connection set with the smallest slot. If the slot value of the fifth wiring set is larger than that of the second wiring set, the optimization is successful, a new wiring result is reserved, the fifth wiring set is used as a current optimized connection set, and the next round of optimization is carried out; if the slack is not good, the optimization is not successful, the original wiring result is returned again, the current connection is marked as non-optimizable, and the next round of optimization is carried out.
In some embodiments, the S160 may include:
paths that violate the set-up time constraint are automatically repaired after the global routing to satisfy the timing constraints of the user. By the method, the number of the establishment time violation paths can be reduced, and the time sequence performance of the circuit is improved.
As shown in fig. 2, a schematic flow chart of an automatic repair setup time violation path of a setup time-based repair wiring method is provided in the present embodiment;
in some embodiments of the present application, in some embodiments,
all nets are routed through a timing driven routing algorithm. The cost function of the timing drive wiring is:
(1)
(2)
in the composition of formula (1), where n represents a wiring candidate resource point and b (n) represents a basic cost of the resource point n; h (n) represents the historical cost of resource point n, and the accumulated congestion cost of using point n after each iteration is recorded; p (n) represents the current congestion cost of point n and varies with the number of times that the current point n is reused; delay (n) represents the delay of the source point n and Crit (i, j) represents the criticality of the connection from the start of net i to fan-out j with respect to the critical path. The calculation method of the criticality Crit (i, j) is shown in a formula (2); where Dmax represents the critical path delay, slack (i, j) represents the margin of the fan-out point j of net i, maxCrit andis a parameter value; wherein, the MaxCrit refers to the maximum criticality, and the greater the MaxCrit is, the greater the criticality is; said->Refers to the delay trade-off coefficient in the connection,/>the smaller the criticality, the smaller; by said MaxCrit and said +.>To control the impact of the slack on the balance between congestion and delay. As can be seen from the formula (1), the cost function of the timing wiring mainly consists of two parts, namely the timing cost and the congestion cost, and the balance point of the timing wiring and the congestion cost is controlled by a key factor Crit.
Obtaining a wiring connection set C with all the setup time margins (slacks) smaller than 0 by a method of setup time analysis; the setup time margin refers to the margin of the fanout point j of all nets i. The method for establishing the time analysis is to complete the process of the time analysis through two times of traversing the time chart. Firstly, scanning from top to bottom on a time sequence diagram to calculate the arrival time of each nodeThe method comprises the steps of carrying out a first treatment on the surface of the The arrival time of each node refers to the maximum delay of signal transmission from a starting point to a current node; then scanning from bottom to top to obtain the required arrival time of each node>The method comprises the steps of carrying out a first treatment on the surface of the The required arrival time is the maximum delay of signal transmission to the current node according to the time sequence constraint requirement; further calculating a slot value of each starting point-end point connection through a formula (3); wherein, the delay refers to the delay of the current connection. The time sequence analysis mode can acquire the setup time margin of all the connections.
(3)
Traversing each connection in set C, incremental routing is performed for each connection with current remaining routing resources. Incremental routing is searching for the shortest path for the connection with the current wire resources remaining, the cost function only taking into account path delays, as shown in equation (4):
(4)
wherein, cost (n) refers to a Cost function, and delay (n) refers to a delay of connection. For any connection in the set C, calculating the delay of the connection wiring path after incremental wiring, if the delay is reduced compared with that before the incremental wiring, saving the wiring result, otherwise, restoring to the original wiring result. And after each connection in the set C runs the incremental wiring, re-running the build time analysis to obtain a wiring connection set C with the minimum current build time margin.
If all the connections of the set C meet the time constraint, stopping the algorithm, otherwise traversing each connection in the set C, and performing incremental restoration on the incremental negotiation method of each connection; wherein, the time constraint condition is that the delay of all paths is less than one period of the working clock. First, the shortest path is searched for each connection in set C, and the difference between the current path delay and the shortest path delay is calculated. And finding one connection with the largest difference value in the set C, and taking the connection as the currently preferred target connection.
If all connections of set C have been optimal solutions or marked as non-optimizable connections, the algorithm stops optimization. After the target connection is found, other net sets occupying the shortest path node on the wiring path are obtained, namely the net set affecting the delay of the current target connection. The shortest delay path of the target connection is then taken as its routing path and all net paths in the net set are torn down. And finally, carrying out incremental negotiation wiring on the wire networks needing to be re-wired by adopting a time sequence driving wiring algorithm by using the rest wiring resources. The incremental negotiation routing is followed by a new slack analysis to calculate a new minimum connection set C'. If the slot value of C 'is larger than that of C, the optimization is successful, a new wiring result is reserved, the set C' is used as a current optimized connection set C, and the next round of optimization is carried out; if the slack is not good, the optimization is not successful, the original wiring result is returned again, the current connection is marked as non-optimizable, and the next round of optimization is carried out.
As shown in fig. 3, a schematic diagram of all setup time-violating connection incremental routing of a repair routing method based on setup time is provided in this embodiment;
in some embodiments of the present application, in some embodiments,
each connection in the set of connection C is first routed in an incremental routing manner by traversing the connections that violate the setup time constraint. Incremental routing is searching for the shortest path for the connection with the current wire resources remaining. Nodes marking other net routing paths are not available and candidate nodes currently connecting incremental routing can only be searched from among the available nodes. The purpose of incremental wiring is to search for the path with the shortest delay, and the cost function adopts formula (4) and only considers the delay cost of the node.
After one connection increment wiring in the wiring connection set C violating the establishment time constraint is subjected to calculation, if the new delay is reduced compared with the delay before increment wiring, the new wiring result is saved as the wiring result of the current connection, and the establishment time analysis is restarted, so that the latest wiring connection set C violating the establishment time constraint is obtained; otherwise, the wiring result before incremental wiring is restored.
Judging that all illegal connections are subjected to incremental wiring or reach the maximum optimization times, if all connections are subjected to incremental wiring or reach the maximum optimization times, stopping optimization, so that required wiring resources are obtained, the time sequence of the circuit is critical, the number of establishment time illegal paths can be reduced, and the time sequence performance of the circuit is improved.
As shown in fig. 4, a schematic diagram of incremental repair setup time violation connection of a setup time-based repair wiring method is provided in this embodiment;
in some embodiments of the present application, in some embodiments,
searching for the shortest path for each connection in set C is not limited by the current occupied wiring resource point, meaning that any wiring resource can be used to search for the shortest path for the current connection. The cost function of searching the shortest path adopts the formula (4), and only the delay cost is considered.
And calculating the difference value between the current path delay and the shortest path delay, and stopping the algorithm if each connection in the set C is the optimal solution. Otherwise, finding a connection with the largest difference between the current delay and the shortest delay as the current optimized target connection. And replacing the wiring path of the current target connection with the searched shortest path.
And traversing wiring paths of other nets according to nodes in the shortest path of the current target connection, and acquiring a net set N occupying the nodes of the shortest path on the wiring paths.
The routing paths affecting each net in net set N are removed.
And for each net affecting the net set N, using the residual wiring resources, and adopting a time sequence driving wiring algorithm to carry out incremental negotiation wiring. The incremental negotiation wires also marks nodes of other net wire paths outside the set N as unavailable, and the candidate nodes for the wires can only be searched from the available nodes. The cost function employed by the delta negotiation routing is equation (1), where the value of Crit (i, j) is obtained from the criticality of the last setup time analysis.
And after the incremental negotiation wiring, carrying out establishment time analysis again, and calculating a new connection set C' with the minimum establishment time margin. If the margin value of the set C 'is larger than the margin of the set C, the optimization is successful, the result of incremental negotiation wiring is reserved, the set C' is used as a current optimized connection set, and the next round of optimization is carried out; if the margin is not good, the optimization is not successful, the wiring result before incremental negotiation is restored, the current connection is marked as non-optimizable, and the next round of optimization is carried out. The termination condition of the algorithm is that there are no optimizable connections in the connection set C with the smallest current margin. Each wiring connection violating the time constraint is repaired one by one through incremental negotiation wiring, so that the delay of wiring paths is further reduced, the constraint of the time is met, the number of the time violating paths can be reduced, and the time sequence performance of the circuit is improved.
As shown in fig. 5, a schematic structural diagram of a repair wiring device based on a setup time is provided in the present embodiment;
an acquiring module 110, configured to acquire a wire to be repaired of the circuit;
a predefining module 120 predefining an establishment time rule according to the wiring to be repaired;
the analysis module 130 is used for analyzing the wiring to be repaired through the time rule to obtain a first wiring set;
the building module 140 performs incremental wiring on the first wiring set to obtain a second wiring set;
the processing module 150 compares the setup time rule with the second wiring attribute to obtain a third wiring set;
and a confirmation module 160 for determining the rationality of the wiring to be repaired according to the third wiring set.
In some embodiments, the acquisition module 110, the predefined module 120, the analysis module 130, the establishment module 140, the processing module 150, and the determination module 160 may be program modules; the program modules may implement the operations of the various modules described above when executed by a processor.
In other embodiments, the acquisition module 110, the predefined module 120, the analysis module 130, the creation module 140, the processing module 150, and the determination module 160 may be a hard-soft combination module; the soft and hard combined die block comprises but is not limited to: various programmable arrays; the programmable array includes, but is not limited to: a field programmable array and/or a complex programmable array.
In still other embodiments, the acquisition module 110, the predefined module 120, the analysis module 130, the creation module 140, the processing module 150, and the determination module 160 may be purely hardware modules; the pure hardware modules wrap around but are not limited to: an application specific integrated circuit.
As shown in fig. 6, an embodiment of the present disclosure provides an electronic device, including:
a memory;
a processor, coupled to the memory, for enabling the implementation of the methods provided in any of the preceding embodiments, e.g., performing the methods as shown in any of fig. 1-4, by executing computer-executable instructions stored on the memory.
The electronic device may be a terminal device and/or a server in a service platform.
As shown in fig. 6, the electronic device may also include a network interface that may be used to interact with a peer device over a network.
Embodiments of the present disclosure provide a computer storage medium having stored thereon computer-executable instructions; the computer-executable instructions, when executed by a processor, enable the method provided by any of the foregoing embodiments, such as performing the method as shown in any of figures 1-4.
It should be understood that in several embodiments provided by the present application, the disclosed apparatus and methods may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A repair wiring method based on a setup time, comprising:
acquiring wiring to be repaired of a circuit;
predefining an establishment time rule according to the wiring to be repaired;
analyzing the wiring to be repaired through the time rule to obtain a first wiring set;
performing incremental wiring on the first wiring set to obtain a second wiring set;
comparing the time rule with the second wiring set to obtain a third wiring set;
and determining the rationality of the wiring to be repaired according to the third wiring set.
2. The set-up time based repair cabling method of claim 1, wherein the predefined set-up time rules comprise at least one of:
a first setup time margin;
a first arrival time of the node;
a first required arrival time of the node;
the first path is delayed.
3. The method for repairing wiring based on setup time according to claim 2, wherein analyzing the wiring to be repaired by the setup time rule to obtain a first wiring set, further comprises:
acquiring a node of a wiring to be repaired;
scanning the node for the first time to obtain a second arrival time of the node;
scanning the node for the second time to obtain a second required arrival time of the node;
determining a second setup time margin according to a second arrival time of the node and a second required arrival time of the node;
and comparing the first establishing time margin with the second establishing time margin to obtain a first wiring set.
4. The setup time based repair routing method of claim 3, wherein comparing the first setup time margin and the second setup time margin results in a first set of wires, further comprising:
if the second establishing time margin is smaller than the first establishing time margin, determining that the wiring to be repaired belongs to a first wiring set; wherein the first set of wires includes at least wires that violate a setup time rule.
5. The setup time-based repair wiring method according to claim 2, wherein the incremental wiring is performed on the first wiring set to obtain a second wiring set, further comprising:
determining a first wiring resource according to the wiring to be repaired;
determining a fourth wiring set from the first wiring set according to the first wiring resource;
determining a second path delay according to the fourth wiring set;
comparing the first path delay with the second path delay to determine a second wiring set; if the second path delay is greater than the first path delay, the first wiring set belongs to a second wiring set; otherwise, the fourth wiring set belongs to the second wiring set.
6. The method of repairing a wire based on setup time of claim 5, wherein comparing the set-up time rule to the second wire set results in a third wire set, further comprising:
if the second wiring set meets the establishment time rule, a third wiring set is obtained; otherwise, determining third path delay according to the second wiring set;
calculating the difference value of the third path delay and the first path delay, and determining a first target connection;
determining a fifth wiring set according to the first target connection;
determining a third setup time margin from the fifth set of wires;
and comparing the third establishing time margin with the first establishing time margin to obtain a third wiring set.
7. The setup time based repair routing method of claim 6, wherein comparing the magnitudes of the third setup time margin and the first setup time margin results in a third set of wires, further comprising:
if the third setup time margin is greater than the first setup time margin, the fifth wiring set belongs to a third wiring set; otherwise, the second set of wires belongs to the third set of wires.
8. A repair wiring device based on setup time, comprising:
the acquisition module is used for acquiring the wiring to be repaired of the circuit;
a predefining module predefining an establishing time rule according to the wiring to be repaired;
the analysis module is used for analyzing the wiring to be repaired through the time rule to obtain a first wiring set;
the building module is used for carrying out incremental wiring on the first wiring set to obtain a second wiring set;
the processing module compares the time rule with the second wiring set to obtain a third wiring set;
and the confirmation module is used for determining the rationality of the wiring to be repaired according to the third wiring set.
9. An electronic device, comprising:
a memory;
a processor, coupled to the memory, for executing computer-executable instructions stored on the memory and capable of implementing the set-up time based repair wiring method provided in any one of claims 1 to 7.
10. A computer storage medium having stored thereon computer executable instructions; the computer-executable instructions, when executed, enable the repair cabling method based on setup time provided in any one of claims 1 to 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117574820A (en) * | 2024-01-15 | 2024-02-20 | 中科亿海微电子科技（苏州）有限公司 | Incremental time sequence analysis method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104881507A (en) * | 2014-02-28 | 2015-09-02 | 国际商业机器公司 | Method and apparatus for repairing hold time violations in circuit |
| CN105787213A (en) * | 2016-04-01 | 2016-07-20 | 中国人民解放军国防科学技术大学 | Repairing method of retention time violation |
| CN106682306A (en) * | 2016-12-26 | 2017-05-17 | 西安电子科技大学 | Rapid FPGA wire arrangement method |
| CN112232005A (en) * | 2020-09-25 | 2021-01-15 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, equipment and storage medium for repairing hold time violation |
| CN112597739A (en) * | 2020-12-30 | 2021-04-02 | 瓴盛科技有限公司 | Method and apparatus for repairing hold time violations in a circuit |
-
2023
- 2023-10-27 CN CN202311405376.6A patent/CN117131825B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104881507A (en) * | 2014-02-28 | 2015-09-02 | 国际商业机器公司 | Method and apparatus for repairing hold time violations in circuit |
| CN105787213A (en) * | 2016-04-01 | 2016-07-20 | 中国人民解放军国防科学技术大学 | Repairing method of retention time violation |
| CN106682306A (en) * | 2016-12-26 | 2017-05-17 | 西安电子科技大学 | Rapid FPGA wire arrangement method |
| CN112232005A (en) * | 2020-09-25 | 2021-01-15 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, equipment and storage medium for repairing hold time violation |
| CN112597739A (en) * | 2020-12-30 | 2021-04-02 | 瓴盛科技有限公司 | Method and apparatus for repairing hold time violations in a circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117574820A (en) * | 2024-01-15 | 2024-02-20 | 中科亿海微电子科技（苏州）有限公司 | Incremental time sequence analysis method |
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