CN112232005A - Method, system, equipment and storage medium for repairing hold time violation - Google Patents

Method, system, equipment and storage medium for repairing hold time violation Download PDF

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CN112232005A
CN112232005A CN202011036592.4A CN202011036592A CN112232005A CN 112232005 A CN112232005 A CN 112232005A CN 202011036592 A CN202011036592 A CN 202011036592A CN 112232005 A CN112232005 A CN 112232005A
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time violation
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CN112232005B (en
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高永亮
邱进超
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
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Abstract

The invention discloses a method, a system, equipment and a storage medium for repairing a hold time violation, wherein the method comprises the following steps: finding out all paths with hold time violation in the circuit through time sequence analysis, and acquiring an establishment time margin of a termination point of the paths; calculating the ratio of the establishing time margin and the holding time violation of the path, and dividing the path into a first path and a second path according to a predefined rule; iteratively repairing the hold time violation of the first type of path using the first type of process standard cell; iteratively repairing the hold time violation of the second type of path using a second type of process standard cell; the voltage threshold of the first type of process is higher than that of the second type of process. The system comprises an illegal path acquisition module, a path classification module, a first type path restoration module and a second type path restoration module. The invention can not only completely repair the retention time violation, but also control the number of the inserted standard units, reduce the occupied area and reduce the increased power consumption.

Description

Method, system, equipment and storage medium for repairing hold time violation
Technical Field
The invention relates to the field of integrated circuit design, in particular to a method, a system, equipment and a storage medium for repairing hold time violation.
Background
Currently, integrated circuits have entered the era of Large Scale Integration (LSI) and Very Large Scale Integration (VLSI), and the Scale of the circuits has rapidly risen to tens of millions of gates or even hundreds of millions of gates. For today's Integrated Circuit (IC) design companies, designers face two biggest problems: firstly, the timing problem in design; secondly, the verification time is too long.
There are two main approaches to analyzing or verifying the timing aspects of a circuit design: dynamic Timing Simulation (Dynamic Timing Simulation) and Static Timing Analysis (Static Timing Analysis). The dynamic time sequence simulation may not detect the time sequence failure of some paths due to the limitation of the input vector, the static time sequence analysis may clearly indicate the circuit part where the time sequence failure occurs because all paths are traversed, and in addition, the static time sequence analysis method may quickly obtain the analysis result because no input vector is required, thereby saving much design time. The goal of static timing analysis is to find critical paths of circuitry that invalidate chip timing and are critical to chip performance. It adopts an exhaustive analysis method, extracts all timing paths existing in the whole circuit, calculates the propagation delay of the signal on the paths, checks whether the setup time (setup) and hold time (hold) of the signal meet the timing requirement, and finds out the error violating the timing constraint by analyzing the maximum path delay and the minimum path delay. In addition, the development of software technology enables the static time sequence analysis software to meet the requirements of full-chip analysis in terms of functions and performance, supports the system design on a chip, and provides powerful support for obtaining the design time sequence requirements as soon as possible.
In static timing analysis, all timing paths can be divided into 4 types according to the difference between the starting point and the ending point of the timing path: input port to first stage flip-flop, first stage flip-flop to second stage flip-flop, second stage flip-flop to output port, input port to output port. Four timing paths in a practical design are shown in fig. 1. Wherein, Path1 is from the input port In to the D terminal of the first stage flip-flop, and Path2 is from the Clk terminal of the first stage flip-flop to the D terminal of the second stage flip-flop; path3 is the Clk end of the second stage flip-flop to the output port OUT; path4 is the input port In to the output port OUT.
According to the timing constraints defined by designers, an Electronic Design Automation (EDA) tool checks all timing paths in the Design for hold time violations (hold violations) according to 4 different types of timing paths.
As shown in fig. 2, taking Path2 from the first level flip-flop to the second level flip-flop as an example, the checking manner of the setup time and the hold time is explained. The timing analysis needs to calculate the delay of a transmission Clock Path (Launch Clock Path), a Capture Clock Path (Capture Clock Path) and a Data Path (Data Path), wherein the Launch Clock Path refers to a Clock Path from a Clock signal end to a first stage flip-flop, the Capture Clock Path refers to a Path from the Clock signal end to a second stage flip-flop, and the Data Path refers to a combinational logic Path from the first stage flip-flop to the second stage flip-flop.
Setup refers to the time that the data at the input of the second stage flip-flop needs to remain stable before the clock active edge reaches the second stage flip-flop. Equation (1) is the designer's equation for setup inspection, where TsetupIs setup, T of the second stage flip-flop FF2launchIs the delay, T, of Launch Clock PathdpIs Data Path delay, TcaptureIs the delay, T, of the Capture Clock Pathck2qIs the delay from the internal clock terminal Clk to the Q terminal of the first stage flip-flopperiodIs the clock period that drives the flip-flop.
Tlaunch+Tck2q+Tdp<Tcapture+Tperiod–Tsetup (1)
Hold refers to the time that the data at the input of the second stage flip-flop needs to be held steady after the active edge of the clock reaches the second stage flip-flop. Similar to setup, in order to consider the most strict case, the fastest Path among Launch Clock Path, Data Path, Capture Clock is calculated at the time of hold check, and equation (2) is an equation for checking the retention time, where TholdIs the hold time, T, required for the second stage flip-flop FF2launchIs Launch Clock Path delay, TdpIs DataDelay of Path, Tck2qIs the delay from the internal clock terminal Clk to the Q terminal of the first stage flip-flopperiodIs the clock period that drives the flip-flop.
Tlaunch+Tck2q+Tdp>Tcapture+Thold (2)
The corresponding clock diagrams for Setup and hold checks are shown in FIG. 3, where hold is checked on the same clock edge of FF1 and FF2, and Setup is checked one clock cycle apart between FF1 and FF 2.
The setup time margin (setup margin) refers to a setup time margin satisfying a timing design requirement, and formula (3) is a calculation formula thereof.
setup margin＝Tcapture+Tperiod–Tsetup–(Tlaunch+Tck2q+Tdp) (3)
The setup time violation (setup vision) refers to a time when the real time of a time sequence path in a chip does not meet the design requirement, and the time sequence path does not meet the formula (1), that is, when the setup margin is less than zero, the time sequence path has the setup violation invention content.
The hold margin (hold margin) refers to a hold margin satisfying the timing design requirement, and formula (4) is a calculation formula thereof.
Hold margin＝Tlaunch+Tck2q+Tdp–(Tcapture+Thold) (4)
The hold time violation (hold vision) refers to the time when the real time of a timing path in a chip does not meet the design requirement, and the timing path does not meet the formula (2), namely, when the hold margin is less than zero, the timing path has the hold violation.
In the chip design process, if setup vision is not repaired cleanly, the finally manufactured chip cannot reach the expected operating frequency, and if hold vision is not repaired cleanly, the manufactured chip cannot work. Therefore, before the chips are taped out, it is necessary to ensure that all timing violations are repaired.
In the conventional method for repairing hold vision, when a timing violation of a path is repaired, a time margin on the path must be considered. When a static time sequence analysis tool or other time sequence repair tools repair retention time violations, for a path with retention time violations, the tool may traverse the path to determine whether there are enough setup flags to repair hold navigation.
As shown in fig. 4, on the timing path from the first stage flip-flop FF1 to the second stage flip-flop FF2, the clock is CLK, and the chip manufacturer provides the slowest process corner (ss corner) and the fastest process corner (FF corner), where the delay of the standard cell is the largest under the ss corner operating condition and the delay of the standard cell is the smallest under the FF corner operating condition. Therefore, for the most pessimistic consideration, when checking the hold condition of a path, the ff core should be selected, and when repairing the hold visualization on the path, the setup margin under the ss core needs to be considered. The timing report (timing report) for the timing path shown in fig. 4 is as follows:
(1)Hold summary check:
Figure BDA0002702132570000041
(2)Setup summary check:
Figure BDA0002702132570000042
from the above setup and hold timing report analyses from FF1 to FF2, it can be seen that hold visualization is 59ps and setup margin is 337ps from FF1 to FF 2.
In a Standard cell library provided by a chip manufacturer, different threshold Voltage processes may be performed for the same Standard cell, including a High threshold Voltage process (HVT), a Standard threshold Voltage process (SVT), a Low threshold Voltage process (LVT), an Ultra Low threshold Voltage process (ULVT), and the like, where a Standard cell of an HVT type has the smallest static power consumption and the smallest driving capability; the standard cell of the ULVT type has the largest static power consumption and the strongest driving capability.
When the hold isolation is repaired, if a standard unit with smaller static power consumption and larger unit delay is selected, the number of inserted standard units reaches the upper limit, and the hold isolation of some paths in the design still cannot be completely repaired; if the standard unit with larger static power consumption and smaller unit delay is selected, the power consumption of the whole design is particularly large, and especially for the process size of 7nm/5m, the increase of the power consumption is more obvious.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method, a system, a device and a storage medium for repairing the retention time violation, which can not only completely repair the retention time violation, but also control the number of inserted standard cells, reduce the occupied area and reduce the increased power consumption.
In order to achieve the purpose, the invention adopts the following technical scheme:
a hold time violation remedying method comprises the following steps:
finding out all paths with hold time violation in the circuit through time sequence analysis, and acquiring an establishment time margin of a termination point of the paths;
calculating the ratio of the establishing time margin and the holding time violation of the path, and dividing the path into a first path and a second path according to a predefined rule;
iteratively repairing the hold time violation of the first type of path using the first type of process standard cell;
iteratively repairing the hold time violation of the second type of path using a second type of process standard cell;
the voltage threshold of the first type of process is higher than that of the second type of process.
Further, the iteratively repairing the hold time violation of the first type of path using the first type of process standard cell includes:
31) repairing the hold time violation of the first type of path using the first type of process standard cell;
32) calculating the ratio of the establishment time margin and the retention time violation of the remaining unrepaired paths, and repartitioning the path classification according to a predefined rule;
33) and judging whether the first type of path exists in the remaining unrepaired paths, and if so, repeating the step 31).
Further, the iteratively repairing the hold time violation of the second type of path using the second type of process standard cell includes:
41) repairing the hold time violation of the second type of path using the second type of process standard cell;
42) and judging whether an unrepaired path exists or not, and if so, repeating the step 41).
Further, the first type of process is a high threshold voltage process or a standard threshold voltage process.
Further, the second type of process is a low threshold voltage process or an ultra-low threshold voltage process.
Further, the calculating a ratio of the setup time margin and the hold time violation of the path, and dividing the path into a first type of path and a second type of path according to a predefined rule includes:
when the absolute value of the ratio of the setup time margin and the hold time violation of the path is greater than 1.5 and less than 3, and the setup time margin is greater than 15ps, the path is a second type of path, otherwise, the path is a first type of path.
Further, the timing analysis employs the Prime Time tool.
The invention also provides a hold time violation repairing system, which comprises:
the system comprises a violation path acquisition module, a time sequence analysis module and a time sequence analysis module, wherein the violation path acquisition module is used for finding out all paths with retention time violations in a circuit through time sequence analysis and acquiring an establishment time margin of a termination point of the paths;
the path classification module is used for calculating the ratio of the establishment time margin and the holding time violation of the path, and classifying the path into a first path and a second path according to a predefined rule;
the first-class path repairing module is used for iteratively repairing the retention time violation of the first-class path by using the first-class process standard unit;
the second-class path repairing module is used for iteratively repairing the retention time violation of the second-class path by using a second-class process standard unit;
the voltage threshold of the first type of process is higher than that of the second type of process.
The invention also provides a device for maintaining time violation recovery, which comprises:
a memory for storing a computer program;
a processor for implementing the steps of the method of holdover time violation remediation as described above when executing the computer program.
The invention also proposes a storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method of holdover time violation remediation as described above.
The invention has the beneficial effects that:
the invention provides a method, a system, equipment and a storage medium for repairing the retention time violation, and the method, the system, the equipment and the storage medium can control the number of the standard cells inserted in the process of repairing the retention time violation and reduce the number of the standard cells with high static power consumption to the maximum extent by classifying the paths of the retention time violation and reasonably selecting the type of the inserted standard cells, thereby achieving the purpose of reducing the power consumption of the system, optimizing the specific type of the standard cells and achieving the effect of reducing the occupied area. Meanwhile, the invention can also reduce the iteration times of holding time violation repair and improve the efficiency of circuit design.
Drawings
FIG. 1 is a diagram of four timing paths in a practical chip design;
FIG. 2 is a schematic diagram of a timing check path from a first level flip-flop to a second level flip-flop path;
FIG. 3 is a schematic diagram of the clock corresponding to setup and hold checks;
FIG. 4 is a schematic diagram of a first level flip-flop to second level flip-flop timing path;
FIG. 5 is a flowchart illustrating a method for repairing a hold time violation according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a flow of iteratively repairing a hold time violation for a first type of path using a first type of process standard cell in an embodiment of the present invention;
FIG. 7 is a flowchart illustrating an embodiment of iteratively repairing the hold time violation for a second type of path using a second type of process standard cell;
FIG. 8 is a schematic structural diagram of a hold time violation recovery system according to an embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
As shown in fig. 5, an embodiment of the present invention discloses a method for repairing a hold time violation, including:
finding out all paths with hold time violation in the circuit through time sequence analysis, and acquiring an establishment time margin of a termination point of the paths;
calculating the ratio of the establishing time margin and the holding time violation of the path, and dividing the path into a first path and a second path according to a predefined rule;
iteratively repairing the hold time violation of the first type of path using the first type of process standard cell;
iteratively repairing the hold time violation of the second type of path using a second type of process standard cell;
the voltage threshold of the first type of process is higher than that of the second type of process.
Specifically, the Time sequence analysis is performed by using a Prime Time tool, all paths (paths) having hold Time violation (hold visibility) are found, and setup Time margins (setup margin) on termination points (endpoints) of the paths are obtained by using the Prime Time.
The predefined rule needs to be obtained by analyzing a process library of a chip manufacturer, and a suitable interval demarcation point for establishing a time margin and maintaining a time violation ratio is selected, so that the working frequency of the whole chip is not influenced, and the power consumption of the chip is controlled to be the lowest. In the embodiment of the invention, a path which is repaired by using a first-class process standard unit is defined as a first-class path, and the first-class process is a high threshold voltage process or a standard threshold voltage process (HVT/SVT); the paths that are specified for repair using the second type of process standard cells are the second type of paths, which are either low threshold voltage processes or ultra low threshold voltage processes (LVT/ULVT).
Table 1 lists the delay of standard cells under a certain process library at different threshold voltages and different process corners. The ratio of standard cell ss corn to ff corn delay for both HVT and SVT is greater than 3, while the ratio of standard cell ss corn to ff corn delay for LVT is around 2, the ratio of ULVT will be smaller, typically between 1.5 and 2. That is, if the retention time violations are repaired using the standard cells in the table below, 3.33ps of setup time margin would be consumed each time a 1ps retention time violation is repaired using HVT, while only 2.06ps of setup time margin would be consumed using LVT. Assuming that a path exists, the hold time violation is 100ps, the setup time margin is 250ps, and the standard cells using HVT and SVT cannot completely repair the hold time violation on the path, which requires LVT/ULVT.
TABLE 1 delay of standard cells under certain process library at different threshold voltages and different process corners
Figure BDA0002702132570000091
Based on the above analysis, the path with the absolute value of the ratio of the setup time margin to the hold time violation larger than 1.5 and smaller than 3 is selected as the second type of path using LVT/ULVT repair, and the setup time margin on the path is also required to be larger than 15 ps. The other paths to be repaired are the first type paths to be repaired by using HVT/SVT.
After the hold time violation path classification is completed, iteratively repairing the first-class path by using a time-series repair tool or by writing a script, as shown in fig. 6, includes:
31) repairing the hold time violation of the first type of path using the first type of process standard cell; at this time, the LVT/ULVT unit is not needed, and any HVT/SVT unit should not be inserted into the second type path, otherwise the retention time of this part of the path cannot be repaired to be clean.
32) Calculating the ratio of the establishment time margin and the retention time violation of the remaining unrepaired paths, and repartitioning the path classification according to a predefined rule; this step is used to repartition path type changes due to design reasons.
33) And judging whether the first type of path exists in the remaining unrepaired paths, and if so, repeating the step 31).
After completing the repair of the first type of path, using a time-series repair tool or writing a script to perform iterative repair on the second type of path, as shown in fig. 7, the method includes:
41) the hold time violations of the second type of paths are repaired using the second type of process standard cells.
42) And judging whether an unrepaired path exists or not, and if so, repeating the step 41).
As shown in fig. 8, an embodiment of the present invention further provides a hold time violation repairing system, including:
the system comprises a violation path acquisition module, a time sequence analysis module and a time sequence analysis module, wherein the violation path acquisition module is used for finding out all paths with retention time violations in a circuit through time sequence analysis and acquiring an establishment time margin of a termination point of the paths;
the path classification module is used for calculating the ratio of the establishment time margin and the holding time violation of the path, and classifying the path into a first path and a second path according to a predefined rule;
the first-class path repairing module is used for iteratively repairing the retention time violation of the first-class path by using the first-class process standard unit;
the second-class path repairing module is used for iteratively repairing the retention time violation of the second-class path by using a second-class process standard unit;
the voltage threshold of the first type of process is higher than that of the second type of process.
The embodiment of the invention also provides equipment for maintaining time violation repair, which comprises the following steps:
a memory for storing a computer program;
a processor for implementing the steps of the method of holdover time violation remediation as described above when executing the computer program.
An embodiment of the present invention further provides a storage medium, where a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of the method for recovering the retention time violation as described above are implemented.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, the scope of the present invention is not limited thereto. Various modifications and alterations will occur to those skilled in the art based on the foregoing description. And are neither required nor exhaustive of all embodiments. On the basis of the technical scheme of the invention, various modifications or changes which can be made by a person skilled in the art without creative efforts are still within the protection scope of the invention.

Claims (10)

1. A hold time violation recovery method is characterized by comprising the following steps:
finding out all paths with hold time violation in the circuit through time sequence analysis, and acquiring an establishment time margin of a termination point of the paths;
calculating the ratio of the establishing time margin and the holding time violation of the path, and dividing the path into a first path and a second path according to a predefined rule;
iteratively repairing the hold time violation of the first type of path using the first type of process standard cell;
iteratively repairing the hold time violation of the second type of path using a second type of process standard cell;
the voltage threshold of the first type of process is higher than that of the second type of process.
2. The hold time violation recovery method of claim 1, wherein iteratively recovering the hold time violation for the first type of path using the first type of process standard cell comprises:
31) repairing the hold time violation of the first type of path using the first type of process standard cell;
32) calculating the ratio of the establishment time margin and the retention time violation of the remaining unrepaired paths, and repartitioning the path classification according to a predefined rule;
33) and judging whether the first type of path exists in the remaining unrepaired paths, and if so, repeating the step 31).
3. The hold time violation recovery method of claim 1, wherein iteratively recovering the hold time violation for the second type of path using the second type of process standard cell comprises:
41) repairing the hold time violation of the second type of path using the second type of process standard cell;
42) and judging whether an unrepaired path exists or not, and if so, repeating the step 41).
4. The hold-time violation recovery method of claim 1, wherein said first type of process is a high threshold voltage process or a standard threshold voltage process.
5. The hold-time violation remediation method of claim 1, wherein the second type of process is a low threshold voltage process or an ultra-low threshold voltage process.
6. The holdover time violation recovery method of claim 1, wherein said calculating a ratio of a setup time margin and a holdover time violation for a path, and classifying the path into a first type of path and a second type of path according to a predefined rule comprises:
when the absolute value of the ratio of the setup time margin and the hold time violation of the path is greater than 1.5 and less than 3, and the setup time margin is greater than 15ps, the path is a second type of path, otherwise, the path is a first type of path.
7. The hold Time violation recovery method of claim 1, wherein the timing analysis employs a Prime Time tool.
8. A hold time violation remediation system, comprising:
the system comprises a violation path acquisition module, a time sequence analysis module and a time sequence analysis module, wherein the violation path acquisition module is used for finding out all paths with retention time violations in a circuit through time sequence analysis and acquiring an establishment time margin of a termination point of the paths;
the path classification module is used for calculating the ratio of the establishment time margin and the holding time violation of the path, and classifying the path into a first path and a second path according to a predefined rule;
the first-class path repairing module is used for iteratively repairing the retention time violation of the first-class path by using the first-class process standard unit;
the second-class path repairing module is used for iteratively repairing the retention time violation of the second-class path by using a second-class process standard unit;
the voltage threshold of the first type of process is higher than that of the second type of process.
9. An apparatus for maintaining time violation remediation, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method of holdover time violation remediation of any one of claims 1 to 7 when executing the computer program.
10. A storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method of holdover time violation remediation as claimed in any one of claims 1 to 7.
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