CN112069754B

CN112069754B - Chip design method, system, device and storage medium

Info

Publication number: CN112069754B
Application number: CN202010935355.5A
Authority: CN
Inventors: 王毓千; 晋大师; 姚水音; 梁洪昌; 唐志敏
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-09-08
Filing date: 2020-09-08
Publication date: 2021-08-24
Anticipated expiration: 2040-09-08
Also published as: CN112069754A

Abstract

A chip design method, system, device and storage medium. The chip design method comprises the following steps: extracting a first attribute value of a corresponding register transmission level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist respectively by using an analysis tool; and based on the attribute design information, verifying whether the register transmission level description file is matched with the first netlist according to the logic function description information and the first attribute value of each corresponding register transmission level functional module in the first netlist and the second attribute value of the first netlist functional module. The chip design method can reduce the possibility of increasing errors and bugs in the chip design process, thereby ensuring the stability of the system performance of the chip and improving the reliability.

Description

Chip design method, system, device and storage medium

Technical Field

Embodiments of the present disclosure relate to a chip design method, system, device, and storage medium.

Background

Currently, power consumption has become an increasingly important factor in integrated circuit design. Currently, tool software such as Synopsys is generally adopted in chip design to realize the whole process. In order to realize low Power design, the Synopsys tool inserts some special circuit units required for low Power consumption, such as a level shifter, etc., into a Gate-level Netlist (Gate Netlist) according to a ufp (unified Power format) file. In this case, the accuracy of the detection design is particularly important. A Formal Verification (Formal Verification) method is commonly used in chip design to verify whether the function of the chip design is correct in a Formal proof manner. The form verification method mainly performs consistency comparison of logic forms and functions.

Disclosure of Invention

The embodiment of the disclosure provides a chip design method, a system, equipment and a storage medium. The chip design method can reduce the possibility of increasing errors and bugs in the chip design process, ensure the stability of the system performance of the chip and improve the reliability.

At least one embodiment of the present disclosure provides a chip design method, including: loading a register transmission level description file, and reading logic function description information used for chip design of the register transmission level description file; loading an attribute design file, and reading attribute design information of the attribute design file, which is used for chip design; generating a first netlist by combining a standard cell library according to the logic function description information and the attribute design information by using a logic synthesis tool, wherein the logic function description information defines a plurality of register transmission level functional modules, and the first netlist comprises a plurality of first netlist functional modules which are arranged in one-to-one correspondence with the plurality of register transmission level functional modules; extracting a first attribute value of the register transfer level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist respectively by using an analysis tool; and verifying whether the register transfer level description file is matched with the first netlist according to the logic function description information, the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist functional module based on the attribute design information.

For example, in a chip design method provided in at least one embodiment of the present disclosure, verifying whether the register transfer level description file matches the first netlist includes: comparing the logic function description information with a first attribute value of each corresponding register transfer level function module in the first netlist and a second attribute value of the first netlist function module, when the logic function description information is equal to the first attribute value of each corresponding register transfer level function module in the first netlist and the second attribute value of the first netlist function module, determining that the register transfer level description file is matched with the first netlist, and when the logic function description information is not equal to at least one of the first attribute value of each corresponding register transfer level function module in the first netlist and the second attribute value of the first netlist function module, determining that the register transfer level description file is not matched with the first netlist.

For example, the chip design method provided in at least one embodiment of the present disclosure further includes: and comparing a first attribute value of a register transfer level functional module of an adjacent transfer level of the logic function description information or a second attribute value of a first netlist functional module of an adjacent transfer level of the first netlist based on the attribute design information to determine the correctness of the register transfer level description file or the first netlist.

For example, in a chip design method provided in at least one embodiment of the present disclosure, the first attribute value and the second attribute value respectively include one or more of a voltage value, a timing, a clock frequency, and power consumption.

For example, the chip design method provided in at least one embodiment of the present disclosure further includes: and comparing a first attribute value of the input end of each register transmission level functional module in the logic function description information with a second attribute value of the input end of the corresponding first netlist functional module in the first netlist, and determining that the input end of the register transmission level functional module is matched with the input end of the first netlist functional module when the logic function description information is equal to the attribute values of the input end of each corresponding register transmission level functional module in the first netlist and the input end of the corresponding first netlist functional module.

For example, in a chip design method provided in at least one embodiment of the present disclosure, the register transfer level functional module and the first netlist functional module corresponding to the logic function description information and the first netlist respectively include at least one sub-functional module, and the chip design method further includes: when the input end of the register transfer level functional module is matched with the input end of the first netlist functional module, comparing a first attribute value of the input end and/or the output end of the register transfer level functional module and a sub-functional module of the first netlist functional module in the logic function description information with a second attribute value in the first netlist, and when the first attribute value of the input end and/or the output end of the sub-functional module in the logic function description information is equal to the second attribute value in the first netlist, determining that the register transfer level functional module is matched with the first netlist functional module.

For example, in a chip design method provided in at least one embodiment of the present disclosure, the register transfer stage functional module includes a first functional module, the first functional module includes a first sub-functional module and a second sub-functional module, an output end of the first sub-functional module is connected to an input end of the second sub-functional module, the first netlist functional module includes a second functional module corresponding to the first functional module, the second functional module includes a third sub-functional module and a fourth sub-functional module, and the third sub-functional module and the fourth sub-functional module correspond to the first sub-functional module and the second sub-functional module, respectively, and the chip design method further includes: comparing a first attribute value of the output end of the first sub-function module in the logic function description information with a second attribute value of the output end of the third sub-function module in the first netlist, and comparing a first attribute value of the input end of the second sub-function module in the logic function description information with a second attribute value of the input end of the fourth sub-function module in the first netlist, and determining that the first function module is matched with the second function module when the first attribute value of the output end of the first sub-function module is equal to the second attribute value of the output end of the third sub-function module, and the first attribute value of the input end of the second sub-function module is equal to the second attribute value of the input end of the fourth sub-function module.

For example, the chip design method provided in at least one embodiment of the present disclosure further includes: comparing a first attribute value of an output end of the first sub-function module with a first attribute value of an input end of the second sub-function module in the logic function description information based on the attribute design information, and determining that the design of the first function module in the register transfer level description file is correct when the first attribute value of the output end of the first sub-function module is equal to the first attribute value of the input end of the second sub-function module; or in the first netlist, based on the attribute design information, comparing a second attribute value of the output end of the third sub-function module with a second attribute value of the input end of the fourth sub-function module, and when the second attribute value of the output end of the third sub-function module is equal to the second attribute value of the input end of the fourth sub-function module, determining that the design of the second function module in the first netlist is correct.

For example, in the chip design method provided in at least one embodiment of the present disclosure, the register transfer stage functional module includes a third functional module, the third functional module includes a first data selection module, a fifth sub-functional module, and a sixth sub-functional module, an output end of the first data selection module is connected to an input end of the fifth sub-functional module and an input end of the sixth sub-functional module, the first netlist functional module includes a fourth functional module corresponding to the third functional module, the fourth functional module includes a second data selection module, a seventh sub-functional module, and an eighth sub-functional module, the second data selection module, the seventh sub-functional module, and the eighth sub-functional module correspond to the first data selection module, the fifth sub-functional module, and the sixth sub-functional module, respectively, the chip design method further comprises the following steps: comparing a first attribute value of the input end of the fifth sub-function module in the logic function description information with a second attribute value of the input end of the seventh sub-function module in the first netlist, and comparing a first attribute value of the input end of the sixth sub-function module in the logic function description information with a second attribute value of the input end of the eighth sub-function module in the first netlist, and determining that the third function module is matched with the fourth function module when the first attribute value of the input end of the fifth sub-function module is equal to the second attribute value of the input end of the seventh sub-function module, and the first attribute value of the input end of the sixth sub-function module is equal to the second attribute value of the input end of the eighth sub-function module.

For example, in a chip design method provided in at least one embodiment of the present disclosure, the property design file includes a power consumption design file, and verifying whether the register transfer level description file matches the first netlist includes: reading the power consumption design file to obtain design information of a plurality of power domains, wherein each power domain comprises a voltage value, extracting the voltage values of the corresponding register transmission level functional module and the first netlist functional module from the logic function description information and the first netlist respectively by using a power verification tool, and determining that the register transmission level description file is matched with the first netlist when the logic function description information is equal to the voltage values of the corresponding register transmission level functional module and the first netlist functional module of the first netlist.

For example, in a chip design method provided in at least one embodiment of the present disclosure, the property design file includes a constraint design file, and verifying whether the register transfer level description file matches the first netlist includes: and reading the constraint design file to obtain clock information, wherein the clock information comprises a plurality of clock frequencies, extracting at least one corresponding clock frequency of the register transmission level functional module and the first netlist functional module from the logic function description information and the first netlist respectively by using a time sequence analysis tool, and determining that the register transmission level description file is matched with the first netlist when the logic function description information and the at least one corresponding clock frequency of the register transmission level functional module and the first netlist functional module of the first netlist are equal to each other.

For example, the chip design method provided in at least one embodiment of the present disclosure further includes: loading a test design file, reading test design information for chip testing of the test design file, generating a second netlist according to the first netlist and the test design information based on a test design tool, wherein the second netlist comprises a plurality of second netlist functional modules which are arranged in one-to-one correspondence with the plurality of first netlist functional modules of the first netlist, extracting third attribute values of the plurality of second netlist functional modules from the second netlist by using the analysis tool, and verifying whether the first netlist is matched with the second netlist according to the second attribute values of the first netlist functional modules and the third attribute values of the second netlist functional modules which correspond to the first netlist and the second netlist respectively.

For example, the chip design method provided in at least one embodiment of the present disclosure further includes: and comparing third attribute values of second netlist functional modules of adjacent transmission stages of the second netlist based on the attribute design information to determine correctness of the second netlist.

For example, the chip design method provided in at least one embodiment of the present disclosure further includes: generating a third netlist and a database file for chip manufacturing according to the second netlist by using a physical implementation tool, wherein the third netlist comprises a plurality of third netlist functional modules which are arranged in one-to-one correspondence with the plurality of second netlist functional modules of the second netlist, extracting fourth attribute values of the plurality of third netlist functional modules from the third netlist by using the analysis tool, and verifying whether the third netlist is matched with the second netlist according to the third attribute values of the second netlist functional modules and the fourth attribute values of the third netlist functional modules which correspond to the third netlist and the second netlist.

For example, the chip design method provided in at least one embodiment of the present disclosure further includes: comparing fourth property values of third netlist functional modules of adjacent transmission stages of the third netlist based on the property design information to determine correctness of the third netlist.

At least one embodiment of the present disclosure provides a chip design system, which includes a first file reading unit, a second file reading unit, a first netlist generating unit, an attribute extracting unit, and a matching verification unit. The first file reading unit is configured to load a register transmission level description file and read logic function description information of the register transmission level description file, wherein the logic function description information is used for chip design; the second file reading unit is configured to load an attribute design file and read attribute design information of the attribute design file, which is used for chip design; the first netlist generating unit is configured to generate a first netlist by using a logic synthesis tool according to the logic function description information and the attribute design information in combination with a standard cell library, wherein the logic function description information defines a plurality of register transfer level functional modules, and the first netlist comprises a plurality of first netlist functional modules arranged in one-to-one correspondence with the plurality of register transfer level functional modules; the attribute extraction unit is configured to extract a first attribute value of the corresponding register transfer level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist respectively by using an analysis tool; and the matching verification unit is configured to verify whether the register transfer level description file is matched with the first netlist according to the logic function description information, the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist functional module based on the attribute design information.

For example, in the chip design system provided in at least one embodiment of the present disclosure, the matching verification unit is further configured to compare the logic function description information with a first attribute value of each corresponding register transfer level functional module in the first netlist and a second attribute value of the first netlist functional module, determine that the register transfer level description file and the first netlist match when the logic function description information is equal to the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist functional module, determine that at least one of the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist is not equal to each other when the logic function description information is not equal to at least one of the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist functional module, a mismatch between the register transfer level description file and the first netlist is determined.

For example, the chip design system provided in at least one embodiment of the present disclosure further includes: a correctness determination unit configured to compare a first attribute value of a register transfer level functional module of an adjacent transfer level of the logic function description information or a second attribute value of a first netlist functional module of an adjacent transfer level of the first netlist based on the attribute design information to determine correctness of the register transfer level description file or the first netlist.

For example, in the chip design system provided in at least one embodiment of the present disclosure, the matching verification unit includes a first attribute comparison subunit and a first matching determination subunit, the first attribute comparison subunit is configured to compare a first attribute value of the input terminal of each register transfer stage function module in the logic function description information with a second attribute value of the input terminal of the corresponding first netlist function module in the first netlist, and the first matching determination subunit is configured to determine that the input terminal of the register transfer stage function module matches the input terminal of the first netlist function module when the logic function description information and the attribute value of the input terminal of each corresponding register transfer stage function module in the first netlist and the attribute value of the input terminal of the first netlist function module are equal.

For example, in a chip design system provided in at least one embodiment of the present disclosure, the register transfer level functional module and the first netlist functional module corresponding to the logic function description information and the first netlist respectively include at least one sub-functional module, the matching verification unit further includes an attribute comparison second sub-unit and a matching determination second sub-unit, when the input end of the register transfer level functional module matches the input end of the first netlist functional module, the attribute comparison second sub-unit is configured to compare a first attribute value in the logic function description information of the input end and/or the output end of the register transfer level functional module and the sub-functional module of the first netlist functional module with a second attribute value in the first netlist, and the matching determination second sub-unit is configured to compare a first attribute value in the logic function description information of the input end and/or the output end of the sub-functional module with a second attribute value in the first netlist Is equal to a second attribute value in the first netlist, determining that the register transfer level functional module matches the first netlist functional module.

At least one embodiment of the present disclosure also provides a chip design apparatus, which includes a memory and a processor, wherein the memory stores executable code, and when the executable code is executed by the processor, the processor is caused to perform the chip design method as set forth in any one of the preceding claims.

At least one embodiment of the present disclosure also provides a computer-readable storage medium having stored thereon executable code, which when executed by a processor, causes the processor to perform a chip design method as any one of the preceding.

According to the chip design method, the system, the equipment and the storage medium provided by at least one embodiment of the disclosure, based on the attribute design information, whether the register transmission level description file is matched with the first netlist is verified according to the logic function description information, the first attribute value of each corresponding register transmission level function module in the first netlist and the second attribute value of the first netlist function module, defects existing in each level of description can be found according to the attribute values (for example, register transmission level description, the first netlist and the like) of each level of description, and the attribute of each level of description is equivalent (or the attribute values are equal), so that the possibility of generating errors and bugs in the chip design process is reduced, the stability of the system performance of the chip is ensured, and the reliability is improved. Meanwhile, the chip design method is easy to realize and can be widely applied to electronic design automation tools.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is a flowchart of a chip design method according to at least one embodiment of the disclosure;

fig. 2 is a schematic diagram of a chip implementation process provided in at least one embodiment of the disclosure;

fig. 3 is a flow chart of a chip design method according to at least another embodiment of the present disclosure;

fig. 4 is a flowchart of a chip design method according to at least one further embodiment of the present disclosure;

FIG. 5 is a diagram illustrating a register transfer level functional block and a first netlist functional block according to at least one embodiment of the disclosure;

FIG. 6 is a diagram illustrating a corresponding register transfer level function block and a first netlist function block according to at least one other embodiment of the disclosure;

fig. 7 is a flowchart of a chip design method according to at least one further embodiment of the present disclosure;

fig. 8 is a flow chart of a chip design method according to at least one further embodiment of the present disclosure;

fig. 9A is a schematic diagram of a chip design system according to at least one embodiment of the present disclosure;

fig. 9B is a schematic diagram of a chip design system according to at least another embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of another chip design apparatus provided in at least one embodiment of the present disclosure; and

fig. 11 is a schematic diagram of a storage medium according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

During chip design, the description of Register Transfer Level (RTL) is usually converted into the description of GATE Level (GATE) netlist by a logic synthesis tool (e.g., design compiler). Then, a back-end physical implementation tool (e.g., Place & route (pr) tool) generates a gdsii file using the logic GATE level (GATE) netlist as an input, and the gdsii file is used for chip manufacturing. A Formal Verification (Formal Verification) method is used for verifying whether a Register Transfer Level (RTL) description design is consistent with a GATE level (GATE) netlist and whether the GATE level netlist is consistent with the GATE level netlist. Currently, formal verification methods may be integrated in eda (electronics Design automation) tools that are employed to ensure that each level is logically and functionally equivalent. For example, when a designer modifies a logic GATE level netlist, an OR GATE is wrongly written as a NOR GATE due to a hand error, and the formal verification method can easily find such an error by comparing a Register Transfer Level (RTL) description design with a logic GATE level (GATE) netlist.

The form verification method mainly performs consistency comparison of logic forms and functions, and the process can prove that a design does not have a certain defect, cannot prove that the design does not have the defect, and cannot prove that the design conforms to a certain attribute. That is, the approach of employing formal verification makes the chip design unable to be certified or tested as defect-free because it is impossible to formally specify what is "defect-free". All that can be done is to prove that a system does not have any conceivable drawbacks and has all the attributes that make the design functionally desirable and useful.

However, there is currently no general method available to ensure that the attributes described at each level are equivalent, and evaluation of the equivalence of the attributes described at each level is now based primarily on design evaluation, simulation, and designer experience. The above evaluation process introduces excessive human factors, increases the possibility of errors and bugs, and may cause system performance or reliability problems of the chip, and system failure due to electrical characteristics.

Therefore, in the case where low power chip design is more and more important, a method of checking defects existing in the flow of chip design is required.

At least one embodiment of the present disclosure provides a chip design method. The chip design method comprises the following steps: loading a register transmission level description file, and reading logic function description information used for chip design of the register transmission level description file; loading an attribute design file, and reading attribute design information of the attribute design file, which is used for chip design; generating a first netlist by using a logic synthesis tool according to logic function description information and attribute design information in combination with a standard cell library, wherein the logic function description information defines a plurality of register transmission level functional modules, and the first netlist comprises a plurality of first netlist functional modules which are arranged in one-to-one correspondence with the plurality of register transmission level functional modules; extracting a first attribute value of a corresponding register transmission level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist respectively by using an analysis tool; and based on the attribute design information, verifying whether the register transmission level description file is matched with the first netlist according to the logic function description information and the first attribute value of each corresponding register transmission level functional module in the first netlist and the second attribute value of the first netlist functional module.

In the chip design method provided by the embodiment of the present disclosure, based on the attribute design information, whether the register transfer level description file matches the first netlist is verified according to the logic function description information and the first attribute value of each corresponding register transfer level function module in the first netlist and the second attribute value of the first netlist function module, and according to the attribute values (e.g., register transfer level description, first netlist, etc.) of each level of description, defects existing in each level of description can be found, and it is ensured that the attributes of each level of description are equivalent (or the attribute values are equal), so that the probability of generating errors and bugs is reduced in the chip design process, and further, the stability of the system performance of the chip is ensured and the reliability is improved. Meanwhile, the chip design method is easy to realize and can be widely applied to electronic design automation tools.

Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.

Fig. 1 is a flowchart of a chip design method according to at least one embodiment of the present disclosure. Fig. 2 is a schematic diagram of a chip implementation process according to at least one embodiment of the disclosure.

The chip design method provided by the embodiment of the present disclosure as shown in fig. 1 includes the following steps.

Step S101: and loading the register transmission level description file, and reading the logic function description information of the register transmission level description file for chip design.

For example, in some examples, as shown in fig. 2, in a chip design flow implemented based on a chip design implementation tool (e.g., synopsys tool), the register transfer level description file RTL includes a system (e.g., functional module) model description of the chip design corresponding to a high level language description (e.g., C language or register transfer level description), or logical function description information for the system. Descriptions corresponding to a high-level language of a plurality of functional blocks in a chip design can be acquired from a register transfer level description file RTL. For example, based on a chip design implementation tool, the register transfer level description file RTL is loaded, and the logic function description information corresponding to a plurality of functional modules for chip design of the register transfer level description file RTL is read. The logical function description information includes logical function descriptions of a plurality of functional blocks. For example, a logical function description constrains multiple logical functions to a particular goal to achieve a particular logical function with many attributes.

For example, in some embodiments, the attributes may include one or more of voltage values, timing, clock frequency, power consumption, and the like.

It should be noted that the functional modules in the embodiments of the present disclosure may be understood as various systems, subsystems, and the like in the chip design.

Step S102: and loading the attribute design file, and reading the attribute design information of the attribute design file for chip design.

For example, in some examples, as shown in FIG. 2, in a chip design flow implemented based on a chip design implementation tool (e.g., a Synopsys tool), property design file U1 includes property design information for a chip design. The property design file U1 may define time constraints, Power domains (Power domains), etc. for a plurality of functional modules. For example, the power domains of the plurality of functional modules in the chip design may be obtained from the attribute design information, and each power domain may include a power supply, a ground terminal, an operating voltage value, and the like. Clock information for the plurality of functional modules may also be derived from the attribute design information, the clock information including a plurality of clock frequencies. The plurality of functional modules operate according to the clock frequency given the constraints given by the attribute design file U1. That is, the attribute design file U1 defines attribute values at which a plurality of function modules operate. Even if other circuit units are inserted between the functional modules, the attribute values at the time of operation of the functional modules are unchanged. For example, based on a chip design implementation tool, an attribute design file is loaded, and attribute design information for chip design of the attribute design file is read, so as to perform the next step of the chip design method.

For example, in some embodiments, the attribute design files U1 may include one or more of a power consumption design file, a constraint design file, and the like. The power consumption design file defines a functional rate domain and the constraint design file defines a time constraint.

Step S103: and generating a first netlist by combining the logic function description information and the attribute design information with the standard cell library by using a logic synthesis tool.

For example, in some embodiments, as shown in fig. 2, step S40: the first netlist G1 is generated by parsing the attribute design file U1 and the register transfer level description file RTL using a logic synthesis tool in conjunction with the standard cell library STD. For example, the standard cell library includes standard parameters of standard cells of a chip design (e.g., unit devices constituting respective functional modules). For example, the standard cell libraries used for different types of chips are different. The first netlist G1 generated by the logic synthesis tool (e.g., for Design Compiler tool in Synopsys tool) is accessed by the logic synthesis tool according to the corresponding description of the attribute Design information to/from some special circuit units (e.g., low power consumption) required, such as level shifters, shift circuits, quasi-shifters, level shift diodes, isolation units (serving as voltage clamping and isolation between different voltage domains), holding registers, eco (engineering Changing order) circuits (for modifying or improving the circuit function of the circuit). The first netlist G1 is the next level description file of the register transfer level description file RTL.

For example, in the disclosed embodiment, the standard cell library is, for example, a library for designing a chip using a 7nm process.

For example, in some embodiments, the logic function description information defines a plurality of register transfer level function blocks, and the first netlist includes a plurality of first netlist function blocks arranged in a one-to-one correspondence with the plurality of register transfer level function blocks. Although the first netlist G1 and the register transfer level description file RTL are different levels of description files in the chip design flow, the functional blocks defined in the first netlist G1 and the register transfer level description file RTL are the same and correspond to each other. That is, the first netlist G1 is parsed in a low-level language for the register transfer level description file RTL without changing functional blocks or logic functions therein.

Step S104: and extracting the first attribute value of the corresponding register transfer level functional module and the second attribute value of the first netlist functional module from the logic function description information and the first netlist respectively by using an analysis tool.

For example, in some embodiments, the analysis tool may be integrated into the Synopsys tool. For example, the analysis tools may include one or more of a static timing tool PT (Prime Time tool), a low power Verification tool VCLP (part of Verification continuity platform), and the like. When the attribute design file comprises a power consumption design file, the analysis tool may employ a static timing tool PT to extract a first attribute value of the corresponding register transfer level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist, respectively. When the attribute design file comprises a constraint design file, the analysis tool may employ a low-power verification tool VCLP to extract a first attribute value of the corresponding register transfer level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist, respectively.

For example, in some embodiments, the first and second attribute values each include one or more of voltage values, timing, clock frequency, power consumption, and the like.

Step S105: and based on the attribute design information, verifying whether the register transmission level description file is matched with the first netlist according to the logic function description information and the first attribute value of each corresponding register transmission level functional module in the first netlist and the second attribute value of the first netlist functional module.

For example, as shown in FIG. 2, after the first netlist G1 is generated, in step S10, the first netlist G1 and the register transfer level description file RTL are subjected to property verification to determine whether the register transfer level description file RTL matches the first netlist G1. For example, comparing a first property value of the register transfer level function block with a second property value of the first netlist function block, and determining that the register transfer level description file RTL matches the first netlist G1 when the first property value of the register transfer level function block and the second property value of the first netlist function block are both equal; when at least one of the first property value of the register transfer level functional block and the second property value of the first netlist functional block are not equal, it is determined that the register transfer level description file RTL does not match the first netlist G1.

For example, in some embodiments, as shown in fig. 2, in step S10, it may also be determined whether the design of the first netlist G1 or the register transfer level description file RTL is correct through attribute verification. That is, it is found whether there is a mis-input element or mis-design in the first netlist G1 or the register transfer level description file RTL. An example of step S10 may refer to fig. 3 and the like described below.

For example, in some embodiments, as shown in fig. 2, the chip design method provided in the embodiments of the present disclosure further includes step S50 in fig. 2: and loading a test design file. For example, test design information for chip testing of a test design file is read (e.g., synopsys tool).

For example, the chip design method further includes generating a second netlist G2 from the first netlist G1 and the test design information based on a test design tool. For example, the test design tool may be part of a Synopsys tool. The second netlist G2 includes a plurality of second netlist function modules arranged in a one-to-one correspondence with the plurality of first netlist function modules of the first netlist G1.

For example, as shown in FIG. 2, performing property verification on the first netlist G1 and the second netlist G2 in step S20 further includes determining the correctness of the second netlist G2. For example, the chip design method further includes comparing third attribute values of second netlist functional modules of adjacent transmission stages of the second netlist G2 based on the attribute design information to determine correctness of the second netlist G2. The process of determining the correctness of the second netlist G2 may refer to a method of determining the correctness of the register transfer level description file RTL or the first netlist G1 in the embodiment shown in FIG. 3, which will be described in detail later.

For example, in some embodiments, as shown in FIG. 2, the chip design method further includes generating a third netlist G3 and a database file GDS (i.e., GDSII file) for chip manufacture from the second netlist G2 using a physical implementation tool. The chip design method provided by the embodiment of the present disclosure further includes step S60 in fig. 2: the second netlist G2 is resolved using physical implementation tools. For example, the physical implementation tool is, for example, a Place & route (pr) tool, and may generate the third netlist G3 and a gdsii file using the second netlist G2 as an input, the gdsii file being used for chip manufacturing. The third netlist G3 includes a plurality of third netlist function modules arranged in a one-to-one correspondence with the plurality of second netlist function modules of the second netlist G2.

For example, as shown in FIG. 2, performing property verification on the third netlist G3 and the second netlist G2 in step S30 further includes determining the correctness of the third netlist G3. For example, the chip design method may further compare fourth property values of the third netlist functional modules of adjacent transmission stages of the third netlist G3 based on the property design information to determine the correctness of the third netlist G3. The process of determining the correctness of the third netlist G3 may refer to a method of determining the correctness of the register transfer level description file RTL or the first netlist G1 in the embodiment shown in FIG. 3, which will be described in detail later.

For example, the chip design method further includes extracting a plurality of third attribute values of the second netlist functional module from the second netlist G2 using an analysis tool, and verifying whether the first netlist G1 matches the second netlist G2 according to the second attribute values of the first netlist functional module and the third attribute values of the second netlist functional module corresponding to each of the first netlist G1 and the second netlist G2. For example, as shown in FIG. 2, performing property verification on the first netlist G1 and the second netlist G2 in step S20 includes verifying whether the first netlist G1 matches the second netlist G2. The method of determining whether the first netlist G1 matches the second netlist G2 is the same as the method of verifying the properties of the register transfer level description file RTL and the first netlist G1 in step S10. Reference may be made in particular to the method of determining whether the register transfer level description file RTL matches the first netlist G1 in the embodiment shown in fig. 1-8 as described in detail below. And will not be described in detail herein.

For example, the chip design method further includes extracting a plurality of fourth attribute values of a third netlist functional module from the third netlist G3 by using an analysis tool, and verifying whether the third netlist matches the second netlist according to the third attribute values of the corresponding second netlist functional module of the third netlist G3 and the second netlist G2 and the fourth attribute values of the third netlist functional module. For example, as shown in FIG. 2, performing property verification on the third netlist G3 and the second netlist G2 in step S30 includes verifying whether the third netlist G3 and the second netlist G2 match. The method of determining whether the third netlist G3 and the second netlist G2 match is the same as the method of verifying the properties of the register transfer level description file RTL and the first netlist G1 in step S10. Reference may be made in particular to the method of determining whether the register transfer level description file RTL matches the first netlist G1 in the embodiment shown in fig. 1-8 as described in detail below.

Fig. 3 is a flowchart of a chip design method according to at least another embodiment of the disclosure. The method of verifying whether the register transfer level description file matches the first netlist and the method of determining the correctness of the register transfer level description file or the first netlist are shown in fig. 3. The chip design method provided by the embodiment of the disclosure further includes the following steps S201 to S207 shown in fig. 3.

Step S201: and comparing the first attribute value of each corresponding register transfer level functional module with the second attribute value of the first netlist functional module.

Step S202: and when the first attribute value of the register transfer level functional module and the second attribute value of the first netlist functional module are equal, determining that the register transfer level description file and the first netlist are matched with each other.

Step S203: and when at least one of the first attribute value of the register transfer level functional module and the second attribute value of the first netlist functional module is not equal, determining that the register transfer level description file and the first netlist are not matched with each other.

For example, in some embodiments, the logic function description information is compared to a first attribute value of each corresponding register transfer level functional module in the first netlist and a second attribute value of the first netlist functional module; when the logic function description information is equal to a first attribute value of each corresponding register transmission level functional module in the first netlist and a second attribute value of the first netlist functional module, determining that the register transmission level description file is matched with the first netlist; and when the logic function description information is not equal to at least one of the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist functional module, determining that the register transfer level description file is not matched with the first netlist. When at least one of the first attribute value of the register transmission level functional module and the second attribute value of the first netlist functional module is not equal, it is indicated that there is a mismatch between the register transmission level functional module and the first netlist functional module, and the reason of the mismatch can be found according to the register transmission level functional module and the first netlist functional module where the first attribute value and the second attribute value are not equal, for example, by checking whether the design of the first netlist functional module is inserted into another circuit unit by mistake, and then adjusting the design of the first netlist. According to the method, the attribute values which are equal to each other in the register transmission level description file and the first netlist can be found out, all defects existing in each level of description are found, and the attributes of each level of description are equivalent (or the attribute values are equal), so that the possibility of generating errors and bugs in the chip design process is reduced, the stability of the system performance of the chip is ensured, and the reliability is improved.

Step S204: based on the attribute design information, a first attribute value of a register transfer level functional module of an adjacent transfer level of the logic function description information or a second attribute value of a first netlist functional module of an adjacent transfer level of the first netlist is compared.

Step S205: and when the first attribute values of the register transfer level functional modules of the adjacent transfer levels are equal or the second attribute values of the first netlist functional modules of the adjacent transfer levels of the first netlist are equal, determining that the design of the register transfer level description file or the first netlist is correct.

Step S206: when the first attribute values of the register transfer stage functional modules of the adjacent transfer stages are equal or the second attribute values of the first netlist functional modules of the adjacent transfer stages of the first netlist are not equal, comparing the first attribute values of the register transfer stage functional modules of the adjacent transfer stages or the second attribute values of the first netlist functional modules of the adjacent transfer stages with the attribute values defined in the attribute design information.

Step S207: and when the first attribute value of the register transfer stage functional module of the adjacent transfer stage or the second attribute value of the first netlist functional module of the adjacent transfer stage is not equal to the attribute value defined in the attribute design information, determining that the design of the register transfer stage description file or the first netlist is incorrect.

For example, when a first attribute value of a register transfer stage functional module of an adjacent transfer stage or a second attribute value of a first netlist functional module of an adjacent transfer stage is equal to an attribute value defined in the attribute design information, it is determined that the design of the register transfer stage description file or the first netlist is correct.

For example, in some instances, the attribute-based design information is read, for example, from the attribute design file U1 described in fig. 2. The attribute design information includes attribute values of a plurality of functional blocks (defined as register transfer level functional blocks in register transfer level description file RTL and defined as first netlist functional blocks in first netlist G1). When the first attribute values of the register transmission stage functional modules of the adjacent transmission stages are equal, it is indicated that no other circuit unit exists between the register transmission stage functional modules of the adjacent transmission stages, and no wrong design exists. When the first attribute values of the register transmission level functional modules of the adjacent transmission levels are not equal, it is indicated that other circuit units are arranged between the register transmission level functional modules of the transmission levels, at this time, the first attribute values of the register transmission level functional modules of the adjacent transmission levels are compared with the attribute values of the adjacent transmission level functional modules in the corresponding attribute design information, and if the comparison results are equal, it is indicated that the first attribute values of the register transmission level functional modules of the adjacent transmission levels are correct, and the other circuit units between the register transmission level functional modules of the transmission levels are correctly inserted. That is, the attribute value of the plurality of function modules defined in the attribute design information is a standard value. In the embodiment of the present disclosure, the comparison method of the second attribute value of the first netlist functional module of the adjacent transmission stage is the same as the comparison method of the first attribute value of the register transmission stage functional module of the adjacent transmission stage, and is not described herein again.

For example, in some embodiments, fig. 4 is a flowchart of a chip design method according to at least one further embodiment of the present disclosure. The method in fig. 4 comprises the following steps S301 to S304, which are explained below in connection with fig. 5.

Step S301: and comparing a first attribute value of the input end of each register transfer level functional module in the logic function description information with a second attribute value of the input end of the corresponding first netlist functional module in the first netlist.

Step S302: and when the logic function description information is equal to the attribute values of the input end of each corresponding register transfer level functional module in the first netlist and the input end of the first netlist functional module, determining that the input end of the register transfer level functional module is matched with the input end of the first netlist functional module.

For example, in some embodiments, fig. 5 is a schematic diagram of a corresponding register transfer level functional block and a first netlist functional block provided in at least one embodiment of the disclosure. The upper half of fig. 5 illustrates the register transfer level description file RTL and the lower half of fig. 5 illustrates the first netlist G1. As shown in FIG. 5, the register transfer level description file RTL includes a first functional block 1101 and the first netlist G1 includes a second functional block 1102. The first functional module 1101 and the second functional module 1102 are corresponding functional modules. The first functional module 1101 and the second functional module 1102 both belong to a first power domain a. Since the first function module 1101 and the second function module 1102 both belong to the first power domain a, the first attribute value of the first function module 1101 and the second attribute value of the second function module 1102 obtained by the analysis tool are equal, that is, when viewed from the node corresponding to the input terminal, the first attribute value of the input terminal of the first function module 1101 and the second attribute value of the input terminal of the second function module 1102 are equal. At this point, it may be determined that the input of the first functional module 1101 matches the input of the second functional module 1102. When the first functional module 1101 and the second functional module 1102 further include sub-functional modules, it is further necessary to compare whether the attribute values of the input end and the output end of the sub-functional modules are equivalent to determine whether the first functional module 1101 and the second functional module 1102 are matched.

For example, in some embodiments, the logic function description information and the corresponding register transfer level functional module of the first netlist and the functional module of the first netlist respectively include at least one sub-functional module, and the chip design method provided by the embodiment of the disclosure further includes the following steps in fig. 4.

Step S303: the first attribute values of the inputs and/or outputs of the register transfer level functional module and the sub-functional modules of the first netlist functional module in the logic function description information are compared with the second attribute values in the first netlist.

Step S304: when the first attribute value in the logic function description information of the input end and/or the output end of the sub-function module is equal to the second attribute value in the first netlist, the register transfer level function module is determined to be matched with the first netlist function module.

For example, in some embodiments, as shown in FIG. 5. In the register transfer level description file RTL, the first functional module 1101 further includes a first sub-functional module 201 and a second sub-functional module 202. The first sub-function module 201 belongs to a second power domain B and the second sub-function module 202 belongs to the second power domain B. The output of the first sub-function module 201 is connected to the input of the second sub-function module 202, for example via a logic network L1. In the embodiments of the present disclosure, the logic network is, for example, a logic circuit or a logic connection relationship. In first netlist G1, second functional module 1102 further includes third sub-functional module 203 and fourth sub-functional module 204. The third sub-function module 203 belongs to the second power domain B and the fourth sub-function module 204 belongs to the second power domain B. The output of the third sub-function 203 is connected to the input of the fourth sub-function 204, for example via the logic network L2 and the logic network L3. The third sub-function module 203 and the fourth sub-function module 204 correspond to the first sub-function module 201 and the second sub-function module 202, respectively.

For example, as shown in fig. 5, the first sub-function module 201 may include a first sub-logic circuit 301. For example, the first sub-logic circuit 301 is a flip-flop. The output pin 401 of the first sub-logic circuit 301 is the output terminal of the first sub-functional module 201. The second sub-function module 202 may include a second sub-logic circuit 302. For example, the second sub-logic 302 is a flip-flop. The input pin 402 of the second sub-logic circuit 302 is an input terminal of the second sub-functional block 202. The third sub-function module 203 may comprise a third sub-logic circuit 303. For example, the third sub-logic circuit 303 is a flip-flop. The output pin 403 of the third sub-logic circuit 303 is the output of the third sub-functional module 203. The fourth sub-function module 204 may include a fourth sub-logic 304. For example, the fourth sub-logic circuit 304 is a flip-flop. The input pin 404 of the fourth sub-logic 304 is the input of the fourth sub-function block 204.

For example, as shown in FIG. 5, in the first netlist G1, an ECO circuit 305 is further inserted between the third sub-function block 203 and the fourth sub-function block 204. The input 405 of the ECO circuit 305 is connected to the output 403 of the third sub-function block 203 (i.e., the output pin 403 of the third sub-logic circuit 303) via a logic network L2, and the output 406 of the ECO circuit 305 is connected to the input 404 of the fourth sub-function block 204 (i.e., the input pin 404 of the fourth sub-logic circuit 304) via a logic network L3. The ECO circuit 305 inputs the first power domain a.

It should be noted that, in the embodiment of the present disclosure, an ECO circuit 305 is further inserted between the third sub-function module 203 and the fourth sub-function module 204 for an example, and other circuits may also be inserted between the third sub-function module 203 and the fourth sub-function module 204, which is not limited to this.

For example, as shown in FIG. 5, comparing the first attribute value at the output 401 of the first sub-function module 201 with the second attribute value at the output 403 of the third sub-function module 203, since the first sub-logic 301 and the third sub-logic 303 both belong to the second power domain B, the first attribute value at the output 401 (i.e., the output pin 401) and the second attribute value at the output 403 extracted by the analysis tool are equal. Comparing the first attribute value at the input 402 of the second sub-function module 202 with the second attribute value at the input 404 of the fourth sub-function module 204, the analysis tool extracts that the first attribute value at the input 402 (i.e. the input pin 402) of the second sub-function module 202 belongs to the second power domain B, since the second sub-logic 302 belongs to the second power domain B. Since the input 404 (input pin 404) of the fourth sub-function module 204 is connected to the output 406 of the ECO circuit 305, the second property value of the input 404 is equal to the second property value of the output 406, and the ECO circuit 305 belongs to the first power domain a, the second property value of the input 404 (input pin 404) of the fourth sub-function module 204 extracted by the analysis tool belongs to the first power domain a. Therefore, the first attribute value at the input 402 of the second sub-function module 202 (i.e. the input pin 402) is not equal to the second attribute value at the input 404 of the fourth sub-function module 204 (i.e. the input pin 404). At this time, the first functional module 1101 does not match the second functional module 1102.

For example, as shown in fig. 5, the first netlist G1 erroneously inserts the ECO circuit 305 between the third sub-function module 203 and the fourth sub-function module 204, so that the first function module 1101 does not match the second function module 1102, if the erroneously inserted ECO circuit 305 is removed, then the property verification is performed on the first function module 1101 and the second function module 1102, and the first property value of the input terminal 402 (i.e., the input terminal 402) of the second sub-function module 202 is equal to the second property value of the input terminal 404 (the input terminal 404) of the fourth sub-function module 204 and both belong to the second power domain B, so that the first function module 1101 matches the second function module 1102.

For example, in some embodiments, as shown in fig. 5, the chip design method provided in the embodiments of the present disclosure further includes comparing, in the logic function description information, a first attribute value of the output 401 of the first sub-function module 201 with a first attribute value of the input 402 of the second sub-function module 202 based on the attribute design information, and determining that the design of the first function module 1101 in the register transfer level description file RTL is correct when the first attribute value of the output 401 of the first sub-function module 201 is equal to the first attribute value of the input 402 of the second sub-function module 202. In first netlist G1, the second property values at output 403 of third sub-function module 203 are compared with the second property values at input 404 of fourth sub-function module 204 based on the property design information, and when the second property values at output 403 of third sub-function module 203 and the second property values at input 404 of fourth sub-function module 204 are equal, it is determined that second function module 1102 is correctly designed in first netlist G1.

For example, as shown in fig. 5, according to the above analysis, in the logical function description information, the first attribute value of the output terminal 401 of the first sub-function module 201 and the first attribute value of the input terminal 402 of the second sub-function module 202 both belong to the second power domain B and are equal, so the design of the first function module 1101 in the register transfer level description file RTL is correct. In the first netlist G1, the second property value of the output 403 of the third sub-function module 203 belongs to the second power domain B, the input 404 of the fourth sub-function module 204 belongs to the first power domain a, the second property value of the output 403 of the third sub-function module 203 is not equal to the second property value of the input 404 of the fourth sub-function module 204, and the second function module 1102 is incorrectly designed in the first netlist G1.

For example, in some embodiments, fig. 6 is a schematic diagram of a corresponding register transfer level functional block and a first netlist functional block provided in at least another embodiment of the present disclosure. The upper half of fig. 6 illustrates the register transfer level description file RTL, and the lower half of fig. 6 illustrates the first netlist G1.

As shown in FIG. 6, the register transfer stage function module 2101 (e.g., the top-level module defined by the register transfer stage description) includes a third function module 2201, and the third function module 2201 includes a first data selection module 2307, a fifth sub-function module 2306, and a sixth sub-function module 2305. An output of the first data selection module 2307 is connected to an input of the fifth sub-function module 2306 and to an input of the sixth sub-function module 2305. The first netlist function module 2102 includes a fourth function module 2202 corresponding to the third function module 2201, which includes a second data selection module 2300, a seventh sub-function module 2304, and an eighth sub-function module 2305. An output of the second data selection module 2300 is connected to an input of the seventh sub-function module 2304 and to an input of the eighth sub-function module 2305. The second data selection module 2300, the seventh sub-function module 2304 and the eighth sub-function module 2305 correspond to the first data selection module 2307, the fifth sub-function module 2306 and the sixth sub-function module 2305, respectively.

For example, as shown in fig. 6, the third functional module 2201 comprises a first input pin 2208 and a second input pin 2207, the first input pin 2208 receives a clock CLK1, and the second input pin 207 receives a clock CLK 2. The frequency domain in which the third functional module 2201 is located includes a frequency CLK1 and a frequency CLK 2. Similarly, the frequency domain in which the first data selection module 2307, the fifth sub-function module 2306 and the sixth sub-function module 2305 of the third function module 2201 are located also includes a frequency CLK1 and a frequency CLK 2. The first input pin 2208 of the third functional module 2201 has an attribute value of frequency CLK1 and the second input pin 2207 of the third functional module 2201 has an attribute value of frequency CLK 2. The first input pin 2411 and the second input pin 2409 of the first data selecting module 2307 are respectively connected to the first input pin 2208 and the second input pin 2207 of the third functional module 2201, and the frequency domain in which the output pin 2410 of the first data selecting module 2307 (i.e., the output end of the first data selecting module 2307) is located includes a frequency CLK1 and a frequency CLK 2. The output 2410 of the first data selection module 2307 (i.e., the output pin 2410 of the first data selection module 2307) has attribute values of frequency CLK1 and frequency CLK 2. The output pin 2410 of the first data selection module 2307 is connected to the input pin 2413 of the fifth sub-function module 2306 (i.e., the input of the fifth sub-function module 2306) and the input pin 2412 of the sixth sub-function module 2305 (i.e., the input of the sixth sub-function module 2305). The attribute values at the input 2413 of the fifth sub-function module 2306 are a frequency CLK1 and a frequency CLK2, and the attribute values at the input 2412 of the sixth sub-function module 2305 are a frequency CLK1 and a frequency CLK 2.

For example, continuing with fig. 6, the fourth functional module 2202 includes a first input pin 2206, a second input pin 2205, a third input pin 2204, and a fourth input pin 2203, the first input pin 2206 and the third input pin 2204 receiving a frequency CLK1, the second input pin 2205 and the fourth input pin 2203 receiving a frequency CLK 2. The frequency domain in which the fourth functional module 2202 resides includes a frequency CLK1 and a frequency CLK 2. Similarly, the frequency domain in which the second data selection module 2300, the seventh sub-function module 2304 and the eighth sub-function module 2303 of the fourth function module 2202 also includes a frequency CLK1 and a frequency CLK 2. The attribute values of the first input pin 2206 and the third input pin 2204 of the fourth functional module 2202 are the frequency CLK1, and the attribute values of the second input pin 2205 and the fourth input pin 2203 of the fourth functional module 2202 are the frequency CLK 2. The first input pin 2408, the second input pin 2406, the third input pin 2405 and the fourth input pin 2403 of the second data selection module 2300 are respectively connected with the first input pin 2206, the second input pin 2205, the third input pin 2204 and the fourth input pin 2203 of the fourth functional module 2202, and the frequency domain where the first output pin 2407 and the second output pin 2404 (i.e. the output end of the second data selection module 2300) of the second data selection module 2300 are located includes a frequency CLK1 and a frequency CLK 2. The attribute values of the output terminals (i.e., the first output pin 2407 and the second output pin 2404) of the second data selecting module 2300 are a frequency CLK1 and a frequency CLK 2. For example, in an example, the second data selection module 2300 includes two data selection modules, respectively a data selection module 2302 and a data selection module 2301. Data selection module 2302 includes a first input pin 2408, a second input pin 2406 and a first output pin 2407, and data selection module 2301 includes a third input pin 2405, a fourth input pin 2403 and a second output pin 2404.

For example, in other examples, the second data selection module 2300 may adopt a structure corresponding to the first data selection module 2307, that is, include one data selection module, in which case the second data selection module 2300 includes two input pins and one output pin. The embodiment of the present disclosure is not limited to the specific structure of the second data selecting module 2300.

As further shown in fig. 6, the first output pin 2407 of the second data selection module 2300 is connected to the input pin 2402 of the seventh sub-function module 2304 (i.e., the input terminal of the seventh sub-function module 2304), and the second output pin 2404 of the second data selection module 2300 is connected to the input pin 2401 of the eighth sub-function module 2303 (i.e., the input terminal of the eighth sub-function module 2303). The attribute values at the input 2402 of the seventh sub-function module 2304 are a frequency CLK1 and a frequency CLK2, and the attribute values at the input 2403 of the eighth sub-function module 2303 are a frequency CLK1 and a frequency CLK 2.

For example, in some embodiments, as shown in FIG. 6, based on the above analysis of the attribute values of the various functional modules in FIG. 6, the first attribute value of the input 2413 of the fifth sub-functional module 2306 (i.e., the input pin 2413 of the fifth sub-functional module 2306) in the logical function description information is compared with the second attribute value of the input 2402 of the seventh sub-functional module 2304 (i.e., the input pin 2402 of the seventh sub-functional module 2304) in the first netlist G1, and the first attribute value of the input 2412 of the sixth sub-functional module 2305 (i.e., the input pin 2412 of the sixth sub-functional module 2305) in the logical function description information is compared with the second attribute value of the input 2401 of the eighth sub-functional module 2303 (i.e., the input pin 2401 of the eighth sub-functional module 2303) in the first netlist G1. The first attribute values (e.g., frequencies CLK1 and CLK2) at the input 2412 of the sixth sub-function module 2305 are equal to the second attribute values (e.g., frequencies CLK1 and CLK2) at the input 2401 of the eighth sub-function module 2303, the first attribute values (e.g., frequencies CLK1 and CLK2) at the input 2413 of the fifth sub-function module 2306 are equal to the second attribute values (e.g., frequencies CLK1 and CLK2) at the input 2402 of the seventh sub-function module 2304, and thus the third function module 2201 matches the fourth function module 2202.

For example, in some embodiments, fig. 7 is a flowchart of a chip design method according to at least one further embodiment of the disclosure. The attribute design files include Power consumption design files that define functional rate domains, for example, Power consumption design files based on technical designs of the IEEE1801 standard, Unified Power Format. The chip design method provided by the implementation of the present disclosure further includes the following steps S401 to S403, which are described below with reference to, for example, fig. 5.

Step S401: the power consumption design file is read to obtain design information for a plurality of power domains, each of the plurality of power domains including a voltage value.

For example, in some embodiments, as shown in FIG. 5, the first attribute value of the input 402 (i.e., the input pin 402) of the second sub-function module 202 is the voltage value of the second power domain B, and the second attribute value of the input 404 (the input pin 404) of the fourth sub-function module 204 is the voltage value of the first power domain A.

Step S402: and extracting the voltage values of the corresponding register transmission level functional module and the first netlist functional module from the logic function description information and the first netlist respectively by using a power verification tool.

For example, in some embodiments, the power verification tool is, for example, a static timing tool PT. As shown in fig. 5, the voltage value of the input terminal 402 (i.e. the input pin 402) of the second sub-function module 202 and the voltage value of the input terminal 404 (i.e. the input pin 404) of the fourth sub-function module 204 can be extracted from the logic function description information and the first netlist by using the power verification tool.

Step S403: and when the logic function description information and the voltage values of the corresponding register transfer level functional module and the first netlist functional module of the first netlist are equal, determining that the register transfer level description file is matched with the first netlist.

For example, in some embodiments, as shown in fig. 5, since the first property value of the input 402 (i.e., the input pin 402) of the second sub-function module 202 is the voltage value of the second power domain B, and the second property value of the input 404 (the input pin 404) of the fourth sub-function module 204 is the voltage value of the first power domain a, the first property value of the second sub-function module 202 is not equal to the second property value of the fourth sub-function module 204, there is no match between the register transfer level description file and the first netlist.

For example, in some embodiments, fig. 8 is a flowchart of a chip design method according to at least one further embodiment of the disclosure. The property Design files include constraint Design files (SDC) that define time Constraints, such as Constraints on timing, area, and power consumption of the circuit. The chip design method provided by the implementation of the present disclosure further includes the following steps S501 to S503, which will be described below with reference to, for example, fig. 6.

Step S501: reading the constraint design file to obtain clock information, wherein the clock information comprises a plurality of clock frequencies.

For example, in some embodiments, as shown in fig. 6, the frequency domain in which the third functional module 2201 is located includes a frequency CLK1 and a frequency CLK 2. The frequency domain in which the fourth functional module 2202 resides includes a frequency CLK1 and a frequency CLK 2.

Step S502: and extracting at least one clock frequency of the corresponding register transfer level functional module and the first netlist functional module from the logic function description information and the first netlist respectively by using a timing analysis tool.

For example, in some embodiments, as shown in FIG. 6, the timing analysis tool is a low power consumption verification tool VCLP. The first attribute values of the input 2412 of the sixth sub-function module 2305 are frequency CLK1 and frequency CLK2, the second attribute values of the input 2401 of the eighth sub-function module 2303 are frequency CLK1 and frequency CLK2, the first attribute values of the input 2413 of the fifth sub-function module 2306 are frequency CLK1 and frequency CLK2, and the second attribute values of the input 2402 of the seventh sub-function module 2304 are frequency CLK1 and frequency CLK 2.

Step S503: and when the logic function description information corresponds to the corresponding register transfer level functional module of the first netlist and at least one clock frequency of the first netlist functional module, determining that the register transfer level description file is matched with the first netlist.

For example, in some embodiments, as shown in FIG. 6, the first attribute values (e.g., frequencies CLK1 and CLK2) at the input 2412 of the sixth sub-function module 2305 are equal to the second attribute values (e.g., frequencies CLK1 and CLK2) at the input 2401 of the eighth sub-function module 2303, the first attribute values (e.g., frequencies CLK1 and CLK2) at the input 2413 of the fifth sub-function module 2306 are equal to the second attribute values (e.g., frequencies CLK1 and CLK2) at the input 2402 of the seventh sub-function module 2304, and thus the third function module 2201 is matched to the fourth function module 2202.

For example, at least one embodiment of the present disclosure further provides a chip design system. Fig. 9A is a schematic diagram of a chip design system according to at least one embodiment of the present disclosure. Fig. 9B is a schematic diagram of a chip design system according to at least another embodiment of the present disclosure. As shown in fig. 9A, the chip design system 500 is used for implementing the chip design method provided by the embodiments of the present disclosure.

For example, in some embodiments, as shown in fig. 9A, chip design system 500 includes a first file reading unit 510, a second file reading unit 520, a first netlist generation unit 530, an attribute extraction unit 540, and a match verification unit 550. The first file reading unit 510 is configured to load the register transfer level description file and read the logic function description information for the chip design of the register transfer level description file. For example, as shown in fig. 2, in the chip design flow, the register transfer level description file RTL includes a system (e.g., function module) model description of the chip design corresponding to a high-level language description (e.g., C language or register transfer level description) or logic function description information for the system. For example, the first file reading unit 510 is implemented as a functional module in a chip design implementation tool (e.g., synopsys tool), and loads the register transfer level description file RTL, and reads logical function description information corresponding to a plurality of functional modules for chip design of the register transfer level description file RTL. The logical function description information includes logical function descriptions of a plurality of functional blocks.

For example, in some embodiments, as shown in fig. 9A, the second file reading unit 520 is configured to load the property design file and read the property design information for chip design of the property design file. For example, as shown in fig. 2, the property design file U1 includes property design information for chip design. The property design file U1 may define time constraints, Power domains (Power domains), etc. for a plurality of functional modules. The attribute design file U1 defines attribute values at which a plurality of function modules operate. For example, the second file reading unit 520 may be implemented as a functional module in a chip design implementation tool, and load an attribute design file, and read attribute design information of the attribute design file for chip design to perform the next step of the chip design method.

For example, in some embodiments, as shown in FIG. 9A, the first netlist generation unit 530 is configured to generate a first netlist from the logic function description information and the property design information in combination with a standard cell library using a logic synthesis tool. For example, as shown in FIG. 2, the first netlist generation unit 530 is configured to generate the first netlist G1 using a logic synthesis tool to parse the attribute design file U1 and the register transfer level description file RTL in conjunction with the standard cell library STD. The first netlist G1 is the next level description file of the register transfer level description file RTL. For example, the logic function description information defines a plurality of register transfer level function blocks, and the first netlist G1 includes a plurality of first netlist function blocks arranged in one-to-one correspondence with the plurality of register transfer level function blocks.

For example, in some embodiments, as shown in FIG. 9A, the attribute extraction unit 540 is configured to extract a first attribute value of the corresponding register transfer level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist, respectively, using an analysis tool. For example, in some embodiments, the analysis tool may be integrated into the Synopsys tool. For example, the analysis tools may include one or more of a static timing tool PT (Prime Time tool), a low power Verification tool VCLP (part of Verification continuity platform), and the like. For example, the attribute extraction unit 540 may invoke an analysis tool to extract a first attribute value of the corresponding register transfer level function block and a second attribute value of the first netlist function block from the logic function description information and the first netlist, respectively.

For example, in some embodiments, as shown in fig. 9A, the matching verification unit 550 is configured to verify whether the register transfer level description file matches the first netlist based on the logic function description information and the first attribute value of each corresponding register transfer level function block in the first netlist and the second attribute value of the first netlist function block based on the attribute design information. For example, as shown in FIG. 2, after the first netlist G1 is generated, the matching verification unit 550 is configured to perform property verification on the first netlist G1 and the register transfer level description file RTL to determine whether the register transfer level description file RTL matches the first netlist G1. For example, comparing a first property value of the register transfer level function block with a second property value of the first netlist function block, and determining that the register transfer level description file RTL matches the first netlist G1 when the first property value of the register transfer level function block and the second property value of the first netlist function block are both equal; when at least one of the first property value of the register transfer level functional block and the second property value of the first netlist functional block are not equal, it is determined that the register transfer level description file RTL does not match the first netlist G1.

In the chip design system provided in the embodiment of the present disclosure, the matching verification unit is configured to verify whether the register transfer level description file matches the first netlist according to the logic function description information and the first attribute value of each corresponding register transfer level function module in the first netlist and the second attribute value of the first netlist function module based on the attribute design information, and may find a defect existing in each level of description according to the attribute value (e.g., register transfer level description, first netlist, etc.) of each level of description, and ensure that the attribute of each level of description is equivalent (or the attribute values are equal), thereby reducing the possibility of generating errors and bugs in the chip design process, further ensuring the stability of the system performance of the chip and improving the reliability. Meanwhile, the chip design method is easy to realize and can be widely applied to electronic design automation tools.

For example, in some embodiments, as shown in fig. 9A, the matching verification unit 550 is further configured to compare the logic function description information with the first attribute value of each corresponding register transfer level function module in the first netlist and the second attribute value of the first netlist function module, determine that the register transfer level description file matches the first netlist when the logic function description information is equal to the first attribute value of each corresponding register transfer level function module in the first netlist and the second attribute value of the first netlist function module, and determine that there is a mismatch between the register transfer level description file and the first netlist when the logic function description information is not equal to at least one of the first attribute value of each corresponding register transfer level function module in the first netlist and the second attribute value of the first netlist function module. For example, when at least one of the first attribute value of the register transfer level functional module and the second attribute value of the first netlist functional module is not equal, it indicates that there is a mismatch between the register transfer level functional module and the first netlist functional module, and the reason of the mismatch can be found according to the register transfer level functional module and the first netlist functional module where the first attribute value and the second attribute value are not equal, for example, by checking whether the design of the first netlist functional module is erroneously inserted into another circuit unit, and then adjusting the design of the first netlist. According to the method, the attribute values which are equal to each other in the register transmission level description file and the first netlist can be found out, all defects existing in each level of description are found, and the attributes of each level of description are equivalent (or the attribute values are equal), so that the possibility of generating errors and bugs in the chip design process is reduced, the stability of the system performance of the chip is ensured, and the reliability is improved.

For example, in some embodiments, as shown in fig. 9A, chip design system 500 also includes a correctness determination unit 560. The correctness determination unit 560 is configured to compare a first attribute value of the register transfer level functional module of the adjacent transfer level of the logic function description information or a second attribute value of the first netlist functional module of the adjacent transfer level of the first netlist based on the attribute design information to determine the correctness of the register transfer level description file or the first netlist. For example, the correctness determination unit 560 determines that the design of the register transfer level description file or the first netlist is correct when the first attribute value of the register transfer level function module of the adjacent transfer level or the second attribute value of the first netlist function module of the adjacent transfer level is equal to the attribute value defined in the attribute design information, according to the comparison result of the comparison of the first attribute value of the register transfer level function module of the adjacent transfer level of the logic function description information or the second attribute value of the first netlist function module of the adjacent transfer level of the first netlist. Otherwise, the correctness determination unit 560 compares the first attribute value of the register transfer level functional module of the adjacent transfer level or the second attribute value of the first netlist functional module of the adjacent transfer level with the attribute value defined in the attribute design information, determines that the design of the register transfer level description file or the first netlist is correct if the comparison results are equal, and determines that the design of the register transfer level description file or the first netlist is incorrect if the comparison results are not equal.

For example, in some embodiments, as shown in FIG. 9B, the match verification unit 550 includes an attribute comparison first sub-unit 551 and a match determination first sub-unit 553. The attribute comparison first subunit 551 is configured to compare a first attribute value of the input of each register transfer level functional module in the logic function description information with a second attribute value of the input of the corresponding first netlist functional module in the first netlist. The first sub-unit 553 for determining a match of the input of the register transfer level function block with the input of the first netlist function block is configured to determine when the logic function description information and the property values of the input of the first netlist function block and the input of each corresponding register transfer level function block in the first netlist are equal. For example, as shown in FIG. 5, the register transfer level description file RTL includes a first functional block 1101, and the first netlist G1 includes a second functional block 1102. The first functional module 1101 and the second functional module 1102 are corresponding functional modules. The first functional module 1101 and the second functional module 1102 both belong to a first power domain a. The first property value at the input of the first function block 1101 is equal to the second property value at the input of the second function block 1102. At this time, the configuration determining first sub-unit 553 may determine that the input terminal of the first functional module 1101 matches the input terminal of the second functional module 1102.

For example, in some embodiments, the logic function description information and the corresponding register transfer level functional block of the first netlist and the first netlist functional block each include at least one sub-functional block.

For example, in some embodiments, as shown in FIG. 9B, the match verification unit 550 also includes an attribute comparison second subunit 552 and a match determination second subunit 554. When the input of the register transfer level function block matches the input of the first netlist function block, the attribute comparison second subunit 552 is configured to compare a first attribute value in the logic function description information with a second attribute value in the first netlist of the inputs and/or outputs of the register transfer level function block and the sub-function block of the first netlist function block. The match determination second subunit 554 is configured to determine that the register transfer level function block matches the first netlist function block when a first attribute value in the logic function description information of an input and/or an output of the sub-function block is equal to a second attribute value in the first netlist. For example, as shown in fig. 5, in the register transfer level description file RTL, the first functional module 1101 further includes a first sub-functional module 201 and a second sub-functional module 202. In first netlist G1, second functional module 1102 further includes third sub-functional module 203 and fourth sub-functional module 204. Comparing the first attribute value at the output 401 of the first sub-function module 201 with the second attribute value at the output 403 of the third sub-function module 203, the first attribute value at the output 401 (i.e. the output pin 401) and the second attribute value at the output 403 are equal, since both the first sub-logic 301 and the third sub-logic 303 belong to the second power domain B. The first attribute value at the input 402 of the second sub-function module 202 is compared with the second attribute value at the input 404 of the fourth sub-function module 204, and the first attribute value at the input 402 of the second sub-function module 202 (i.e. the input pin 402) belongs to the second power domain B due to the second sub-logic 302 belonging to the second power domain B. Since the input 404 (input pin 404) of the fourth sub-function module 204 is connected to the output 406 of the ECO circuit 305, the second property value of the input 404 is equal to the second property value of the output 406, while the ECO circuit 305 belongs to the first power domain a and the second property value of the input 404 (input pin 404) of the fourth sub-function module 204 belongs to the first power domain a. Therefore, the first attribute value at the input 402 of the second sub-function module 202 (i.e. the input pin 402) is not equal to the second attribute value at the input 404 of the fourth sub-function module 204 (i.e. the input pin 404). At this time, the matching determination second subunit 554 may determine that the first functional module 1101 does not match the second functional module 1102.

Fig. 10 is a schematic structural diagram of another chip design apparatus according to at least one embodiment of the present disclosure. The chip design apparatus 400 is, for example, suitable for implementing the chip design method provided by the embodiments of the present disclosure. Chip design apparatus 400 may be a terminal device, a server, or the like. It should be noted that the chip design apparatus 400 shown in fig. 10 is only an example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 10, the chip designing apparatus 400 may include a processing device (e.g., a central processing unit, a graphic processor, etc.) 410, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM)420 or a program loaded from a storage device 480 into a Random Access Memory (RAM) 430. In the RAM 430, various programs and data necessary for the operation of the chip designing apparatus 400 are also stored. The processing device 410, the ROM420, and the RAM 430 are connected to each other by a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.

Generally, the following devices may be connected to the I/O interface 450: input devices 460 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 470 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, or the like; storage 480 including, for example, magnetic tape, hard disk, etc.; and a communication device 490. The communication means 490 may allow the chip design apparatus 400 to communicate wirelessly or wiredly with other electronic devices to exchange data. While fig. 10 illustrates a chip design apparatus 400 including various devices, it is to be understood that not all of the illustrated devices are required to be implemented or provided, and that the chip design apparatus 400 may alternatively be implemented or provided with more or fewer devices.

For example, according to an embodiment of the present disclosure, the above chip design method may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the chip design method described above. In such embodiments, the computer program may be downloaded and installed from a network through communication device 490, or installed from storage device 480, or installed from ROM 420. When executed by the processing device 410, the computer program may perform the functions defined in the chip design method provided by the embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a storage medium for storing non-transitory computer program executable code (e.g., computer executable instructions) that when executed by a computer may implement the chip design method described in any one of the embodiments of the present disclosure; alternatively, the non-transitory computer program executable code may implement the chip design method described in any of the embodiments of the present disclosure when executed by a computer.

Fig. 11 is a schematic diagram of a storage medium according to an embodiment of the disclosure. As shown in fig. 11, the storage medium 600 non-temporarily stores computer program executable code 601. For example, the computer program executable code 601 may perform one or more steps according to the chip design method described above when executed by a computer.

For example, the storage medium 600 may be applied to the chip designing apparatus 400 described above. For example, the storage medium 600 may be the memory 420 in the chip designing apparatus 400 shown in fig. 10. For example, the related description about the storage medium 600 may refer to the corresponding description of the memory 420 in the chip design apparatus 400 shown in fig. 10, and will not be described herein again.

The following points need to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and shall be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A chip design method, comprising:

loading a register transmission level description file, and reading logic function description information used for chip design of the register transmission level description file;

loading an attribute design file, and reading attribute design information of the attribute design file, which is used for chip design;

generating a first netlist by combining a standard cell library according to the logic function description information and the attribute design information by using a logic synthesis tool, wherein the logic function description information defines a plurality of register transmission level functional modules, and the first netlist comprises a plurality of first netlist functional modules which are arranged in one-to-one correspondence with the plurality of register transmission level functional modules;

extracting a first attribute value of the register transfer level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist respectively by using an analysis tool; and

verifying whether the register transfer level description file is matched with the first netlist according to the logic function description information, the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist functional module based on the attribute design information;

and comparing first attribute values of register transfer level functional modules of adjacent transfer levels in the logic function description information or comparing second attribute values of first netlist functional modules of adjacent transfer levels in the first netlist based on the attribute design information to determine the correctness of the register transfer level description file or the first netlist.

2. The chip design method of claim 1, wherein verifying whether the register transfer level description file matches the first netlist comprises:

comparing the logic function description information with a first property value of each corresponding register transfer level functional block in the first netlist and a second property value of the first netlist functional block,

determining that the register transfer level description file and the first netlist match each other when the logic function description information and the first attribute value of each corresponding register transfer level functional module in the first netlist and the second attribute value of the first netlist functional module are equal,

and when the logic function description information is not equal to at least one of the first attribute value of the register transfer level functional module and the second attribute value of the first netlist functional module corresponding to each of the first netlists, determining that the register transfer level description file is not matched with the first netlist.

3. The chip design method of claim 1, wherein the first attribute value and the second attribute value each comprise one or more of a voltage value, a timing, a clock frequency, and a power consumption.

4. The chip design method of claim 1, further comprising:

comparing a first attribute value of the input of each of the register transfer level functional blocks in the logic function description information with a second attribute value of the input of the corresponding first netlist functional block in the first netlist,

and when the logic function description information is equal to the attribute values of the input end of the register transfer level functional module and the input end of the first netlist functional module corresponding to each of the first netlists, determining that the input end of the register transfer level functional module is matched with the input end of the first netlist functional module.

5. The chip design method according to claim 4, wherein the corresponding register transfer level functional blocks and the first netlist functional block of the logic function description information and the first netlist respectively comprise at least one sub-functional block,

the chip design method further comprises the following steps:

when the input of the register transfer stage functional block matches the input of the first netlist functional block,

comparing a first attribute value in the logic function description information of the inputs and/or outputs of the register transfer level functional block and a sub-functional block of the first netlist functional block with a second attribute value in the first netlist,

and when the first attribute value of the input end and/or the output end of the sub-functional module in the logic function description information is equal to the second attribute value in the first netlist, determining that the register transfer level functional module is matched with the first netlist functional module.

6. The chip design method according to claim 5,

the register transmission stage functional module comprises a first functional module, the first functional module comprises a first sub-functional module and a second sub-functional module, the output end of the first sub-functional module is connected with the input end of the second sub-functional module,

the first netlist functional module comprises a second functional module corresponding to the first functional module, the second functional module comprises a third sub-functional module and a fourth sub-functional module, the third sub-functional module and the fourth sub-functional module respectively correspond to the first sub-functional module and the second sub-functional module,

the chip design method further comprises the following steps:

comparing a first attribute value of the output of the first sub-function module in the logical function description information with a second attribute value of the output of the third sub-function module in the first netlist, and comparing a first attribute value of the input of the second sub-function module in the logical function description information with a second attribute value of the input of the fourth sub-function module in the first netlist,

and when the first attribute value of the output end of the first sub-function module is equal to the second attribute value of the output end of the third sub-function module, and the first attribute value of the input end of the second sub-function module is equal to the second attribute value of the input end of the fourth sub-function module, determining that the first function module is matched with the second function module.

7. The chip design method of claim 6, further comprising:

comparing, in the logical function description information, a first attribute value of an output terminal of the first sub-function module with a first attribute value of an input terminal of the second sub-function module based on the attribute design information,

when the first attribute value of the output end of the first sub-function module is equal to the first attribute value of the input end of the second sub-function module, determining that the design of the first function module in the register transmission level description file is correct; or

Comparing, in the first netlist, a second property value at the output of the third sub-function module with a second property value at the input of the fourth sub-function module based on the property design information,

and when the second attribute value of the output end of the third sub-function module is equal to the second attribute value of the input end of the fourth sub-function module, determining that the second function module is correctly designed in the first netlist.

8. The chip design method according to claim 5,

the register transmission level functional module comprises a third functional module, the third functional module comprises a first data selection module, a fifth sub-functional module and a sixth sub-functional module, the output end of the first data selection module is connected with the input end of the fifth sub-functional module and the input end of the sixth sub-functional module,

the first netlist function module comprises a fourth function module corresponding to the third function module, the fourth function module comprises a second data selection module, a seventh sub-function module and an eighth sub-function module, the second data selection module, the seventh sub-function module and the eighth sub-function module respectively correspond to the first data selection module, the fifth sub-function module and the sixth sub-function module,

the chip design method further comprises the following steps:

comparing a first property value of the input of the fifth sub-function module in the logical function description information with a second property value of the input of the seventh sub-function module in the first netlist, and comparing a first property value of the input of the sixth sub-function module in the logical function description information with a second property value of the input of the eighth sub-function module in the first netlist,

and when the first attribute value of the input end of the fifth sub-function module is equal to the second attribute value of the input end of the seventh sub-function module, and the first attribute value of the input end of the sixth sub-function module is equal to the second attribute value of the input end of the eighth sub-function module, determining that the third function module is matched with the fourth function module.

9. The chip design method according to claim 1, wherein the attribute design file includes a power consumption design file,

verifying that the register transfer level description file matches the first netlist comprises:

reading the power consumption design file to obtain design information for a plurality of power domains, each of the plurality of power domains including a voltage value,

extracting the voltage values of the corresponding register transfer level functional module and the first netlist functional module from the logic function description information and the first netlist respectively by using a power verification tool,

and when the logic function description information and the voltage values of the corresponding register transfer level functional module and the corresponding first netlist functional module of the first netlist are equal, determining that the register transfer level description file and the first netlist are matched with each other.

10. The chip design method according to claim 1, wherein the property design file includes a constraint design file,

reading the constraint design file to obtain clock information, the clock information comprising a plurality of clock frequencies,

extracting at least one clock frequency of the corresponding register transfer level functional module and the first netlist functional module from the logic function description information and the first netlist respectively by using a timing analysis tool,

and when the logic function description information and at least one clock frequency of the corresponding register transfer level functional module and the corresponding first netlist functional module of the first netlist are correspondingly equal, determining that the register transfer level description file and the first netlist are matched with each other.

11. The chip design method according to any one of claims 1 to 10, further comprising:

loading a test design file, reading test design information of the test design file for chip testing,

generating a second netlist from the first netlist and the test design information based on a test design tool, wherein the second netlist comprises a plurality of second netlist functional modules arranged in one-to-one correspondence with the plurality of first netlist functional modules of the first netlist,

and extracting third attribute values of the plurality of second netlist functional modules from the second netlist by using the analysis tool, and verifying whether the first netlist is matched with the second netlist according to the second attribute values of the first netlist functional modules and the third attribute values of the second netlist functional modules corresponding to the first netlist and the second netlists respectively.

12. The chip design method of claim 11, further comprising:

and comparing third attribute values of second netlist functional modules of adjacent transmission stages of the second netlist based on the attribute design information to determine correctness of the second netlist.

13. The chip design method of claim 11, further comprising:

generating a third netlist and a database file for chip manufacturing from the second netlist using a physical implementation tool, wherein the third netlist includes a plurality of third netlist functional modules arranged in one-to-one correspondence with the plurality of second netlist functional modules of the second netlist,

and extracting fourth attribute values of the plurality of third netlist functional modules from the third netlist by using the analysis tool, and verifying whether the third netlist is matched with the second netlist according to the third attribute values of the second netlist functional modules and the fourth attribute values of the third netlist functional modules corresponding to the third netlist and the second netlist.

14. The chip design method of claim 13, further comprising:

comparing fourth property values of third netlist functional modules of adjacent transmission stages of the third netlist based on the property design information to determine correctness of the third netlist.

15. A chip design system, comprising:

the first file reading unit is configured to load a register transmission level description file and read logic function description information of the register transmission level description file, wherein the logic function description information is used for chip design;

a second file reading unit configured to load an attribute design file and read attribute design information for chip design of the attribute design file;

a first netlist generating unit configured to generate a first netlist by using a logic synthesis tool according to the logic function description information and the attribute design information in combination with a standard cell library, wherein the logic function description information defines a plurality of register transfer level functional modules, and the first netlist includes a plurality of first netlist functional modules arranged in one-to-one correspondence with the plurality of register transfer level functional modules;

an attribute extraction unit configured to extract a first attribute value of the register transfer level functional module and a second attribute value of the first netlist functional module from the logic function description information and the first netlist respectively by using an analysis tool; and

a matching verification unit configured to verify whether the register transfer level description file matches the first netlist according to the logic function description information and the first attribute value of the register transfer level function module and the second attribute value of the first netlist function module corresponding to each of the first netlist based on the attribute design information;

and a correctness determination unit configured to compare first attribute values of register transfer level functional modules of adjacent transfer levels in the logic function description information or compare second attribute values of first netlist functional modules of adjacent transfer levels in the first netlist based on the attribute design information to determine correctness of the register transfer level description file or the first netlist.

16. A chip design apparatus, comprising:

a processor; and

memory, wherein the memory has stored therein computer executable code, which when executed by the processor, performs the chip design method of any one of claims 1-14.

17. A computer readable storage medium having stored thereon executable code which, when executed by a processor, causes the processor to perform the chip design method of any one of claims 1 to 14.