CN112749526A - Power rail design method, apparatus and non-transitory computer readable medium thereof - Google Patents
Power rail design method, apparatus and non-transitory computer readable medium thereof Download PDFInfo
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Abstract
The present disclosure relates to a power rail design method, apparatus, and non-transitory computer readable medium thereof, the method comprising: identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file; carrying out design specification verification on a plurality of circuit units generated after layout and winding in an integrated circuit design file to obtain a plurality of non-violation circuit areas corresponding to power rails in each power supply area; and widening the power rail of the integrated circuit design file corresponding to at least part of the non-violated circuit area so as to occupy at least part of the non-violated circuit area.
Description
Technical Field
The present invention relates to integrated circuit design technology, and more particularly, to a power rail design method, apparatus, and non-transitory computer readable medium thereof.
Background
For reducing the negative effects caused by electromigration and voltage degradation of the power rail during power plane (power plane), most of the prior methods use more routing resources for power plane, for example, the power rail is increased from one Metal layer (Metal layer) to two Metal layers, but the routing resources are reduced more and less by using more Metal layers, which increases the design difficulty.
Therefore, there is a need in the art for a new power rail design method, apparatus, and non-transitory computer readable medium.
Disclosure of Invention
This summary is provided to provide a simplified summary of the disclosure so that the reader can obtain a basic understanding of the disclosure. This summary is not an extensive overview of the disclosure and is intended to neither identify key/critical elements of the embodiments nor delineate the scope of the embodiments.
It is an object of the present disclosure to provide a power rail design method, apparatus and non-transitory computer readable medium thereof, which can improve the problems of the prior art.
To achieve the above object, a technical solution of the present invention relates to a power rail (power rail) design method, including: identifying a plurality of power rails and a plurality of corresponding power domains (power domains) in an integrated circuit design file; performing Design Rule Check (DRC) on a plurality of circuit units generated after layout and routing in an integrated circuit design file to acquire a plurality of non-violation circuit areas corresponding to power supply rails in each power supply area; and widening the power rail of the integrated circuit design file corresponding to at least part of the non-violated circuit area so as to occupy at least part of the non-violated circuit area.
Another aspect of the present invention relates to a power rail design apparatus, including: a memory and a processor. The memory is configured to store a plurality of computer readable instructions. The processor is electrically coupled to the memory and configured to obtain and execute computer readable instructions to perform a power rail design method, the power rail design method comprising: identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file; carrying out design specification verification on a plurality of circuit units generated after layout and winding in an integrated circuit design file to obtain a plurality of non-violation circuit areas corresponding to power rails in each power supply area; and widening the power rail of the integrated circuit design file corresponding to at least part of the non-violated circuit area so as to occupy at least part of the non-violated circuit area.
Yet another aspect of the present disclosure relates to a non-transitory computer readable medium comprising computer readable instructions, wherein when executed by a processor of a computer system, cause the processor to perform a power rail design method, the power rail design method comprising: identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file; carrying out design specification verification on a plurality of circuit units generated after layout and winding in an integrated circuit design file to obtain a plurality of non-violation circuit areas corresponding to power rails in each power supply area; and widening the power rail of the integrated circuit design file corresponding to at least part of the non-violated circuit area so as to occupy at least part of the non-violated circuit area.
The power rail design method, the device and the non-transitory computer readable medium thereof can widen the power rail according to the non-violation circuit area of the circuit unit after the design specification verification so as to improve the electrical performance of the power rail.
Drawings
In order to make the aforementioned and other objects, features, advantages and embodiments of the invention more comprehensible, the following description is given:
fig. 1 is a block diagram of a power rail design apparatus according to an embodiment of the present invention;
FIG. 2 is a flow chart of a power rail design method according to an embodiment of the invention;
FIG. 3 is a layout diagram of an integrated circuit according to an embodiment of the present invention; and
FIG. 4 is a flowchart illustrating a method for performing step 203 of FIG. 2 according to an embodiment of the present invention.
Detailed Description
Please refer to fig. 1. Fig. 1 is a block diagram of a power rail design apparatus 1 according to an embodiment of the present invention. The power rail designing apparatus 1 includes: memory 100, processor 102, network unit 104, storage unit 106, and input-output unit 108. The aforementioned components may communicate with each other via, for example, but not limited to, a bus 110.
The memory 100 is any storage device capable of storing data, and may be, for example, but not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a flash memory, a hard disk, or other storage devices capable of storing data. The memory 100 is configured to store at least a plurality of computer readable instructions 101. In one embodiment, the memory 100 may also be used to store temporary data generated during the operation of the processor 102.
The processor 102 is electrically coupled to the memory 100 and configured to access the computer readable instructions 101 from the memory 100 to control the components in the power rail design apparatus 1 to perform the functions of the power rail design apparatus 1.
Wherein the network unit 104 is configured to access the network under the control of the processor 102. The storage unit 106 may be, for example, but not limited to, a magnetic disk or an optical disk for storing data or instructions under the control of the processor 102. The input/output unit 108 is operable by a user to communicate with the processor 102 for input and output of data.
Please refer to fig. 2. Fig. 2 is a flow chart of a power rail design method 200 according to an embodiment of the invention. The power rail design method 200 may be applied to the power rail design apparatus 1 shown in fig. 1, or may be implemented by other hardware components such as a database, a general processor, a calculator, a server, or other unique hardware devices with specific logic circuits or devices with specific functions, such as integrating program codes and processors/chips into unique hardware. In more detail, the power rail design method 200 may be implemented using a computer program to control the components of the power rail design apparatus 1. The computer program can be stored in a non-transitory computer readable recording medium such as a rom, a flash memory, a floppy disk, a hard disk, a compact disk, a flash drive, a magnetic tape, a database accessible via a network, or a computer readable recording medium with the same functions as those easily recognized by those skilled in the art.
The power rail design method 200 includes the following steps (it should be understood that the steps mentioned in the present embodiment, except for the specific sequence, can be performed simultaneously or partially simultaneously according to the actual requirement.
In step 201, a plurality of power rails and a plurality of corresponding power regions are identified in the integrated circuit design file 103.
In one embodiment, the integrated circuit design file 103 may be stored in, for example, but not limited to, the memory 100 and retrieved by the processor 102. The integrated circuit design file contains design data for a plurality of different circuit cells and power rails.
Please refer to fig. 3. Fig. 3 is a layout diagram of an integrated circuit 3 according to an embodiment of the present invention.
The integrated circuit 3 comprises circuit cells and power supply rails. In fig. 3, circuit units 300, 310 and power rails 320, 330 are exemplarily shown.
The circuit units 300 and 310 may be various logic operation gates, operation units or other circuits with specific functions in different embodiments to operate and process the input data. In one embodiment, the circuit cells 300 and 310 are standard cells (standard cells) and are the smallest circuit cells.
The power rails 320 and 330 are electrically coupled to the circuit units 300 and 310 through power contacts, such as contacts N1 and N2, respectively. In one embodiment, one of the power rails 320, 330 is a power line connected to a non-grounded voltage source (not shown) to provide power from the voltage source to the circuit units 300, 310; the other is a ground line connected to a ground potential (not shown) to provide the ground potential to the circuit units 300, 310.
For circuit units 300, 310 with different requirements, the power rails 320, 330 may provide power with different voltages, or power with the same voltage but different sources. Therefore, when the circuit units 300 and 310 operate according to different power sources, they belong to different power source regions.
In step 202, design specification verification is performed on the circuit units 300 and 310 generated in the integrated circuit design file 103 after layout and routing to obtain a plurality of non-violating circuit regions corresponding to the power rails 320 and 330 in each power region.
In order to meet the design specifications when any swing is down, the circuit units 300 and 310 often have elastic space without filling up the metal width. Therefore, after the circuit units 300 and 310 are generated through layout and routing and design specification verification is performed, a plurality of non-violation circuit areas can be obtained. At least some of the non-offending circuit regions are adjacent and correspond to power rails 320, 330, such as non-offending circuit region 340 exemplarily shown in fig. 3.
In step 203, the power rails 320, 330 of the integrated circuit design file 103 are widened corresponding to the non-violated circuit area 340 to occupy at least a portion of the non-violated circuit area 340.
Since these non-violating circuit regions 340 do not violate design specifications, they may be utilized to widen the power rails 320, 330 to extend into the non-violating circuit regions 340.
In one embodiment, the power rails 320, 330 are widened according to the power region to which they belong. For example, when the power rails 320, 330 receive power from a voltage source, the widened portions are also used to receive power from the voltage source. When the power rails 320, 330 are receiving ground potential, the widened portions are also used for receiving ground potential.
In one embodiment, if all of the non-violating circuit regions 340 are used for the widening of the power rails 320, 330, the flexibility of the integrated circuit design and modification is impacted. Thus, in one embodiment, the circuit cells 300, 310 in the IC design file 103 may be analyzed to widen only for non-violating circuit regions 340 selected according to the analysis results.
Please refer to fig. 4. FIG. 4 is a flowchart of a method 400 for performing step 203 of FIG. 2 according to an embodiment of the present invention.
In step 401, after obtaining the non-violation circuit areas 340, simulation-generated current and voltage analysis may be performed on the circuit units 300, 310 in the integrated circuit design file 103 to determine the areas of electrical performance weakness in the circuit units 300, 310. Wherein the electrically exhibited weak area is an area susceptible to power supply voltage drop (IR drop) and/or Electromigration (EM).
At step 402, the intersection of the non-offending circuit region 340 and the electrically exhibited weak region is determined.
In step 403, it is determined whether the number of intersections is less than a predetermined value.
At step 404, when the number of intersections is then less than the predetermined value, the intersection of the power rails 320, 330 corresponding to the non-offending circuit region 340 and the electrically weak region is widened.
When the number of intersections is not less than the default value, the number of intersections between the non-violated circuit area 340 and the electrically-behaved weak area is still too large.
In such a case, in step 405, the minimum resistance path from a voltage source (e.g., a voltage source connected via power rails 320, 330) to the power transmission paths in the circuit units 300, 310 is determined in the integrated circuit design file 103. Wherein, on the path of least resistance, it is easier to have larger current pass through.
At step 406, a candidate area on the path of least resistance is determined at the intersection of the non-offending circuit area 340 and the electrically exhibited area of weakness.
In step 407, only the candidate regions corresponding to the power rails 320, 330 are widened.
The power rail design method, the device and the non-transitory computer readable medium can widen the power rail according to the non-violation circuit area of the circuit unit after the design specification is verified, and effectively solve the problems of power supply voltage drop and electromigration of the power rail under the conditions that winding resources before a winding stage are not occupied and the design specification is not violated.
Although the foregoing embodiments have been described with reference to specific embodiments, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims.
[ notation ] to show
1: power rail design device
101: computer readable instructions
103: integrated circuit design file
106: storage unit
110: bus line
201 to 203: step (ii) of
300. 310: circuit unit
340: non-violating circuit regions
401 to 407: step (ii) of
100: memory device
102: processor with a memory having a plurality of memory cells
104: network unit
108: input/output unit
200: power rail design method
3: integrated circuit with a plurality of transistors
320. 330: power rail
400: method of producing a composite material
N1, N2: and (6) connecting points.
Claims (10)
1. A power rail design method, comprising:
identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file;
performing design specification verification on a plurality of circuit units generated after layout and routing in the integrated circuit design file to obtain a plurality of non-violation circuit areas corresponding to the power rails in the power supply areas; and
widening at least a portion of the non-violated circuit areas corresponding to the power rails of the integrated circuit design file to occupy at least a portion of the non-violated circuit areas.
2. The power rail design method of claim 1, further comprising:
performing simulation on the circuit units to generate current and voltage analysis so as to judge a plurality of electrical performance weak areas in the circuit units; and
the intersection of the power rails corresponding to the non-offending circuit regions and the electrically-exhibited weak regions is widened only.
3. The method of claim 2, wherein the electrically exhibited weak regions are regions susceptible to power supply voltage drop and/or electromigration.
4. The power rail design method of claim 1, further comprising:
determining a minimum resistance path from a voltage source to one of a plurality of power transmission paths in the circuit units in the integrated circuit design file;
judging a plurality of candidate areas positioned on the path of the minimum resistance in the intersection of the non-violation circuit areas and the electrically-expressed weak areas; and
only the candidate regions corresponding to the power rails are widened.
5. The method of claim 1, wherein the power rails are a power line or a ground line respectively.
6. A power rail design apparatus, comprising:
a memory configured to store a plurality of computer readable instructions; and
a processor electrically coupled to the memory and configured to obtain and execute the computer readable instructions to perform a power rail design method, the power rail design method comprising:
identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file;
performing design specification verification on a plurality of circuit units generated after layout and routing in the integrated circuit design file to obtain a plurality of non-violation circuit areas corresponding to the power rails in the power supply areas; and
widening at least a portion of the non-violated circuit areas corresponding to the power rails of the integrated circuit design file to occupy at least a portion of the non-violated circuit areas.
7. The power rail design apparatus of claim 6, wherein the power rail design method further comprises:
performing simulation on the circuit units to generate current and voltage analysis so as to judge a plurality of electrical performance weak areas in the circuit units; and
only the intersection of the non-offending circuit regions and the electrically-exhibited weak regions corresponding to the power rails is widened.
8. The power rail design apparatus of claim 7, wherein the electrically exhibited weak areas are areas susceptible to power supply voltage drop and/or electromigration.
9. The power rail design apparatus of claim 6, wherein the power rail design method further comprises:
determining a minimum resistance path from a voltage source to one of a plurality of power transmission paths in the circuit units in the integrated circuit design file;
judging a plurality of candidate areas positioned on the path of the minimum resistance in the intersection of the non-violation circuit areas and the electrically-expressed weak areas; and
only the candidate regions corresponding to the power rails are widened.
10. A non-transitory computer readable medium comprising a plurality of computer readable instructions, wherein the computer readable instructions, when executed by a processor of a computer system, cause the processor to perform a power rail design method, the power rail design method comprising:
identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file;
performing design specification verification on a plurality of circuit units generated after layout and routing in the integrated circuit design file to obtain a plurality of non-violation circuit areas corresponding to the power rails in the power supply areas; and
widening at least a portion of the non-violated circuit areas corresponding to the power rails of the integrated circuit design file to occupy at least a portion of the non-violated circuit areas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911046322.9A CN112749526B (en) | 2019-10-30 | 2019-10-30 | Power rail design method, device and non-transient computer readable medium thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911046322.9A CN112749526B (en) | 2019-10-30 | 2019-10-30 | Power rail design method, device and non-transient computer readable medium thereof |
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| CN112749526B CN112749526B (en) | 2024-05-07 |
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Cited By (1)
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| TWI792882B (en) * | 2022-01-24 | 2023-02-11 | 瑞昱半導體股份有限公司 | Optimizing method and optimizing device for integrated circuit layout based on power rail and power supply domain |
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