CN112749526B - Power rail design method, device and non-transient computer readable medium thereof - Google Patents
Power rail design method, device and non-transient computer readable medium thereof Download PDFInfo
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- CN112749526B CN112749526B CN201911046322.9A CN201911046322A CN112749526B CN 112749526 B CN112749526 B CN 112749526B CN 201911046322 A CN201911046322 A CN 201911046322A CN 112749526 B CN112749526 B CN 112749526B
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000001052 transient effect Effects 0.000 title description 4
- 238000004804 winding Methods 0.000 claims abstract description 10
- 238000012795 verification Methods 0.000 claims abstract description 8
- 238000004458 analytical method Methods 0.000 claims description 4
- 230000006399 behavior Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000004590 computer program Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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Abstract
The present disclosure relates to a power rail design method, apparatus, and non-transitory computer readable medium, the method comprising: identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file; performing design specification verification on a plurality of circuit units generated after layout and winding in an integrated circuit design file to obtain a plurality of non-violating circuit areas corresponding to power supply rails in each power supply area; and widening the power supply rail of the integrated circuit design file corresponding to at least part of the non-violating circuit area so as to occupy at least part of the non-violating circuit area.
Description
Technical Field
The present invention relates to integrated circuit design technology, and in particular, to a power rail design method, apparatus, and non-transitory computer readable medium thereof.
Background
In order to reduce negative effects caused by electromigration and voltage degradation on a power rail during power planning (power plan), more winding resources are mostly used for power planning in the prior art, for example, the power rail is increased from one metal layer (METAL LAYER) to two metal layers, but the winding resources are less and less due to the use of more metal layers, so that the design difficulty is increased.
Therefore, how to design a new power rail design method, device and non-transitory computer readable medium thereof is a problem to be solved in the industry.
Disclosure of Invention
This summary is intended to provide a simplified summary of the disclosure so that the reader will have a basic understanding of the disclosure. This summary is not an extensive overview of the disclosure and is intended to neither identify key/critical elements of the embodiments of the invention nor delineate the scope of the invention.
It is an object of the present invention to provide a power rail design method, apparatus and non-transitory computer readable medium thereof, which solve the problems of the prior art.
To achieve the above object, one aspect of the present invention relates to a power rail (power rail) design method, comprising: identifying a plurality of power rails and a plurality of corresponding power domains (power domains) in an integrated circuit design file; performing design specification verification (design rule check; DRC) on a plurality of circuit units generated after placement and routing in an integrated circuit design file to obtain a plurality of non-offending circuit areas corresponding to power rails in each power area; and widening the power supply rail of the integrated circuit design file corresponding to at least part of the non-violating circuit area so as to occupy at least part of the non-violating circuit area.
Another aspect of the present disclosure relates to a power rail design apparatus, including: memory and a processor. The memory is configured to store a plurality of computer readable instructions. The processor is electrically coupled to the memory and configured to obtain and execute the computer readable instructions to perform a power rail design method, the power rail design method comprising: identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file; performing design specification verification on a plurality of circuit units generated after layout and winding in an integrated circuit design file to obtain a plurality of non-violating circuit areas corresponding to power supply rails in each power supply area; and widening the power supply rail of the integrated circuit design file corresponding to at least part of the non-violating circuit area so as to occupy at least part of the non-violating circuit area.
Yet another aspect of the disclosure relates to a non-transitory computer readable medium comprising a plurality of computer readable instructions, wherein the computer readable instructions, when executed by a processor of a computer system, cause the processor to perform a power rail design method comprising: identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file; performing design specification verification on a plurality of circuit units generated after layout and winding in an integrated circuit design file to obtain a plurality of non-violating circuit areas corresponding to power supply rails in each power supply area; and widening the power supply rail of the integrated circuit design file corresponding to at least part of the non-violating circuit area so as to occupy at least part of the non-violating circuit area.
The power supply rail design method, the device and the non-transient computer readable medium thereof can widen the power supply rail according to the non-illegal circuit area of the circuit unit after the design specification is verified, so as to improve the electrical performance of the power supply rail.
Drawings
The above and other objects, features, advantages and embodiments of the present invention will become more apparent by reading the following description of the accompanying drawings in which:
FIG. 1 is a block diagram of a power rail design apparatus according to an embodiment of the present invention;
FIG. 2 is a flow chart of a power rail design method according to an embodiment of the invention;
FIG. 3 is a schematic layout of an integrated circuit according to an embodiment of the invention; and
FIG. 4 is a flowchart of a method for performing step 203 of FIG. 2 according to an embodiment of the present invention.
Detailed Description
Please refer to fig. 1. Fig. 1 is a block diagram of a power rail design apparatus 1 according to an embodiment of the present invention. The power rail design apparatus 1 includes: memory 100, processor 102, network element 104, storage element 106, and input/output element 108. The components described above may communicate with each other via, for example, but not limited to, bus 110.
Memory 100 is any storage device that may be used to store data and may be, for example, but is not limited to, random access memory (random access memory; RAM), read Only Memory (ROM), flash memory, a hard disk, or other storage device that may be used to store data. Memory 100 is configured to store at least a plurality of computer readable instructions 101. In one embodiment, memory 100 may also be used to store temporary data generated during operations performed by processor 102.
The processor 102 is electrically coupled to the memory 100 and configured to access the computer readable instructions 101 from the memory 100 to control the components of the power rail design apparatus 1 to perform the functions of the power rail design apparatus 1.
Wherein the network element 104 is configured to access the network under control of the processor 102. Storage unit 106 may be, for example, but is not limited to, a magnetic disk or optical disk for storing data or instructions under the control of processor 102. The input-output unit 108 is operable by a user to communicate with the processor 102 for input and output of data.
Please refer to fig. 2. Fig. 2 is a flow chart of a power rail design method 200 according to an embodiment of the invention. The power rail design method 200 may be applied to the power rail design apparatus 1 shown in fig. 1, or may be actually performed by other hardware components such as databases, general processors, computers, servers, or other unique hardware devices or devices with specific logic circuits or specific functions, such as integrating program codes and processors/chips into unique hardware. In more detail, the power rail design method 200 may be implemented using a computer program to control the components of the power rail design apparatus 1. The computer program may be stored in a non-transitory computer readable recording medium such as a rom, a flash memory, a floppy disk, a hard disk, an optical disk, a flash drive, a magnetic tape, a database accessible by a network, or a computer readable recording medium having the same functions as those skilled in the art.
The power rail design method 200 includes the following steps (it should be understood that the steps mentioned in this embodiment may be performed simultaneously or partially simultaneously, and the order of the steps may be adjusted according to the actual needs, unless the order is specifically described.
In step 201, in the integrated circuit design file 103, a plurality of power rails and a plurality of corresponding power regions are identified.
In one embodiment, integrated circuit design file 103 may be stored in, for example, but not limited to, memory 100 and retrieved by processor 102. The integrated circuit design file contains design data for a plurality of different circuit cells and power rails.
Please refer to fig. 3. Fig. 3 is a schematic layout diagram of an integrated circuit 3 according to an embodiment of the invention.
The integrated circuit 3 comprises circuit units and power supply rails. In fig. 3, circuit units 300, 310 and power rails 320, 330 are exemplarily shown.
The circuit units 300, 310 may be various logic gates, operation units or other circuits with specific functions to perform operations and processes on the input data in different embodiments. In one embodiment, the circuit cells 300, 310 are standard cells STANDARD CELL, which are the smallest circuit cells.
The power rails 320, 330 are electrically coupled to the circuit units 300, 310 through power contacts, such as contacts N1, N2, respectively. In one embodiment, one of the power rails 320, 330 is a power line connected to a non-ground voltage source (not shown) to provide power from the voltage source to the circuit units 300, 310; the other is a ground line connected to a ground potential (not shown) to provide the ground potential to the circuit units 300, 310.
The power rails 320, 330 may provide power at different voltages or power at the same voltage but from different sources for different circuit units 300, 310. Therefore, when the circuit units 300 and 310 operate according to different power sources, they respectively belong to different power source regions.
In step 202, the layout and routing of the circuit cells 300, 310 in the integrated circuit design file 103 are verified to obtain a plurality of non-offending circuit areas corresponding to the power supply rails 320, 330 in each power supply area.
In order to meet the design specification when the circuit units 300, 310 are placed down at random, the metal width of the circuit units is not filled, and the circuit units have a flexible space. Thus, after the circuit cells 300, 310 are generated via layout and routing and verified by the design specification, a plurality of non-offending circuit areas are obtained. Wherein at least a portion of the non-offending circuit region is contiguous and corresponds to the power rails 320, 330, such as the non-offending circuit region 340 illustrated by way of example in fig. 3.
In step 203, the power rails 320, 330 of the integrated circuit design file 103 are widened corresponding to the non-offending circuit region 340 to occupy at least a portion of the non-offending circuit region 340.
Since these non-violated circuit regions 340 do not violate design specifications, they may be utilized to widen the power rails 320, 330 into the non-violated circuit regions 340.
In one embodiment, the power rails 320, 330 widen according to the power region to which they belong. For example, when the power rails 320, 330 are receiving power from a voltage source, the widened portion is also receiving power from the voltage source. When the power rails 320, 330 are receiving ground, the widened portion is also configured to receive ground.
In one embodiment, if all of the non-offending circuit area 340 is used for widening of the power rails 320, 330, flexibility in integrated circuit design and modification will be affected. Thus, in one embodiment, the circuit cells 300, 310 in the integrated circuit design file 103 may be analyzed to widen only for non-offending circuit regions 340 selected based on the analysis results.
Please refer to fig. 4. Fig. 4 is a flowchart of a method 400 for performing step 203 of fig. 2 according to an embodiment of the present invention.
After the non-offending circuit area 340 is obtained in step 401, the circuit units 300, 310 in the integrated circuit design file 103 may be simulated to generate current and voltage analyses to determine the electrically-performance weak point areas in the circuit units 300, 310. The electrical performance vulnerability region is a region susceptible to power supply voltage drop (IR drop) and/or Electromigration (EM).
In step 402, the intersection of the non-offending circuit region 340 and the electrically-performance weak point region is determined.
In step 403, it is determined whether the number of intersections is less than a predetermined value.
In step 404, when the number of intersections is then smaller than the default value, only the intersections of the power rails 320, 330 corresponding to the non-offending circuit region 340 and the electrically behavior weak point region are widened.
When the number of intersections is not less than the default value, the number of intersections representing the non-offending circuit region 340 and the electrically behavior weak point region remains too large.
In such a case, at step 405, the least resistance path from a voltage source (e.g., the voltage source connected through the power rails 320, 330) to the multiple power transmission paths in the circuit units 300, 310 is determined in the integrated circuit design file 103. Wherein on the path of least resistance, a larger current is easier to pass.
In step 406, candidate regions located on the minimum resistance path are determined in the intersection of the non-offending circuit region 340 and the electrically weak spot region.
In step 407, only the candidate areas corresponding to the power rails 320, 330 are widened.
The power supply rail design method, the device and the non-transient computer readable medium thereof can widen the power supply rail according to the non-violating circuit area of the circuit unit after the verification of the design specification, and effectively solve the problems of power supply voltage drop and electromigration of the power supply rail under the condition of not occupying winding resources before a winding stage and not violating the design specification.
Although the embodiments of the present invention have been described in detail, those skilled in the art to which the invention pertains will appreciate that numerous changes and modifications can be made without departing from the spirit and scope of the invention as set forth in the appended claims.
[ Symbolic description ]
1: Power supply rail design device
101: Computer readable instructions
103: Integrated circuit design file
106: Storage unit
110: Bus line
201 To 203: step (a)
300. 310: Circuit unit
340: Non-offending circuit area
401 To 407: step (a)
100: Memory
102: Processor and method for controlling the same
104: Network element
108: Input/output unit
200: Power supply rail design method
3: Integrated circuit
320. 330: Power supply rail
400: Method of
N1, N2: and (5) a contact.
Claims (10)
1. A power rail design method, comprising:
identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file;
performing design specification verification on a plurality of circuit units generated after layout and winding in the integrated circuit design file to obtain a plurality of non-violating circuit areas corresponding to the power supply rails in each of the power supply areas; and
At least a portion of the non-offending circuit areas corresponding to the power rails of the integrated circuit design file are widened to occupy at least a portion of the non-offending circuit areas.
2. The power rail design method of claim 1, further comprising:
Simulating the circuit units to generate current and voltage analysis so as to judge a plurality of electric performance weak point areas in the circuit units; and
Only the intersections of the power rails with the non-offending circuit areas and the electrically behavior weak points are widened.
3. The power rail design method of claim 2, wherein the electrically active weak spots are areas susceptible to power supply voltage drops and/or electromigration.
4. The power rail design method of claim 2, further comprising:
In the IC design file, a minimum resistance path from a voltage source to a plurality of power supply transmission paths in the circuit units is judged;
Judging a plurality of candidate areas positioned on the minimum resistance path in the intersection of the non-violating circuit areas and the electric performance weak point areas; and
Only the candidate areas corresponding to the power rails are widened.
5. The power rail design method according to claim 1, wherein the power rails are a power line or a ground line, respectively.
6. A power rail design apparatus, comprising:
a memory configured to store a plurality of computer readable instructions; and
A processor electrically coupled to the memory and configured to obtain and execute the computer-readable instructions to perform a power rail design method comprising:
identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file;
performing design specification verification on a plurality of circuit units generated after layout and winding in the integrated circuit design file to obtain a plurality of non-violating circuit areas corresponding to the power supply rails in each of the power supply areas; and
At least a portion of the non-offending circuit areas corresponding to the power rails of the integrated circuit design file are widened to occupy at least a portion of the non-offending circuit areas.
7. The power rail design apparatus according to claim 6, wherein the power rail design method further comprises:
Simulating the circuit units to generate current and voltage analysis so as to judge a plurality of electric performance weak point areas in the circuit units; and
Only the intersections of the non-offending circuit areas and the electrically behavior weak points areas corresponding to the power rails are widened.
8. The power rail design apparatus of claim 7, wherein the electrically active weak spots are areas susceptible to power supply voltage drops and/or electromigration.
9. The power rail design apparatus according to claim 7, wherein the power rail design method further comprises:
In the IC design file, a minimum resistance path from a voltage source to a plurality of power supply transmission paths in the circuit units is judged;
Judging a plurality of candidate areas positioned on the minimum resistance path in the intersection of the non-violating circuit areas and the electric performance weak point areas; and
Only the candidate areas corresponding to the power rails are widened.
10. A non-transitory computer readable medium containing a plurality of computer readable instructions, wherein the computer readable instructions, when executed by a processor of a computer system, cause the processor to perform a power rail design method comprising the steps of:
identifying a plurality of power rails and a plurality of corresponding power areas in an integrated circuit design file;
performing design specification verification on a plurality of circuit units generated after layout and winding in the integrated circuit design file to obtain a plurality of non-violating circuit areas corresponding to the power supply rails in each of the power supply areas; and
At least a portion of the non-offending circuit areas corresponding to the power rails of the integrated circuit design file are widened to occupy at least a portion of the non-offending circuit areas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911046322.9A CN112749526B (en) | 2019-10-30 | 2019-10-30 | Power rail design method, device and non-transient computer readable medium thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911046322.9A CN112749526B (en) | 2019-10-30 | 2019-10-30 | Power rail design method, device and non-transient computer readable medium thereof |
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| CN112749526A CN112749526A (en) | 2021-05-04 |
| CN112749526B true CN112749526B (en) | 2024-05-07 |
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| TWI792882B (en) * | 2022-01-24 | 2023-02-11 | 瑞昱半導體股份有限公司 | Optimizing method and optimizing device for integrated circuit layout based on power rail and power supply domain |
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| US7200829B2 (en) * | 2004-06-24 | 2007-04-03 | International Business Machines Corporation | I/O circuit power routing system and method |
| US8451026B2 (en) * | 2011-05-13 | 2013-05-28 | Arm Limited | Integrated circuit, method of generating a layout of an integrated circuit using standard cells, and a standard cell library providing such standard cells |
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| JP2001034646A (en) * | 1999-07-16 | 2001-02-09 | Matsushita Electric Ind Co Ltd | Device and method for optimizing semiconductor integrated circuit |
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