CN116611385A - Optimization method and optimization device for integrated circuit layout - Google Patents

Abstract

An optimization method and an optimization device for an integrated circuit layout in a post-winding stage are provided. The method comprises the following steps: identifying a power rail and a corresponding power domain in an integrated circuit design file; performing design specification verification on the circuit units in the integrated circuit design file to calculate a plurality of usable areas; judging a plurality of electromigration violation points corresponding to the power rail and related current information; defining a path to be corrected on the power rail corresponding to the electromigration violation point according to the electromigration violation point and the current information; replacing the types of the plurality of guide holes on the power supply rail at the part which is not overlapped with the waiting correction path; and correcting the number of guide holes on the part of the power rail overlapped with the path to be corrected so as to reduce the number of electromigration violations.

Description

Optimization method and optimization device for integrated circuit layout

Technical Field

The present invention relates to integrated circuit design, and more particularly, to an optimization method, apparatus and non-transitory computer readable medium for integrated circuit layout.

Background

After the circuit layout is completed, standard cells (standard cells) are placed around the IC, and the power rail refers to a metal wire connected in series with a power pin or a ground pin of the standard cells. For a plurality of standard cells at the same level, a corresponding plurality of power rails are directly connected in series with each other. Depending on the design of the different standard cells, there are also modes of use in which they are connected in series with each other by the same vertical line.

In the circuit layout, the power rail maintains high availability in addition to sharing the wiring resources of the metal layer with the signal wiring (routing), so that the metal lines are thinner and thinner compared with the whole power supply layout, and relatively serious electromigration is easy to occur on the power rail.

In order to reduce the negative effects caused by electromigration on the power rail during power planning (power plan), most of the existing methods use more winding resources for power planning, for example, the width of the power rail is increased, but the more the power rail is used, the less winding resources are used, and the difficulty of design is increased.

Disclosure of Invention

The present invention is directed to an optimization method, an optimization device and a non-transitory computer readable medium for integrated circuit layout, which address the shortcomings of the prior art.

In order to solve the above-mentioned problems, one of the technical solutions adopted in the present invention is to provide an optimization method for an integrated circuit layout, which includes: identifying a plurality of power rails and a plurality of corresponding power domains (power domains) in an integrated circuit design file; performing design specification verification (design rule check, DRC) on circuit cells generated after placement and routing in the integrated circuit design file to calculate usable areas corresponding to the power rails; simulating the circuit units to generate current and voltage analysis so as to judge a plurality of electromigration violations corresponding to the power rails and relevant current information; defining a plurality of paths to be corrected on the power rails corresponding to the electromigration violations according to the electromigration violations and the current information; replacing the types of the plurality of guide holes on the power rails at the parts which are not overlapped with the waiting correction paths; and correcting the number of the plurality of vias on the portions of the power rails overlapping the wait correction path according to the current directions and the locations of the electromigration violations to reduce the number of the electromigration violations.

In order to solve the above-mentioned problems, another aspect of the present invention is to provide an optimizing apparatus for an integrated circuit layout, which includes a memory and a processor. A memory configured to store a plurality of computer-executable instructions; and a processor electrically coupled to the memory and configured to obtain and execute the computer-executable instructions to perform an optimization method comprising: identifying a plurality of power rails and a plurality of corresponding power domains (power domains) in an integrated circuit design file; performing design specification verification (design rule check, DRC) on circuit cells generated after placement and routing in the integrated circuit design file to calculate usable areas corresponding to the power rails; simulating the circuit units to generate current and voltage analysis so as to judge a plurality of electromigration violations corresponding to the power rails and relevant current information; defining a plurality of paths to be corrected on the power rails corresponding to the electromigration violations according to the electromigration violations and the current information; replacing the types of the plurality of guide holes on the power rails at the parts which are not overlapped with the waiting correction paths; and correcting the number of the plurality of vias on the portions of the power rails overlapping the wait correction path according to the current directions and the locations of the electromigration violations to reduce the number of the electromigration violations.

In order to solve the above-mentioned problems, another aspect of the present invention provides a non-transitory computer readable medium comprising a plurality of computer readable instructions, wherein when the computer readable instructions are executed by a processor of a computer system, the processor is caused to perform an optimizing method, the optimizing method comprises: identifying a plurality of power rails and a plurality of corresponding power domains (power domains) in an integrated circuit design file; performing design specification verification (design rule check, DRC) on circuit cells generated after placement and routing in the integrated circuit design file to calculate usable areas corresponding to the power rails; simulating the circuit units to generate current and voltage analysis so as to judge a plurality of electromigration violations corresponding to the power rails and relevant current information; defining a plurality of paths to be corrected on the power rails corresponding to the electromigration violations according to the electromigration violations and the current information; replacing the types of the plurality of guide holes on the power rails at the parts which are not overlapped with the waiting correction paths; and correcting the number of the plurality of vias on the portions of the power rails overlapping the wait correction path according to the current directions and the locations of the electromigration violations to reduce the number of the electromigration violations.

One of the advantages of the present invention is that the optimization method, apparatus and non-transitory computer readable medium for integrated circuit layout provided by the present invention can detect whether a certain section of double-layer power supply rail after the completion of layout (placement) and routing (routing) can adjust the via density between them and distribute the current trend based on the Design Rule Checking (DRC) method of the circuit element connection relationship. Thus, adverse effects caused by electromigration can be reduced without violating design rules.

For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the invention.

Drawings

FIG. 1 is a functional block diagram of an optimization apparatus for integrated circuit layout according to an embodiment of the present invention.

FIG. 2 is a flow chart of an optimization method for an integrated circuit layout according to an embodiment of the invention.

Fig. 3 is a layout diagram of an integrated circuit according to an embodiment of the invention.

Fig. 4 is a schematic diagram of defining a path to be corrected in a layout diagram of an integrated circuit according to an embodiment of the invention.

FIG. 5 is a schematic diagram illustrating a layout of an integrated circuit according to an embodiment of the present invention.

Fig. 6 is a third schematic diagram of defining a path to be corrected in a layout diagram of an integrated circuit according to an embodiment of the invention.

Symbol description

1: optimizing device

3: integrated circuit

10: memory device

11: processor and method for controlling the same

12: network element

13: memory cell

14: input/output interface

15: bus line

30: circuit unit

31. 32: power supply rail

33. 34: usable area

40. 50, 60: route to be corrected

41. 51: part of the

100: computer readable instructions

102: integrated circuit design file

104: simulation tool

310. 320: contact point

D1: first predetermined distance

D2: second predetermined distance

D3: third predetermined distance

D4: fourth predetermined distance

em1, em2, em3: electromigration violation point

I1 and I2: electric current

V1: large guide hole

V11, V12, V13, V21: guide hole

V2: small-sized guide hole

Detailed Description

The following description is presented to illustrate embodiments of the disclosed optimization method, apparatus and non-transitory computer readable medium for integrated circuit layout, and those skilled in the art will appreciate the advantages and effects of the present invention from the disclosure herein. The invention is capable of other and different embodiments and its several details are capable of modification and variation in various respects, all from the point of view and application, all without departing from the spirit of the present invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention. In addition, the term "or" as used herein shall include any one or combination of more of the associated listed items as the case may be.

FIG. 1 is a functional block diagram of an optimization apparatus for integrated circuit layout according to an embodiment of the present invention. Referring to fig. 1, an embodiment of the invention provides an optimizing apparatus 1 for an integrated circuit layout, which includes a memory 10, a processor 11, a network unit 12, a storage unit 13, and an input/output interface 14. The elements described above may communicate with each other via, for example, but not limited to, bus 15.

Memory 10 is any storage device that may be used to store data and may be, for example, but is not limited to, random access memory (random access memory; RAM), read Only Memory (ROM), flash memory, a hard disk, or other storage device that may be used to store data. The memory 10 is configured to store at least a plurality of computer readable instructions 100. In one embodiment, the memory 10 may also be used to store temporary data generated during operation of the processor 11.

The processor 11 is electrically coupled to the memory 10 and is configured to access the computer readable instructions 100 from the memory 10 to control the components of the power rail design apparatus 1 to perform the functions of the power rail design apparatus 1.

Wherein the network element 12 is configured to access the network under control of the processor 11. The storage unit 13 may be, for example, but is not limited to, a magnetic disk or an optical disk, for storing data or instructions under the control of the processor 11. The input/output unit 14 is operable by a user to communicate with the processor 11 for inputting and outputting data.

FIG. 2 is a flow chart of an optimization method for an integrated circuit layout according to an embodiment of the invention. Fig. 2 provides an optimization method for an integrated circuit layout, which can be applied to the optimization device 1 shown in fig. 1, or implemented by other hardware components such as databases, general processors, computers, servers, or other unique hardware devices with specific logic circuits or devices with specific functions, such as integrating program codes and processors/chips into unique hardware. In more detail, the optimization method can be implemented using a computer program to control the elements of the optimization apparatus 1. The computer program may be stored in a non-transitory computer readable recording medium such as a rom, flash memory, floppy disk, hard disk, optical disk, usb disk, magnetic tape, network accessible database, or computer readable recording medium having the same functions as those skilled in the art.

Referring to fig. 2, the optimizing method for the integrated circuit layout includes the following steps:

step S200: in the integrated circuit design file, a plurality of power rails and a corresponding plurality of power domains (power domains) are identified. In some embodiments, the integrated circuit design file 102 may be stored in, for example, but not limited to, the memory 10 and accessed by the processor 11. The integrated circuit design file contains design data for a plurality of different circuit cells and power rails.

In detail, in this step, the power rails refer to a plurality of dual-layer power rails. In one dual layer power rail, two power rails are included, each disposed in two metal layers, which are connected by a plurality of vias (via). In the subsequent steps, it is mainly determined whether the via density of each double-layer power rail can be increased or decreased, and it is not emphasized hereinafter to refer to the double-layer power rail.

Fig. 3 is a schematic layout diagram of an integrated circuit 3 according to an embodiment of the invention. As shown in fig. 3, the integrated circuit 3 exemplarily comprises at least one circuit unit 30 and power supply rails 31, 32. In this embodiment, the power rails 31, 32 are double-layered power rails, the power rail 31 has a plurality of large-sized guide holes V1, and the power rail 32 has a plurality of small-sized guide holes V2. In the present embodiment, the number of the circuit unit 30, the power rails 31, 32, the large-sized via V1 and the small-sized via V2 is merely an example, and the present invention is not limited thereto.

The circuit unit 30 may be, for example, various logic gates, an operation unit or other circuits with specific functions to perform operation and processing on the input data. In some embodiments, the circuit cell 30 may be a standard cell, which is the smallest circuit cell.

The power rails 31, 32 are electrically coupled to the circuit unit 30 through power contacts, such as contacts 310, 320, respectively. In one embodiment, power rail 31 may provide power to circuit unit 30 from a voltage source, while power rail 32 may be connected to a ground line having a ground potential to provide the ground potential to circuit unit 30. The power rails 31, 32 may provide power at different voltages or at the same voltage but from different sources for different requirements of the circuit unit 30. Therefore, when the circuit units 31, 32 are operated according to different power sources, they will respectively belong to different power source domains.

Step S201: design specification verification (design rule check, DRC) is performed on circuit cells generated in the integrated circuit design file via layout and routing (placement and routing) to calculate a plurality of usable areas corresponding to the power rails.

To meet the design specifications, the circuit unit 30 generally does not use up all of the design space to maintain flexibility. Therefore, after the circuit unit 30 is created via layout and wiring and DRC is performed, a plurality of usable areas are obtained. Wherein at least part of the usage areas are contiguous to correspond to the power rails 31, 32, such as the usage areas 33, 34 shown in fig. 3.

Step S202: the circuit units are simulated to generate current and voltage analyses to determine a plurality of electromigration violations and associated current information corresponding to the power rails.

In this step, after the available regions 33 and 34 are obtained, the circuit unit 30 in the integrated circuit design file 102 may be subjected to analog current and voltage analysis to determine the regions of the corresponding power supply rails 31 and 32 that are susceptible to Electromigration (EM).

In detail, the memory 10 may store a simulation tool 104, which may be executed after accessing the memory 10 by the processor 11. Simulation tool 104 may be configured to perform voltage and current simulations to determine currents from one or more components within integrated circuit 3 and compare the currents to set current limits to identify the electromigration violations corresponding to power rails 31, 32. At the same time, the simulation tool 104 may also obtain a plurality of current directions and a plurality of current magnitudes on the power rails corresponding to the electromigration violations.

For example, if the current on the power rails 31, 32 violates the current limit, an electromigration violation is identified. In some embodiments, simulation tool 104 may include an integrated circuit importance Simulation Program (SPICE) simulator.

Step S203: according to the electromigration violations and the current information, a plurality of paths to be corrected are defined on the power rails corresponding to the electromigration violations.

In detail, defining the path to be corrected may include several ways.

Please refer to fig. 4, which is a first diagram illustrating a path to be corrected defined in a layout diagram of the integrated circuit 3 according to an embodiment of the present invention.

As shown in fig. 4, for one of the electromigration violations, for example, electromigration violation em1, the higher current side is found based on the current information. Taking fig. 4 as an example, the one-side current I2 of the electromigration violation em1 is larger than the other-side current I1, and thus extends a first predetermined distance D1 along the corresponding power rail 31 to the side of the larger current I2 as one of the paths 40 to be corrected.

Please refer to fig. 5, which is a second diagram illustrating a path to be corrected defined in a layout diagram of the integrated circuit 3 according to an embodiment of the present invention.

As shown in fig. 5, for one of the electromigration violations, e.g., electromigration violation em2, the lower current side is found from the current information. Taking fig. 5 as an example, the one-side current I2 of the electromigration violation em2 is smaller than the other-side current I1, and thus extends a second predetermined distance D2 along the corresponding power rail 31 to the side of the smaller current I2 as one of the paths 50 to be corrected.

Fig. 6 is a third schematic diagram of defining a path to be corrected in a layout diagram of the integrated circuit 3 according to an embodiment of the invention.

As shown in fig. 6, for one of the electromigration violations, for example, electromigration violation em3, a first side with a lower current and a second side with a higher current are found according to the current information. Taking fig. 6 as an example, the first side current I1 of the electromigration violation of point em3 is smaller than the second side current I2, and therefore extends a third predetermined distance D3 along the corresponding power rail 31 to the first side of the smaller current I1 and a fourth predetermined distance D4 along the corresponding power rail 31 to the second side of the larger current I2 as one of the paths 60 to be corrected.

Step S204: the types of the plurality of vias on the power rails are replaced in the portions not overlapping with the wait modification paths. For example, after step S203, the power supply rail on which the path to be corrected is not found, for example, the power supply rail 32 of fig. 5, is replaced corresponding to the kind of the via V13 in the portion 51 of the usable area 33. For example, the via size of via V13 may be replaced with a larger via size to direct a larger current into these regions by reducing the impedance to reduce the number of electromigration violations in the layout of integrated circuit 3. On the other hand, although not specifically shown in fig. 4, if the power rail 32 of fig. 4 is connected to a specific electromigration violation, the type of via V21 in the portion 41 of the region 34 may be replaced to reduce the number of electromigration violations.

Step S205: the number of vias on portions of the power rails overlapping the wait-correction paths is corrected based on the current directions and the locations of the electromigration violations to reduce the number of electromigration violations.

In detail, this step reduces electromigration violations by adjusting via density in the path to be corrected.

Thus, taking fig. 4 as an example, since the path 40 to be corrected has higher current, a part or all of the vias V11 on the path 40 to be corrected are removed to guide the larger current I2 to the side with lower current I1 by increasing impedance until the corresponding electromigration violation em1 disappears or the degree of violation of the electromigration violation em1 is reduced as much as possible, for example, the current of the electromigration violation em1 is made as close to the set current limit as possible without exceeding too much.

Taking fig. 5 as an example, since the path 50 to be corrected has a lower current, an additional via is added to the path 50 to be corrected, or the via type is changed to increase the via size, so as to guide the larger current I1 to the side with the lower current I2 by reducing the impedance until the corresponding electromigration violation point em2 disappears, or the degree of violation of the electromigration violation point em2 is reduced as much as possible, for example, the current of the electromigration violation point em2 is made as close to the set current limit as possible and does not exceed too much.

Next, taking fig. 6 as an example, since the first side has a lower current I1 and the second side has a higher current I2 on the path 60 to be corrected, an additional via is added to the portion of the path 60 to be corrected extending toward the first side, or the via type is changed to increase the via size, and at the same time, a portion or all of the vias V12 are removed from the portion of the path 60 to be corrected extending toward the second side, so as to guide the larger current I2 to be shunted toward the side having the lower current I1 by reducing the impedance of the low current portion and increasing the impedance of the high current portion until the corresponding electromigration violation point em3 disappears, or the degree of violation of the electromigration violation point em3 is reduced as much as possible. It should be noted that in the step of removing the via hole, it is necessary to determine whether the via hole is removable, so as to avoid affecting the normal operation of the circuit unit 30.

Therefore, in the above manner, besides the negative effect caused by electromigration on the power rail can be reduced, the existing winding resources are not required to be additionally occupied, and furthermore, the usable area is not required to be corrected by checking the design rule for the change of the density of the guide holes because the usable area passes the checking of the design rule.

Advantageous effects of the embodiment

One of the advantages of the present invention is that the optimization method, apparatus and non-transitory computer readable medium for integrated circuit layout provided by the present invention can detect whether a certain section of double-layer power supply rail after the completion of layout (placement) and routing (routing) can adjust the via density between them and distribute the current trend based on the Design Rule Checking (DRC) method of the circuit element connection relationship. Thus, adverse effects caused by electromigration can be reduced without violating design rules.

The above disclosure is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention, so all technical equivalents which may be used in the specification and drawings of the present invention are included in the claims of the present invention.

Claims (10)

1. An optimization method for an integrated circuit layout, comprising:

identifying a plurality of power rails and a plurality of power supply domains corresponding to the power rails in an integrated circuit design file;

performing design specification verification on a plurality of circuit units generated after layout and winding in the integrated circuit design file to calculate a plurality of usable areas corresponding to the plurality of power rails;

performing simulation to the circuit units to generate current and voltage analysis so as to judge a plurality of electromigration violations corresponding to the power rails and related current information;

defining a plurality of paths to be corrected on the power rails corresponding to the electromigration violations according to the electromigration violations and the current information;

replacing the types of the plurality of guide holes on the plurality of power rails at the part which is not overlapped with the plurality of paths to be corrected; and

and correcting the number of the plurality of guide holes on the plurality of power rails at the part overlapped with the plurality of paths to be corrected according to the plurality of current directions and the positions of the plurality of electromigration violations so as to reduce the number of the plurality of electromigration violations.

2. The optimizing method according to claim 1, wherein the step of replacing the kind of the plurality of vias comprises replacing the plurality of vias with a plurality of vias having a larger size.

3. The optimization method of claim 1, wherein defining the plurality of paths to be corrected comprises:

and aiming at one electromigration violation point, finding out a side with higher current according to the current information, and extending a first preset distance to the side along the corresponding power rail to serve as one of the paths to be corrected.

4. The optimization method of claim 3, wherein the step of modifying the number of the plurality of vias further comprises removing the plurality of vias on the plurality of paths to be modified.

5. The optimization method of claim 1, wherein defining the plurality of paths to be corrected comprises:

and aiming at one electromigration violation point, finding out a side with lower current according to the current information, and extending a second preset distance to the side along the corresponding power rail to serve as one of the paths to be corrected.

6. The optimization method of claim 5, wherein the step of modifying the number of the plurality of vias further comprises adding additional vias to the plurality of paths to be modified.

7. The optimization method of claim 1, wherein defining the plurality of paths to be corrected comprises:

for one of the electromigration violations, a first side with lower current and a second side with higher current are found according to the current information, a third preset distance is extended to the first side along the corresponding power rail, and a fourth preset distance is extended to the second side along the corresponding power rail to serve as one of the paths to be corrected.

8. The optimizing method as claimed in claim 7, wherein the step of correcting the number of the plurality of vias further includes adding an additional via in a portion extending toward the first side and reducing a via in a portion extending toward the second side among the plurality of paths to be corrected.

9. The optimization method of claim 1, wherein the current information includes a plurality of current directions and a plurality of current magnitudes of the plurality of power rails corresponding to the plurality of electromigration violations.

10. An optimization apparatus for an integrated circuit layout, comprising:

a memory configured to store a plurality of computer executable instructions; and

a processor, electrically coupled to the memory, configured to obtain and execute the computer-executable instructions to perform an optimization method comprising:

identifying a plurality of power rails and a plurality of power supply domains corresponding to the power rails in an integrated circuit design file;

performing design specification verification on a plurality of circuit units generated after layout and winding in the integrated circuit design file to calculate a plurality of usable areas corresponding to the plurality of power rails;

performing simulation to the circuit units to generate current and voltage analysis so as to judge a plurality of electromigration violations corresponding to the power rails and related current information;

defining a plurality of paths to be corrected on the power rails corresponding to the electromigration violations according to the electromigration violations and the current information;

replacing the types of the plurality of guide holes on the plurality of power rails at the part which is not overlapped with the plurality of paths to be corrected; and

and correcting the number of the plurality of guide holes on the plurality of power rails at the part overlapped with the plurality of paths to be corrected according to the current direction and the positions of the plurality of electromigration violations so as to reduce the number of the plurality of electromigration violations.