CN114861578A - Method, device, equipment and storage medium for repairing hold time violation - Google Patents
Method, device, equipment and storage medium for repairing hold time violation Download PDFInfo
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Abstract
The application provides a method, a device, equipment and a storage medium for repairing hold time violation, and relates to the technical field of integrated circuits. The method comprises the following steps: the method comprises the steps of obtaining a static time sequence analysis result of an integrated circuit, wherein the static time sequence analysis result comprises a retention time parameter and an establishment time margin parameter of each register, determining a plurality of logic units related to a target register from the integrated circuit according to the retention time parameter of each register, determining whether the target register meets a preset condition of the establishment time margin according to the establishment time margin parameter of the target register, replacing the target logic units in the plurality of logic units if the establishment time margin of the target register does not meet the preset condition, modifying the establishment time margin of the target register, and repairing the target register for retention time violation. According to the method and the device, the fact that extra establishment time violation is not introduced when the retention time violation is repaired can be guaranteed, and the efficiency of repairing the retention time violation is improved.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a retention time violation recovery method, apparatus, device, and storage medium.
Background
Timing issues are one of the most interesting issues in the design of integrated circuit chips.
The register is used as a core device of the integrated circuit chip, and in order to ensure the normal operation of the integrated circuit chip, it is necessary to ensure that the setup time and the hold time between the data signal and the clock signal of the register meet the design specifications, that is, the data signal must be prepared in advance before the valid edge of the clock signal arrives, and the data signal also needs to last for a while after the valid edge of the clock signal arrives, so as to ensure that the data can be correctly stored in the register. If the data signal does not last long enough after the arrival of the active edge of the clock signal, a hold time violation will be caused.
The existing hold time violation repairing method mainly inserts an extra buffer into a timing path where a register is located to increase path delay, but if the margin of the setup time of the register is small, the setup time violation may be caused by increasing the path delay by inserting the extra buffer, resulting in a repairing failure.
Disclosure of Invention
An object of the present application is to provide a method, an apparatus, a device, and a storage medium for repairing a retention time violation, so as to ensure that no additional setup time violation is introduced when performing the retention time violation repair, and improve the efficiency of repairing the retention time violation.
In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:
in a first aspect, an embodiment of the present application provides a method for repairing a hold time violation, including:
obtaining a static timing analysis result of an integrated circuit, the static timing analysis result comprising: a parameter of a retention time of each register in the integrated circuit, and a parameter of an established time margin of each register;
determining a plurality of logic units associated with a target register from the integrated circuit according to the parameters of the holding time of each register, wherein the target register is a register with holding time violation;
determining whether the target register meets the preset condition of the establishment time margin or not according to the parameter of the establishment time margin of the target register;
if the building time margin of the target register does not meet the preset condition, replacing a target logic unit in the plurality of logic units to modify the building time margin of the target register;
and repairing the retention time violation of the target register.
Optionally, the determining, from the integrated circuit, a plurality of logic units associated with a target register according to the parameter of the holding time of each register includes:
determining at least one register from the integrated circuit for which a hold time violation exists based on the parameters of the hold times of the respective registers;
determining a register at the end point of a time sequence path from the at least one register as the target register;
and determining that the logic units on the time sequence path where the target register is located are a plurality of logic units associated with the target register.
Optionally, the obtaining a static timing analysis result of the integrated circuit includes:
obtaining the static time sequence analysis results of the integrated circuit under a plurality of process corners;
the determining a plurality of logic units associated with a target register from the integrated circuit according to the parameters of the holding time of each register comprises:
determining a plurality of logic cells associated with the target register from the integrated circuit based on the parameters of the retention time of the respective registers at each process corner.
Optionally, the replacing a target logic unit of the plurality of logic units to modify an establishment time margin of the target register includes:
determining a logic unit with a driving force parameter smaller than a preset driving force parameter threshold value in the plurality of logic units as a first target logic unit;
replacing the first target logic unit with a second target logic unit to increase a setup time margin of the target register, wherein a driving force parameter of the second target logic unit is greater than a driving force parameter of the first target logic unit.
Optionally, the determining that the logic unit with the driving force parameter smaller than the preset driving force parameter threshold value in the plurality of logic units is the first target logic unit includes:
determining a logic unit of the plurality of logic units, wherein the driving force parameter of the buffer unit is smaller than a first preset driving force parameter threshold value, as the first target logic unit; and/or determining a logic unit of which the driving force parameter of a non-buffer unit is smaller than a second preset driving force parameter threshold value in the plurality of logic units as the first target logic unit.
Optionally, the driving force parameter of the second target logic unit is greater than or equal to the preset driving force parameter threshold.
Optionally, the replacing a target logic unit of the plurality of logic units to modify an establishment time margin of the target register includes:
determining a high threshold voltage cell of the plurality of logic cells as a third target logic cell;
replacing the third target logic cell with a standard threshold voltage cell or a low threshold voltage cell to increase a setup time margin of the target register.
Optionally, the replacing a target logic unit of the plurality of logic units to modify an establishment time margin of the target register includes:
determining a standard threshold voltage cell of the plurality of logic cells as a fourth target logic cell;
replacing the fourth target logic cell with a low threshold voltage cell to increase a setup time margin of the target register.
Optionally, the replacing a target logic unit of the plurality of logic units to modify an establishment time margin of the target register includes:
determining a fifth target logic unit from the plurality of logic units according to the channel widths of the plurality of logic units;
replacing the fifth target logic unit with a sixth target logic unit to increase a setup time margin of the target register, wherein a channel width of the sixth target logic unit is less than a channel width of the fifth target logic unit.
In a second aspect, an embodiment of the present application further provides a hold time violation repairing apparatus, where the apparatus includes:
an obtaining module, configured to obtain a static timing analysis result of an integrated circuit, where the static timing analysis result includes: a parameter of a retention time of each register in the integrated circuit, and a parameter of an established time margin of each register;
a determining module, configured to determine, from the integrated circuit, a plurality of logic units associated with a target register according to the parameters of the retention time of each register, where the target register is a register with a retention time violation;
the judging module is used for determining whether the target register meets the preset condition of the establishment time margin according to the parameter of the establishment time margin of the target register;
a replacing module, configured to replace a target logic unit of the plurality of logic units to modify the setup time margin of the target register if the setup time margin of the target register does not satisfy the preset condition;
and the repair module is used for repairing the retention time violation of the target register.
Optionally, the determining module includes:
a register determining unit, configured to determine, from the integrated circuit, at least one register in which a hold time violation exists, according to a parameter of a hold time of the respective register;
a target register determining unit, configured to determine, from the at least one register, a register at a timing path end point as the target register;
and the logic unit determining unit is used for determining the logic units on the time sequence path where the target register is located as a plurality of logic units associated with the target register.
Optionally, the obtaining module is specifically configured to obtain the static timing analysis results of the integrated circuit under multiple process corners;
the determining module is specifically configured to determine, from the integrated circuit, a plurality of logic units associated with the target register according to the parameter of the retention time of each register in each process corner.
Optionally, the replacing module includes:
the first screening unit is used for determining a logic unit with a driving force parameter smaller than a preset driving force parameter threshold value in the plurality of logic units as a first target logic unit;
a first replacement unit configured to replace the first target logic unit with a second target logic unit to increase a setup time margin of the target register, wherein a driving force parameter of the second target logic unit is greater than a driving force parameter of the first target logic unit.
Optionally, the first screening unit is specifically configured to determine, as the first target logic unit, a logic unit, of the plurality of logic units, where a driving force parameter of the buffer unit is smaller than a first preset driving force parameter threshold; and/or determining that the logic unit with the driving force parameter of the non-buffer unit in the plurality of logic units smaller than a second preset driving force parameter threshold value is the first target logic unit.
Optionally, the driving force parameter of the second target logic unit is greater than or equal to the preset driving force parameter threshold.
Optionally, the replacing module includes:
a second screening unit for determining a high threshold voltage unit of the plurality of logic units as a third target logic unit;
a second replacement unit to replace the third target logic unit with a standard threshold voltage unit or a low threshold voltage unit to increase a setup time margin of the target register.
Optionally, the replacing module includes:
a third screening unit, configured to determine that a standard threshold voltage unit in the plurality of logic units is a fourth target logic unit;
a third replacement unit to replace the fourth target logic unit with a low threshold voltage unit to increase a setup time margin of the target register.
Optionally, the replacing module includes:
the fourth screening unit is used for determining a fifth target logic unit from the plurality of logic units according to the channel widths of the plurality of logic units;
a fourth replacement unit, configured to replace the fifth target logic unit with a sixth target logic unit to increase a setup time margin of the target register, where a channel width of the sixth target logic unit is smaller than a channel width of the fifth target logic unit.
In a third aspect, an embodiment of the present application further provides a computer device, including: a memory and a processor, wherein the memory stores a computer program executable by the processor, and the processor implements the holdover time violation fixing method according to any one of the first aspect when executing the computer program.
In a fourth aspect, an embodiment of the present application further provides a storage medium, where a computer program is stored on the storage medium, and when the computer program is read and executed, the method for repairing the hold time violation according to any of the above first aspects is implemented.
The beneficial effect of this application is:
the application provides a method, a device, equipment and a storage medium for repairing a hold time violation, wherein the method comprises the following steps: the method comprises the steps of obtaining a static time sequence analysis result of an integrated circuit, wherein the static time sequence analysis result comprises a parameter of holding time of each register in the integrated circuit and a parameter of a setup time margin of each register, determining a plurality of logic units related to a target register from the integrated circuit according to the parameter of the holding time of each register, wherein the target register is a register with a setup time violation, determining whether the target register meets a preset condition of the setup time margin or not according to the parameter of the setup time margin of the target register, and replacing the target logic units in the plurality of logic units to modify the setup time margin of the target register and repair the setup time violation of the target register if the setup time margin of the target register does not meet the preset condition. When the retention time violation is repaired, the establishment time margin of the target register with the retention time violation is judged, the target register with the establishment time margin not meeting the preset condition is determined, and the target logic unit on the time sequence path where the target register is located is replaced, so that the modified establishment time margin of the target register meets the preset condition, the situation that the design of the whole integrated circuit is overturned due to the introduction of additional establishment time violation in the retention time violation repairing process is avoided, and the efficiency of repairing the retention time violation is improved under the condition that the retention time violation is successfully repaired.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a diagram illustrating a relationship between a data signal and a clock signal in a timing path;
FIG. 2 is a schematic flowchart of a hold time violation recovery method according to a first embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a timing path topology;
FIG. 4 is a schematic flowchart of a second embodiment of a holdover time violation remediation method provided by the present application;
FIG. 5 is a schematic flowchart of a third embodiment of a hold time violation remediation method provided by the present application;
FIG. 6 is a schematic flowchart of a hold time violation recovery method according to a fourth embodiment of the present disclosure;
FIG. 7 is a schematic flowchart of a fifth embodiment of a hold time violation remediation method provided by the present application;
fig. 8 is a schematic flowchart of a sixth embodiment of a hold time violation remediation method provided by the present application;
FIG. 9 is a schematic structural diagram of an embodiment of a hold time violation recovery apparatus provided by the present application;
FIG. 10 is a schematic diagram of an embodiment of a computer device provided herein.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Furthermore, the terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
Before describing in detail the hold-time violation recovery method, apparatus, device, and storage medium provided by the present application, a basic concept in an integrated circuit timing path is described to facilitate a better understanding of the present application.
When analyzing or inspecting the Timing characteristics of an integrated circuit, Static Timing Analysis (Static Timing Analysis) is usually adopted, the purpose of the Static Timing Analysis is to find a circuit critical path which makes the chip Timing ineffective and plays a determining role in the chip performance, all Timing paths existing in the whole integrated circuit are extracted by adopting an exhaustive Analysis method, the propagation delay of signals on the Timing paths is calculated, and whether the Setup Time (Setup Time) and the Hold Time (Hold Time) of the signals meet the Timing requirements or not is checked.
Please refer to fig. 1, which is a diagram illustrating a relationship between a data signal and a clock signal in a timing path. As shown in fig. 1, the Setup Time refers to the Time that the Data signal (Data) must remain stable before the valid edge of the clock signal (CLK) of the register arrives in order for the Data to be correctly written into the register, and if the Time that the Data remains stable before the valid edge of the clock signal arrives is less than the required Setup Time, a Setup Time Violation (Setup Time visibility) occurs.
Hold Time refers to the Time after the arrival of the valid edge of the clock signal of the register that the data signal must remain stable in order for the data to be correctly written to the register, and if the Time after the arrival of the valid edge of the clock signal that the data remains stable is less than the required Hold Time, a Hold Time Violation (Hold Time virtualization) occurs.
The technical solution of the present application will be described in detail by specific examples below.
Referring to fig. 2, a schematic flowchart of a first embodiment of a hold time violation recovery method provided by the present application is shown in fig. 2, where the method includes:
s10: obtaining a static timing analysis result of the integrated circuit, wherein the static timing analysis result comprises: a parameter of a hold time of each register in the integrated circuit, and a parameter of a setup time margin of each register.
In this embodiment, after the placement and routing of various devices in the integrated circuit are completed, it is necessary to verify whether the timing of the integrated circuit is correct through static timing analysis. Generally, a static timing analysis tool or other timing analysis tools may be used to perform timing analysis on each register in the integrated circuit, so as to generate a static timing analysis result of the integrated circuit. Wherein, the static timing analysis result can be output in the form of a static timing analysis report, and the report includes: delay parameters of each register on the timing path, wherein the delay parameter of the current register may include: setup timeT setup Retention time ofT hold Time delay of clock signal to current registerT 1 Delay of clock signal reaching previous stage register of current registerT 2 Delay of memory of previous stage registerT 3 Delay of data signal from previous register to current registerT 4 And the clock period driving the current registerT clk 。
For example, referring to fig. 3, a schematic diagram of a timing path topology is shown, as shown in fig. 3, the timing path includes the following four types: the clock follows a transmit clock path from the clock port input to the clock input (CLK terminal) of the first register FF1, the clock follows a path from the clock input (CLK terminal) of the first register FF1 to the output (Q terminal), the data signal follows a data path from the output of the first register FF1 to the input (D terminal) of the second register FF2, and the clock follows a capture clock path from the clock port input to the clock input (CLK terminal) of the second register FF 2.
T 1 Representing the time taken for a clock edge to be input from the clock port to the clock input (CLK terminal) of the second register,T 2 representing the time taken for a clock edge to be input from the clock port to the clock input (CLK terminal) of the first register,T 3 representing the time taken for a clock edge to travel from the clock input (CLK terminal) to the output (Q terminal) of the first register,T 4 representing the time taken for a data signal to travel from the output of the first register to the input of the second register.
The setup time margin of the current register may be calculated based on the delay parameter of the current register. Illustratively, the setup time margin is calculated (setup_margin) Equation (1) of (a) may be:
setup_margin=(T 1 +T clk -T setup )-(T 2 +T 3 +T 4 ) (1)
s20: a plurality of logic units associated with a target register are determined from the integrated circuit based on the parameters of the hold times of the respective registers, the target register being a register for which the hold time is violated.
In this embodiment, a target register with a hold time violation is determined according to the parameters of the hold time of each register. Specifically, the retention time margin of the register may be calculated according to a delay parameter of the register related to the retention time, and the register having the retention time violation is determined as the target register according to the retention time margin of each register. Wherein the hold time margin of the register with hold time violation is less than 0.
After the target register is determined, a plurality of logic units on a time sequence path are determined according to the time sequence path of the target register in the integrated circuitIs a plurality of logical units associated with the target register. Illustratively, the hold time margin is calculated (hold_margin) Equation (2) of (a) may be:
hold_margin=(T 2 +T 3 +T 4 )-(T 1 +T hold ) (2)
wherein when(T 2 +T 3 +T 4 )>(T 1 +T hold )If the retention time margin is larger than 0, the time sequence of the time sequence path where the register is located meets the time sequence design requirement, and no retention time violation exists; when in use(T 2 +T 3 +T 4 )<(T 1 +T hold )When the holding time margin is less than 0, the fact that the time sequence of the time sequence path where the register is located does not meet the time sequence design requirement is indicated, and the register has holding time violation.
In a possible implementation manner, the manner of obtaining the static timing analysis result of the integrated circuit in S10 may include: obtaining static time sequence analysis results of the integrated circuit under a plurality of process corners; determining a plurality of logic units associated with the target register from the integrated circuit according to the parameters of the holding time of each register in S20 above based on the static timing analysis results in a plurality of process corners may include: a plurality of logic cells associated with the target register are determined from the integrated circuit based on the parameters of the hold times of the respective registers at each process corner.
Specifically, a Process corner (Process corner) refers to a Process deviation in a Process design Process of an integrated circuit, the Process deviation may affect working performance of the integrated circuit, and in order to ensure that the integrated circuit can normally work under various Process corners in a design stage and improve reliability of the integrated circuit, when performing static timing analysis on the integrated circuit, the static timing analysis needs to be performed on the integrated circuit under each Process corner to obtain a static timing analysis result of the integrated circuit under each Process corner. Wherein, the technology angle includes: the delay of the logic unit under the working condition of the slowest process corner is maximum, and the delay of the logic unit under the working condition of the fastest process corner is minimum.
After the static time sequence analysis result under each process corner is obtained, the holding time margin of each register under each process corner can be calculated according to the holding time parameter of each register under each process corner, the register with holding time violation under each process corner is determined as a target register according to the holding time margin of each register, and a plurality of logic units on the time sequence path where the target register is located are determined as a plurality of logic units associated with the target register.
S30: and determining whether the target register meets the preset condition of the setup time margin or not according to the parameters of the setup time margin of the target register.
In this embodiment, if the setup time margin of the register is smaller, the setup time violation may be introduced when the hold time violation is repaired, and therefore, before the hold time violation is repaired, the setup time margin of the target register needs to be determined, and whether the target register meets the preset condition of the setup time margin is determined.
The preset condition for establishing the time margin may be set according to the size of the retention time margin, for example, the retention time margin calculated according to the above formula (2) is-10, because the retention time margin is less than 0, it is determined that there is a retention time violation, and in order to repair the retention time violation, it is required to ensure that the establishment time margin is greater than the preset condition-10, otherwise, the establishment time violation is introduced when the retention time violation is repaired.
S40: and if the building time margin of the target register does not meet the preset condition, replacing the target logic unit in the plurality of logic units to modify the building time margin of the target register.
In this embodiment, if the setup time margin of the target register does not satisfy the preset condition, it indicates that the setup time violation may be caused when the hold time violation is repaired, and in order to avoid introducing the setup time violation when the hold time violation is repaired, the target logic unit satisfying the screening condition may be determined from the plurality of logic units on the time sequence path where the target register is located according to the preset screening condition, and the setup time margin of the target register may be modified by replacing the target logic unit, so that the setup time margin of the target register satisfies the preset condition.
S50: and repairing the target register for the retention time violation.
In this embodiment, after the setup time margin satisfies the preset condition, the static timing analysis tool or another timing analysis tool is used to perform static timing analysis on the integrated circuit again, and if the setup time margin satisfies the preset condition, the setup time violation repair process or tool is used to perform the setup time violation repair on the target register.
In a possible implementation manner, the method for performing hold time violation repair on the target register may be: and calculating the delay required for repairing the retention time violation by adopting a preset retention time violation repairing flow or tool, and inserting at least one buffer with the same delay size on the time sequence path where the target register is positioned to finish the retention time violation repairing.
In the method for repairing the retention time violation provided by the embodiment, when the retention time violation is repaired, the setup time margin of the target register with the retention time violation is judged, the target register with the setup time margin not meeting the preset condition is determined, and the target logic unit on the time sequence path where the target register is located is replaced, so that the modified setup time margin of the target register meets the preset condition, the situation that the design of the whole integrated circuit is overturned due to the introduction of the additional setup time violation in the process of repairing the retention time violation is avoided, and the efficiency of repairing the retention time violation is improved under the condition that the retention time violation is successfully repaired is ensured.
On the basis of the implementation method for maintaining time violation recovery provided in fig. 2, the embodiment of the present application further provides a possible implementation manner of the method for maintaining time violation recovery. Referring to fig. 4, a flowchart of a second embodiment of the hold time violation recovery method provided by the present application is shown in fig. 4, where in the method in S20, determining a plurality of logic units associated with a target register from an integrated circuit according to the parameters of the hold time of each register may include:
s21: at least one register for which a hold time violation exists is determined from the integrated circuit based on the parameters of the hold times of the respective registers.
In this embodiment, the retention time margins of all registers in the integrated circuit are calculated according to the retention time parameters of the registers, and at least one register with a retention time violation is determined according to the retention time margins of the registers.
S22: and determining a register at the end point of the time sequence path from at least one register as a target register.
In this embodiment, each timing path is composed of a plurality of registers and logic units among the plurality of registers, after at least one register having a holdover time violation is determined, for at least one register having a holdover time violation on the same timing path, the holdover time violation of each register is a superposition of all holdover time violations before the register, and all the holdover time violations on the timing path can be covered by using the last register having a holdover time violation on the timing path as a target register.
In a possible implementation manner, after the target registers of the respective timing paths are determined, since the target registers of different timing paths may overlap, duplicate target registers need to be removed, and only one target register needs to be reserved.
S23: and determining the logic units on the time sequence path where the target register is located as a plurality of logic units associated with the target register.
In this embodiment, after the target register is determined, according to the timing path where the target register is located, the logic units that the target register passes through on the timing path are extracted as a plurality of logic units associated with the target register.
In a possible implementation method, multiple logic units associated with different target registers may overlap, and in order to avoid repeated replacement operations when performing replacement of a logic unit, the repeated logic unit may be removed and only one logic unit may be reserved.
In the hold time violation repairing method provided by the above embodiment, after determining that at least one register with a hold time violation exists, a register at the end point of the time sequence path is determined from the at least one register as a target register, so that it is determined that a logic unit on the time sequence path where the target register is located can directly cover logic units associated with all registers with the hold time violation on the time sequence path, that is, the complexity of acquiring the logic units associated with all registers with the hold time violation is avoided, and it is ensured that the acquired logic units are not missed, thereby improving the accuracy of hold time violation repairing.
On the basis of the implementation method for maintaining time violation recovery provided in fig. 2, the embodiment of the present application further provides a possible implementation manner of the method for maintaining time violation recovery. Referring to fig. 5, a flowchart illustrating a third embodiment of a hold time violation repairing method provided by the present application is shown in fig. 5, where in the above method, in S40, replacing a target logic unit of a plurality of logic units to modify an establishment time margin of a target register may include:
s41: and determining a logic unit with the driving force parameter smaller than the preset driving force parameter threshold value in the plurality of logic units as a first target logic unit.
In this embodiment, the static timing analysis result further includes capability parameters of the logic unit, where the capability parameters at least include driving force parameters of the logic unit, and the larger the driving force parameter of the logic unit is, the smaller the delay time brought by the logic unit in the integrated circuit is. In order to increase the setup time margin so that the setup time margin satisfies the predetermined condition, the delay of the logic unit needs to be reduced, and therefore, the logic unit having the driving force parameter smaller than the predetermined driving force parameter threshold may be selected from the plurality of logic units as the first target logic unit according to the driving force parameters of the plurality of logic units. The preset driving force parameter threshold can be set according to the size of the establishment time margin, and if the establishment time margin is smaller, the preset driving force parameter threshold can also be set smaller so as to determine a larger number of first target logic units from the plurality of logic units; if the setup time margin is large, the preset driving force parameter threshold may also be set to be large so as to determine a smaller number of first target logic units from the plurality of logic units.
In one possible implementation manner, the determining, in S41, that the logic unit with the driving force parameter smaller than the preset driving force parameter threshold value is the first target logic unit may include:
and determining a logic unit with the driving force parameter of the buffer unit smaller than a first preset driving force parameter threshold value in the plurality of logic units as a first target logic unit.
Specifically, the buffer logic unit exists in the plurality of logic units and plays a buffering role in the timing path, and may be, for example, a buffer, where the logic buffer unit is configured to buffer a time when the clock signal enters the register on the transmission path of the clock signal, and buffer a time when the data signal enters the register on the transmission path of the data signal, so that a setup time and a hold time of the clock signal and the data signal meet requirements. In this embodiment, a first preset driving force parameter threshold is used as a standard to screen the buffer units in the plurality of logic units, and the buffer unit with the driving force parameter smaller than the first preset driving force parameter threshold is determined as a first target logic unit.
In another possible implementation manner, the determining, in S41, that the logic cell of the plurality of logic cells in which the driving force parameter is smaller than the preset driving force parameter threshold is the first target logic cell may include:
and determining a logic unit of which the driving force parameter of the non-buffer unit is smaller than a second preset driving force parameter threshold value in the plurality of logic units as the first target logic unit.
Specifically, the non-buffered logic unit exists in the plurality of logic units, and performs a logic operation in the timing path, for example, the logic unit may be a gate circuit, and the non-buffered logic unit is configured to perform the logic operation on the data signal in the transmission path of the data signal. In this embodiment, a second preset driving force parameter threshold is used as a standard to screen non-buffer units in the plurality of logic units, and a buffer unit with a driving force parameter smaller than the second preset driving force parameter threshold is determined as a first target logic unit.
It should be noted that, in the embodiment, when determining the first target logic unit, only the buffer unit having the driving force parameter smaller than the first preset driving force parameter threshold may be taken as the first target logic unit, only the non-buffer unit having the driving force parameter smaller than the second preset driving force parameter threshold may be taken as the first target logic unit, both the buffer unit having the driving force parameter smaller than the first preset driving force parameter threshold and the non-buffer unit having the driving force parameter smaller than the second preset driving force parameter threshold may be taken as the second target logic unit, and the selection criterion of the first target logic unit is based on the size of the established time margin. For example, if the setup time margin is small, and the setup time margin is adjusted to a larger adjustment range satisfying the preset condition, the buffer unit having the driving force parameter smaller than the first preset driving force parameter threshold may be selected as the first target logic unit, or both the buffer unit having the driving force parameter smaller than the first preset driving force parameter threshold and the non-buffer unit having the driving force parameter smaller than the second preset driving force parameter threshold may be selected as the second target logic unit; if the setup time margin is large, the setup time margin is adjusted to an adjustment range meeting the preset condition to be small, and then the non-buffer unit with the driving force parameter smaller than the second preset driving force parameter threshold value can be selected as the first target logic unit.
S42: and replacing the first target logic unit with a second target logic unit to increase the setup time margin of the target register, wherein the driving force parameter of the second target logic unit is greater than the driving force parameter of the first target logic unit.
In this embodiment, after a first target logic unit with a driving force parameter smaller than a preset driving force parameter threshold is determined, the first target logic unit is replaced with a second target logic unit with a driving force parameter larger than the first target logic unit, and by increasing the driving force parameter, a delay brought by the second target logic unit in a time sequence path is reduced, so that an establishment time margin of the target register is increased.
In one possible implementation, the driving force parameter of the second target logical unit is greater than or equal to a preset driving force parameter threshold.
Specifically, the buffer unit with the driving force parameter smaller than the first preset driving force parameter threshold is replaced by the buffer unit with the first preset driving force parameter threshold or the buffer unit with the driving force parameter larger than the first preset driving force parameter threshold. And replacing the non-buffer unit with the second preset driving force parameter threshold or the non-buffer unit with the driving force parameter larger than the second preset driving force parameter threshold. Illustratively, the buffer unit having a driving force smaller than X8 is replaced with a buffer unit having a driving force of X8 or larger than X8, and the non-buffer unit having a driving force of X1 is replaced with a buffer unit having a driving force of X2.
In the method for repairing the hold time violation provided in the above embodiment, the first target logic unit with the driving force parameter smaller than the preset driving force parameter threshold is replaced with the second target logic unit with the driving force parameter larger than the first target logic unit, so as to increase the setup time margin of the target register, so that the setup time margin of the target register meets the preset condition, and the setup time violation introduced when the hold time violation is repaired is avoided.
On the basis of the implementation method for maintaining time violation recovery provided in fig. 2, the embodiment of the present application further provides a possible implementation manner of the method for maintaining time violation recovery. Referring to fig. 6, a flowchart illustrating a fourth embodiment of a hold time violation repairing method provided by the present application is shown in fig. 6, where in the method, in S40, replacing a target logic unit of a plurality of logic units to modify an establishment time margin of a target register may include:
s43: and determining a high threshold voltage unit in the plurality of logic units as a third target logic unit.
In this embodiment, the capability parameter of the logic unit may further include a Voltage threshold of the logic unit, and the logic unit is divided into a High threshold Voltage (HVT) unit, a Standard Voltage Technology (SVT) unit, and a Low threshold Voltage (LVT) unit according to different Voltage thresholds, where Voltage thresholds of the High threshold Voltage unit, the Standard threshold Voltage unit, and the Low threshold Voltage unit decrease sequentially. The higher the voltage threshold of the logic unit, the larger the delay brought in the timing path, whereas the lower the voltage threshold of the logic unit, the smaller the delay brought in the timing path.
In order to increase the setup time margin so that the setup time margin satisfies the predetermined condition, the delay of the logic unit needs to be reduced, and therefore, a high threshold voltage unit with a large delay may be determined as the third target logic unit according to the threshold voltages of the plurality of logic units.
S44: replacing the third target logic cell with a standard threshold voltage cell or a low threshold voltage cell to increase a setup time margin of the target register.
In this embodiment, the third target logic unit of the high threshold voltage unit is replaced with the standard threshold voltage unit or the low threshold voltage unit to reduce the delay of the logic unit and increase the setup time margin of the target register. Wherein, whether to replace the high threshold voltage unit with the standard threshold voltage unit or the low threshold voltage unit can be selected according to the size of the time margin. For example, if the setup time margin is small, and the setup time margin is adjusted to a larger adjustment range satisfying the preset condition, the high threshold voltage unit may be selected to be replaced by the low threshold voltage unit, so as to reduce the delay time in a larger range; if the setup time margin is large, the setup time margin is adjusted to a smaller adjustment range meeting the preset condition, and then the high threshold voltage unit can be selected to be replaced by the standard threshold voltage unit so as to narrow the delay in a smaller range.
In an alternative embodiment, another scheme for replacing the logic cell based on its voltage threshold is provided. Referring to fig. 7, a schematic flowchart of a fifth embodiment of a hold time violation recovery method provided by the present application is shown in fig. 7, where in the method, in S40, replacing a target logic unit in a plurality of logic units to modify an establishment time margin of a target register may include:
s45: and determining a standard threshold voltage unit in the plurality of logic units as a fourth target logic unit.
S46: the fourth target logic cell is replaced with a low threshold voltage cell to increase the setup time margin of the target register.
In this embodiment, according to the voltage thresholds of the plurality of logic units, the standard threshold voltage unit is selected as the fourth target logic unit, and the fourth target logic unit of the standard threshold voltage unit is replaced by the low threshold voltage unit, so as to reduce the delay of the logic unit and increase the setup time margin of the target register.
In an optional embodiment, the standard threshold Voltage unit or the Low threshold Voltage unit may be replaced by an Ultra Low Voltage technology (ultt), which is not described herein again.
It should be noted that, according to the size of the setup time margin, whether the high threshold voltage cell is selected as the third target logic cell or the standard threshold voltage cell is selected as the fourth target logic cell may be selected. For example, if the setup time margin is small and the setup time margin is adjusted to a large adjustment range satisfying the preset condition, the high-threshold voltage cell may be selected as the third target logic cell to replace the high-threshold voltage cell with the standard threshold voltage cell or the low-threshold voltage cell; if the setup time margin is large, and the setup time margin is adjusted to a smaller adjustment range meeting the preset condition, the standard threshold voltage unit may be selected as the fourth target logic unit, so as to replace the standard threshold voltage unit with the low threshold voltage unit.
In the method for repairing the retention time violation provided in the above embodiment, the setup time margin of the target register is increased by replacing the high-threshold voltage unit with the standard threshold voltage unit or the low-threshold voltage unit, or replacing the standard threshold voltage unit with the low-threshold voltage unit, so that the setup time margin of the target register meets the preset condition, and the setup time violation introduced when the retention time violation is repaired is avoided.
On the basis of the implementation method for maintaining time violation recovery provided in fig. 2, the embodiment of the present application further provides a possible implementation manner of the method for maintaining time violation recovery. Referring to fig. 8, a flowchart illustrating a sixth embodiment of a hold time violation repairing method provided by the present application is shown in fig. 8, where in the method, in S40, replacing a target logic unit of a plurality of logic units to modify an establishment time margin of a target register may include:
s47: and determining a fifth target logic unit from the plurality of logic units according to the channel widths of the plurality of logic units.
In this embodiment, the capability parameter of the logic unit may further include a channel width of the logic unit, where the wider the channel width of the logic unit, the larger the delay time brought in the timing path, and conversely, the narrower the channel width of the logic unit, the smaller the delay time brought in the timing path. In order to increase the setup time margin so that the setup time margin satisfies the predetermined condition, the delay of the logic unit needs to be reduced, and therefore, the logic unit having a channel width greater than the predetermined width threshold may be determined as the fifth target logic unit from among the plurality of logic units according to the channel widths of the plurality of logic units.
S48: replacing the fifth target logic cell with a sixth target logic cell to increase a setup time margin of the target register, wherein a channel width of the sixth target logic cell is less than a channel width of the fifth target logic cell.
In this embodiment, the fifth target logic unit is replaced with a sixth target logic unit having a channel width smaller than that of the fifth target logic unit, so as to reduce the delay of the logic unit and increase the setup time margin of the target register. For example, logic cells with channel widths of 18 and 20 may be exchanged for logic cells with channel widths of 16.
In the method for repairing the hold time violation provided in the foregoing embodiment, the fifth target logic unit is replaced with the sixth target logic unit having a channel width smaller than that of the fifth target logic unit, so as to increase the setup time margin of the target register, so that the setup time margin of the target register meets the preset condition, and the setup time violation introduced when the hold time violation is repaired is avoided.
Based on any one of the above embodiments, the present application further provides a specific execution step of executing the retention time violation recovery method by the computer device. The performing step may include:
s101: obtaining static time sequence analysis results of the integrated circuit under a plurality of process corners, wherein the static time sequence analysis results comprise: maintaining a time violation report and establishing a time violation report.
S102: the method comprises the steps of extracting a plurality of end point registers with hold time violations under a plurality of process corners, removing repetition points, and naming a file containing the end point registers as a hold time violation register file, for example, the file can be named as Eregs.
S103: the total violated paths for which there is a hold time violation are determined from the hold time violation reports of the plurality of endpoint registers, and the file containing the total violated paths is named the violated paths file, which may be named hold.
S104: rpt extracts all cells in all violation paths in the report hold, and names the file containing all cells as a cell file, which may be named Tcells, for example.
S105: for the time sequence paths including all the units, establishing time violation reports under each process corner are obtained, and a file including the establishing time violation reports is named as an establishing time violation report file, for example, may be named as setup _ margin.
S106: the driving units with crosstalk lines, the non-extremely-low threshold voltage units and the units with wide channel widths in the setup time violation report are extracted, all the driving units are named, for example, Dsi _ cells, all the non-extremely-low threshold voltage units are named, for example, Rcells, and all the units with wide channel widths are named, for example, Bcells.
S107: and outputting instantiation names and type name information of all drive units, all non-ultra-low threshold voltage units and all units with channel widths to form a file drive unit file, a threshold voltage unit file and a channel width unit file respectively, wherein the file drive unit file, the threshold voltage unit file and the channel width unit file can be named as size _ cell _ si.tcl.do, size _ cell _ vt.tcl.do and size _ cell _ b.tcl.do respectively.
S108 a: amplifying the driving force of the driving unit with the crosstalk line, and writing the replacement content into a driving unit script file of a script format recognizable by the layout and wiring tool, which can be named as size _ cell _ si.tcl for example; the specific operation comprises the following steps: for a file drive unit file, the drive unit is divided into a buffer unit and a non-buffer unit, the buffer unit having a driving force lower than X8 is changed to X8, and the non-buffer unit having a driving force of X1 is all changed to X2.
S108 b: reducing the threshold voltage of the threshold voltage unit in the threshold voltage unit file, and writing the replacement content into a threshold voltage script file with a script format recognizable by a layout and routing tool, for example, the script file may be named size _ cell _ vt.tcl; the specific operations may include: aiming at a file threshold voltage unit file, a high threshold voltage unit is changed into a standard threshold voltage unit or a low threshold voltage unit, and the standard threshold voltage unit or the low threshold voltage unit is changed into an ultra-low threshold voltage unit.
S108 c: the cell with wide channel width is changed into the cell with narrow channel width, and the replacement content is written into a channel script file with a script format recognizable by a layout and routing tool, for example, the channel script file can be named as size _ cell _ b.tcl.
S109: and summarizing the drive script file, the threshold voltage script file and the channel script file, and removing the duplication to obtain a new script file, wherein the script file can be named size _ cell.
S110: and (4) making the script file into a database, and after the tool finishes local layout optimization and layout and wiring optimization, performing static time sequence analysis of the retention time again.
S111: and importing the static time sequence analysis result into a tool for repairing the retention time violation, and repairing the retention time violation of the integrated circuit.
S112: judging whether all the holding time violations are repaired or not, and if the holding time violations are repaired, ending the repairing; if the hold time violation still exists, the process returns to S102 to execute again.
S113: and (6) ending.
And automatically issuing an engineering repair command through S101-S113, so that the repair of the retention time violation is automatically completed under the condition that the construction time allowance does not meet the preset condition.
Based on the above method embodiment, the embodiment of the present application further provides a virtual device for the above method embodiment. Referring to fig. 9, a schematic structural diagram of an embodiment of a hold-time violation recovery apparatus provided in the present application is shown in fig. 9, where the apparatus includes:
an obtaining module 11, configured to obtain a static timing analysis result of the integrated circuit, where the static timing analysis result includes: parameters of the retention time of each register in the integrated circuit and parameters of the setup time margin of each register;
a determining module 12, configured to determine, from the integrated circuit, a plurality of logic units associated with a target register according to the parameters of the retention time of each register, where the target register is a register whose retention time is violated;
the judging module 13 is configured to determine whether the target register meets a preset condition of the setup time margin according to the parameter of the setup time margin of the target register;
a replacing module 14, configured to replace a target logic unit in the plurality of logic units if the setup time margin of the target register does not satisfy a preset condition, so as to modify the setup time margin of the target register;
and the repair module 15 is used for repairing the retention time violation of the target register.
Optionally, the determining module 12 includes:
a register determining unit for determining at least one register having a hold time violation from the integrated circuit based on the parameters of the hold time of the respective registers;
the target register determining unit is used for determining a register at the end point of the time sequence path from at least one register as a target register;
and the logic unit determining unit is used for determining the logic units on the time sequence path where the target register is located as a plurality of logic units associated with the target register.
Optionally, the obtaining module 11 is specifically configured to obtain static timing analysis results of the integrated circuit under multiple process corners;
the determining module 12 is specifically configured to determine a plurality of logic units associated with the target register from the integrated circuit according to the parameters of the holding time of each register in each process corner.
Optionally, the replacement module 14 includes:
the first screening unit is used for determining a logic unit with the driving force parameter smaller than a preset driving force parameter threshold value in the plurality of logic units as a first target logic unit;
and a first replacement unit for replacing the first target logic unit with a second target logic unit to increase a setup time margin of the target register, wherein a driving force parameter of the second target logic unit is greater than a driving force parameter of the first target logic unit.
Optionally, the first screening unit is specifically configured to determine, as the first target logic unit, a logic unit, of the plurality of logic units, where the driving force parameter of the buffer unit is smaller than a first preset driving force parameter threshold; and/or determining a logic unit, which is used for determining that the driving force parameter of the non-buffer unit in the plurality of logic units is smaller than a second preset driving force parameter threshold value, as a first target logic unit.
Optionally, the driving force parameter of the second target logic unit is greater than or equal to a preset driving force parameter threshold.
Optionally, the replacement module 14 includes:
the second screening unit is used for determining a high threshold voltage unit in the plurality of logic units as a third target logic unit;
and a second replacement unit for replacing the third target logic unit with a standard threshold voltage unit or a low threshold voltage unit to increase a setup time margin of the target register.
Optionally, the replacement module 14 includes:
the third screening unit is used for determining a standard threshold voltage unit in the plurality of logic units as a fourth target logic unit;
and a third replacement unit for replacing the fourth target logic unit with a low threshold voltage unit to increase a setup time margin of the target register.
Optionally, the replacement module includes:
the fourth screening unit is used for determining a fifth target logic unit from the plurality of logic units according to the channel widths of the plurality of logic units;
and the fourth replacement unit is used for replacing the fifth target logic unit with a sixth target logic unit so as to increase the setup time margin of the target register, wherein the channel width of the sixth target logic unit is smaller than that of the fifth target logic unit.
The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Referring to fig. 10, a schematic diagram of an embodiment of a computer device provided in the present application is shown, where the computer device may be a computing device or a server with a computing processing function.
As shown in fig. 10, the computer apparatus 100 includes: the memory 101 and the processor 102, and the memory 101 and the processor 102 are connected by a bus.
The memory 101 is used for storing programs, and the processor 102 calls the programs stored in the memory 101 to execute the above method embodiments. The specific implementation and technical effects are similar, and are not described herein again.
Optionally, the present application also provides a program product, such as a computer readable storage medium, comprising a program which, when being executed by a processor, is adapted to carry out the above-mentioned method embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (in english: processor) to execute some steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. A hold time violation recovery method is characterized by comprising the following steps:
obtaining a static timing analysis result of an integrated circuit, the static timing analysis result comprising: a parameter of a retention time of each register in the integrated circuit, and a parameter of an established time margin of each register;
determining a plurality of logic units associated with a target register from the integrated circuit according to the parameters of the holding time of each register, wherein the target register is a register with holding time violation;
determining whether the target register meets the preset condition of the establishment time margin or not according to the parameter of the establishment time margin of the target register;
if the building time margin of the target register does not meet the preset condition, replacing a target logic unit in the plurality of logic units to modify the building time margin of the target register;
and repairing the retention time violation of the target register.
2. The method of claim 1, wherein determining from the integrated circuit a plurality of logic cells associated with a target register based on the parameters of the retention times of the respective registers comprises:
determining at least one register from the integrated circuit for which a hold time violation exists based on the parameters of the hold times of the respective registers;
determining a register at the end point of a time sequence path from the at least one register as the target register;
and determining that the logic units on the time sequence path where the target register is located are a plurality of logic units associated with the target register.
3. The method of claim 1, wherein the obtaining static timing analysis results for the integrated circuit comprises:
obtaining the static time sequence analysis results of the integrated circuit under a plurality of process corners;
the determining a plurality of logic units associated with a target register from the integrated circuit according to the parameters of the holding time of each register comprises:
determining a plurality of logic cells associated with the target register from the integrated circuit based on the parameters of the retention time of the respective registers at each process corner.
4. The method of claim 1, wherein the replacing a target logical unit of the plurality of logical units to modify a setup time margin of the target register comprises:
determining a logic unit with a driving force parameter smaller than a preset driving force parameter threshold value in the plurality of logic units as a first target logic unit;
replacing the first target logic unit with a second target logic unit to increase a setup time margin of the target register, wherein a driving force parameter of the second target logic unit is greater than a driving force parameter of the first target logic unit.
5. The method of claim 4, wherein the determining that the logical unit of the plurality of logical units for which the driving force parameter is less than the preset driving force parameter threshold is a first target logical unit comprises:
determining a logic unit of the plurality of logic units, in which the driving force parameter of the buffer unit is smaller than a first preset driving force parameter threshold value, as the first target logic unit; and/or the presence of a gas in the atmosphere,
and determining a logic unit of which the driving force parameter of the non-buffer unit is smaller than a second preset driving force parameter threshold value in the plurality of logic units as the first target logic unit.
6. The method of claim 4, wherein the driving force parameter of the second target logical unit is greater than or equal to the preset driving force parameter threshold.
7. The method of claim 1, wherein the replacing a target logical unit of the plurality of logical units to modify a setup time margin of the target register comprises:
determining a high threshold voltage cell of the plurality of logic cells as a third target logic cell;
replacing the third target logic cell with a standard threshold voltage cell or a low threshold voltage cell to increase a setup time margin of the target register.
8. The method of claim 1, wherein the replacing a target logical unit of the plurality of logical units to modify a setup time margin of the target register comprises:
determining a standard threshold voltage cell of the plurality of logic cells as a fourth target logic cell;
replacing the fourth target logic cell with a low threshold voltage cell to increase a setup time margin of the target register.
9. The method of claim 1, wherein the replacing a target logical unit of the plurality of logical units to modify a setup time margin of the target register comprises:
determining a fifth target logic unit from the plurality of logic units according to the channel widths of the plurality of logic units;
replacing the fifth target logic unit with a sixth target logic unit to increase a setup time margin of the target register, wherein a channel width of the sixth target logic unit is less than a channel width of the fifth target logic unit.
10. A hold time violation remediation device, the device comprising:
an obtaining module, configured to obtain a static timing analysis result of an integrated circuit, where the static timing analysis result includes: a parameter of a retention time of each register in the integrated circuit, and a parameter of an established time margin of each register;
a determining module, configured to determine, from the integrated circuit, a plurality of logic units associated with a target register according to the parameters of the retention time of each register, where the target register is a register with a retention time violation;
the judging module is used for determining whether the target register meets the preset condition of the establishment time margin according to the parameter of the establishment time margin of the target register;
a replacing module, configured to replace a target logic unit of the plurality of logic units to modify the setup time margin of the target register if the setup time margin of the target register does not satisfy the preset condition;
and the repair module is used for repairing the retention time violation of the target register.
11. A computer device, comprising: a memory storing a computer program executable by the processor, and a processor implementing the hold-time violation remediation method of any of claims 1-9 when executing the computer program.
12. A storage medium having stored thereon a computer program which, when read and executed, implements the hold-time violation recovery method of any of claims 1-9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116681011A (en) * | 2023-08-03 | 2023-09-01 | 飞腾信息技术有限公司 | Time violation repairing method and device, computer equipment and storage medium |
| CN117494630A (en) * | 2023-12-29 | 2024-02-02 | 珠海格力电器股份有限公司 | Register time sequence optimization method and device, electronic equipment and storage medium |
| CN117764008A (en) * | 2023-12-27 | 2024-03-26 | 杭州行芯科技有限公司 | Circuit path detection method, electronic device and readable storage medium |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030172361A1 (en) * | 2002-03-06 | 2003-09-11 | You-Ming Chiu | Method for performing multi-clock static timing analysis |
| US20120102448A1 (en) * | 2010-10-25 | 2012-04-26 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Systems, Methods, and Programs for Leakage Power and Timing Optimization in Integrated Circuit Designs |
| CN104881507A (en) * | 2014-02-28 | 2015-09-02 | 国际商业机器公司 | Method and apparatus for repairing hold time violations in circuit |
| US20160380748A1 (en) * | 2015-06-25 | 2016-12-29 | Microsoft Technology Licensing, Llc | Clock domain bridge static timing analysis |
| WO2018076735A1 (en) * | 2016-10-31 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Method and device for repairing hold time violation, and computer storage medium |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN108983870A (en) * | 2017-05-31 | 2018-12-11 | 深圳市中兴微电子技术有限公司 | A kind of time restorative procedure and device |
| CN110598235A (en) * | 2019-06-25 | 2019-12-20 | 眸芯科技（上海）有限公司 | Method and system for repairing time sequence violation in chip design |
| CN111881637A (en) * | 2020-07-08 | 2020-11-03 | 广芯微电子（广州）股份有限公司 | Method, system and storage medium for optimizing power consumption of digital circuit |
| CN112131810A (en) * | 2020-09-29 | 2020-12-25 | 天津飞腾信息技术有限公司 | Method and device for restoring set-up time violation, electronic equipment and readable storage medium |
| CN112232005A (en) * | 2020-09-25 | 2021-01-15 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, equipment and storage medium for repairing hold time violation |
| CN112597739A (en) * | 2020-12-30 | 2021-04-02 | 瓴盛科技有限公司 | Method and apparatus for repairing hold time violations in a circuit |
| CN113781354A (en) * | 2021-09-18 | 2021-12-10 | 北京环境特性研究所 | Image noise point suppression method and device, computing equipment and storage medium |
| WO2022041154A1 (en) * | 2020-08-28 | 2022-03-03 | 华为技术有限公司 | Hold time margin detection circuit |
-
2022
- 2022-07-05 CN CN202210781019.9A patent/CN114861578B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030172361A1 (en) * | 2002-03-06 | 2003-09-11 | You-Ming Chiu | Method for performing multi-clock static timing analysis |
| US20120102448A1 (en) * | 2010-10-25 | 2012-04-26 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Systems, Methods, and Programs for Leakage Power and Timing Optimization in Integrated Circuit Designs |
| CN104881507A (en) * | 2014-02-28 | 2015-09-02 | 国际商业机器公司 | Method and apparatus for repairing hold time violations in circuit |
| US20160380748A1 (en) * | 2015-06-25 | 2016-12-29 | Microsoft Technology Licensing, Llc | Clock domain bridge static timing analysis |
| WO2018076735A1 (en) * | 2016-10-31 | 2018-05-03 | 深圳市中兴微电子技术有限公司 | Method and device for repairing hold time violation, and computer storage medium |
| CN108009055A (en) * | 2016-10-31 | 2018-05-08 | 深圳市中兴微电子技术有限公司 | A kind of method and apparatus for repairing retention time fault |
| CN108983870A (en) * | 2017-05-31 | 2018-12-11 | 深圳市中兴微电子技术有限公司 | A kind of time restorative procedure and device |
| CN108170956A (en) * | 2017-12-28 | 2018-06-15 | 佛山中科芯蔚科技有限公司 | The sequential signing method and device of a kind of retention time |
| CN110598235A (en) * | 2019-06-25 | 2019-12-20 | 眸芯科技（上海）有限公司 | Method and system for repairing time sequence violation in chip design |
| CN111881637A (en) * | 2020-07-08 | 2020-11-03 | 广芯微电子（广州）股份有限公司 | Method, system and storage medium for optimizing power consumption of digital circuit |
| WO2022041154A1 (en) * | 2020-08-28 | 2022-03-03 | 华为技术有限公司 | Hold time margin detection circuit |
| CN112232005A (en) * | 2020-09-25 | 2021-01-15 | 山东云海国创云计算装备产业创新中心有限公司 | Method, system, equipment and storage medium for repairing hold time violation |
| CN112131810A (en) * | 2020-09-29 | 2020-12-25 | 天津飞腾信息技术有限公司 | Method and device for restoring set-up time violation, electronic equipment and readable storage medium |
| CN112597739A (en) * | 2020-12-30 | 2021-04-02 | 瓴盛科技有限公司 | Method and apparatus for repairing hold time violations in a circuit |
| CN113781354A (en) * | 2021-09-18 | 2021-12-10 | 北京环境特性研究所 | Image noise point suppression method and device, computing equipment and storage medium |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116681011A (en) * | 2023-08-03 | 2023-09-01 | 飞腾信息技术有限公司 | Time violation repairing method and device, computer equipment and storage medium |
| CN116681011B (en) * | 2023-08-03 | 2023-11-07 | 飞腾信息技术有限公司 | Time violation repairing method and device, computer equipment and storage medium |
| CN117764008A (en) * | 2023-12-27 | 2024-03-26 | 杭州行芯科技有限公司 | Circuit path detection method, electronic device and readable storage medium |
| CN117494630A (en) * | 2023-12-29 | 2024-02-02 | 珠海格力电器股份有限公司 | Register time sequence optimization method and device, electronic equipment and storage medium |
| CN117494630B (en) * | 2023-12-29 | 2024-04-26 | 珠海格力电器股份有限公司 | Register time sequence optimization method and device, electronic equipment and storage medium |
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