JP4549935B2 - Semiconductor integrated circuit design support system and program - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit design support system for designing a semiconductor integrated circuit without problems and a program for causing a computer to execute this function.

  Conventionally, in semiconductor integrated circuit design, a flip-flop with a reset or set terminal (hereinafter referred to as FF with reset) is referred to as a flip-flop without reset or set terminal (hereinafter referred to as FF without reset) to reduce the number of LSI gates and improve layout. May be replaced). For example, Patent Document 1 describes that a place where no problem occurs is replaced with a resetless FF.

  However, the conventional semiconductor integrated circuit design represented by Patent Document 1 does not consider the length of the reset period. For this reason, if the reset period is too short, an undefined value may not be lost in the FF without reset after the initial reset release at the time of executing the gate level simulation. In such a case, the result of the RTL (Register Transfer Level) simulation is inconsistent and the analysis becomes very difficult. Conventionally, a designer who is familiar with the target circuit has dealt with such a problem by searching for an indefinite value occurrence location and manually replacing the FF without reset at that location with a FF with reset. .

JP-A-10-97557

  In conventional semiconductor integrated circuit design, a designer who is familiar with the target circuit needs to replace it with an FF with reset while considering that indefinite values do not propagate for all FFs. Without it, the work was difficult. In addition, this work requires a considerable amount of time even for a designer who is familiar with the target circuit. In addition, there is a case where an erroneous replacement is performed due to manual work, and in such a case, there is a problem that more time is spent for the analysis.

  Further, when the design is performed from the initial stage of the design, the designer may be able to cope with it without spending a comparatively excessive time. However, when using a circuit block that has already been completed to some extent, for example, accepting a circuit block of another department or another company, especially a design department not familiar with LSI design, or diverting a circuit block used in past development, etc. Then, it is very difficult for the above-mentioned correction work to be performed by the design party or the receiving department.

  The present invention has been made to solve the above-described problems, and a semiconductor integrated circuit design support system capable of automatically extracting a place where indefinite value propagation occurs after canceling the initial reset of the design circuit and its function An object of the present invention is to obtain a program for causing a computer to execute.

  Another object of the present invention is to provide a semiconductor integrated circuit design support system capable of automatically detecting a reset period length in which undefined value propagation does not occur and a program for causing a computer to execute this function.

  Another object of the present invention is to obtain a semiconductor integrated circuit design support system capable of automatically correcting a place where indefinite value propagation occurs and a program for causing a computer to execute this function.

The semiconductor integrated circuit design support system according to the present invention sequentially connects the connection destinations of the components in the circuit to be designed, and connects them continuously without using a flip-flop provided with an input terminal for a reset signal or set signal. Reset signal or set signal input terminal that causes indefinite value propagation that occurs after initial reset release , based on the relationship between the number of flip-flop stages that do not have a reset signal or set signal input terminal and the number of clock stages corresponding to the reset period An indeterminate value generation FF detection means for detecting a flip-flop having no signal is provided.

  According to the present invention, the reset signal or the set signal connected continuously without following the flip-flop provided with the input terminal of the reset signal or the set signal by sequentially tracing the connection destinations of the components in the circuit to be designed. Indeterminate value generation that detects flip-flops that do not have reset signal or set signal input terminals that cause indefinite value propagation, based on the relationship between the number of flip-flop stages that do not have an input terminal and the number of clock stages corresponding to the reset period Since the FF detection means is provided, it is possible to easily find a defective part even if the designer is not familiar with the design target circuit.

Embodiment 1 FIG.
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit design support system according to Embodiment 1 of the present invention and a circuit configuration of a design support target. A target circuit 100 is a target semiconductor integrated circuit that is supported by the semiconductor integrated circuit design support system according to the first embodiment, and includes input ports 101 and 102, an output port 103, a flip-flop (denoted as FF in the figure). 1 to 9 and combinational circuits 1 to 10 (denoted as C1 to C10 in the figure). Hereinafter, the flip-flops 1 to 9 are referred to as FF1 to 9 and the combinational circuits 1 to 10 are referred to as C1 to C10.

  The input ports 101 and 102 are signal input ports from the outside of the target circuit 100, and the output port 103 is a signal output port to the outside of the target circuit 100. Of FF1 to FF9, FF1, FF5, and FF7 are flip-flops with reset or set terminals, and the others are flip-flops without reset or set terminals. C1 to C10 are combinational circuits that do not include FFs and latches.

  Here, the flip-flop having no reset or set terminal is a flip-flop in which an input terminal for inputting an external reset signal or an input terminal for inputting an external set signal is not provided. The flip-flop with a reset or set terminal is a flip-flop provided with an input terminal for inputting an external reset signal or an input terminal for inputting an external set signal. It is set to a reset or set state by a signal. In the following description, the flip-flop without reset or set terminal is abbreviated as FF without reset, and the flip-flop with reset or set terminal is abbreviated as FF with reset.

  C1 is connected to the input port 101, and is connected in turn to FF1, C2, FF2, C3, FF3, C4, FF4, C5, FF5, C6, FF6, C7, FF7, C8, FF8, C9, FF9, and C10. The output of C10 is connected to the output port 103. The input port 102 is connected to C5. Further, the output of FF7 is connected to the input side of C7, and FF7 constitutes a self-loop circuit.

  The indeterminate value generation FF detection means 1 constituting the semiconductor integrated circuit design support system according to the first embodiment has a function of specifying an unreset FF that causes indefinite value propagation to the target circuit 100. A reset period stage number counting means 2 and a non-reset FF detecting means 3 are provided. The reset period stage number counting means 2 has a function of counting the number of stages of the non-reset FFs continuously up to the number of clocks in the reset period. The non-reset FF detection means 3 has a function of detecting the non-reset FF and the input port in the target circuit 100.

  In the indefinite value generation FF detection means 1, the non-reset FF detection means 3 sequentially traces the connection destinations of the components of the target circuit 100 to detect the number of consecutive stages of the non-reset FF, and the reset period stage number count means 2 The number of stages is counted up to the number of stages in the reset period, and when the non-reset FFs are continuously connected, the non-reset FFs are identified as non-reset FFs causing indefinite value propagation.

  The indefinite value generation FF detection means 1, the reset period stage count counting means 2 and the non-reset FF detection means 3 described above allow the CPU to read the semiconductor integrated circuit design support program according to the present invention and control its operation. It can be realized on the computer as a specific means cooperating with hardware such as memory. In addition, information related to the connection relationship between the components of the target circuit 100 is stored, for example, in a storage device equipped in the computer, and is appropriately read and used by the above means.

  In the following description, the configuration and basic functions of a computer that embodies the semiconductor integrated circuit design support system of the present invention can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. Since it is not directly related to the essence of the present invention, detailed description is omitted.

Next, the operation will be described.
FIG. 2 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the first embodiment.
First, the non-reset FF detection means 3 in the indeterminate value generation FF detection means 1 detects all the non-reset FFs or input ports (step ST1). In the example of FIG. 1, the FF detection means 3 without reset inputs information about the components of the target circuit 100 described in a netlist, hardware description language, and the like and their connection relations, and the FF2 that is an FF without reset, FF3, FF4, FF6, FF8, FF9 and input ports 101 and 102 are detected.

  Here, a case where FF2 is detected by the FF detecting means 3 without reset will be described as an example. In this case, the non-reset FF detection means 3 sequentially follows the connection destination of the FF2 output, detects the non-reset FF (corresponding to FF3 and FF4) in the middle, and notifies the reset period stage number count means 2 . At this time, the reset period stage number counting unit 2 counts the number of the reset period FF detecting unit 3 every time the non-reset FF detecting unit 3 detects the non-reset FFs. The process so far corresponds to step ST2.

  Further, the reset period stage number counting means 2 counts up to the number of clocks corresponding to the reset period set in the target circuit 100, and the FF detection means 3 without reset causes the FF with reset or output port until the reset period stage number is reached. Is detected (step ST3). At this time, if the resetless FF detection unit 3 detects the FF with reset or the output port, the process proceeds to step ST6 to analyze the next path.

  If no FF with reset or output port is detected within the number of stages in the reset period in step ST3, the process proceeds to step ST4. In step ST4, the reset period stage number counting means 2 determines whether or not the reset period stage number has been reached. At this time, if the number of reset period stages has not been reached, the process returns to step ST2, and the processes from step ST2 to step ST4 are repeatedly executed. If the reset period stage number has been reached, the process proceeds to step ST5.

  Assuming that the reset period given to the target circuit 100 is 3 clocks or more, the reset period stage number counting means 2 is an FF with reset by the non-reset FF detecting means 3 before counting “3” from the FF2. FF5 is detected. The reset period stage number counting means 2 determines that indefinite value propagation does not occur in this path at this time, completes the analysis of this path, and proceeds to step ST6. If the reset period given to the target circuit 100 is less than 3 clocks, the process proceeds to step ST4.

  For example, if the reset period given to the target circuit 100 is 2 clocks, the process proceeds to step ST5 when the reset period stage number counting means 2 counts “2”. In step ST5, the reset period stage number counting means 2 causes the indefinite value propagation to occur in the FF4 which is the reset-free FF where the stage number "2" is counted after the FF2 is detected by the resetless FF detection means 3. And output as a detection result.

  In this way, detection of the non-reset FF that causes indefinite value propagation is completed for this path. Subsequently, the process proceeds to step ST6, and the processing from step ST1 to step ST5 is repeatedly performed for all corresponding paths in the target circuit 100 in the same manner as described above. By the operation so far, the detection of the non-reset FF causing the indefinite value propagation is performed for all the paths of the target circuit 100, and the processing is completed (step ST7).

  In the above description, an FF having an input terminal for an asynchronous reset signal has been described. However, in the case of an FF having an input terminal for a synchronous reset signal, it is necessary to execute in advance by adding one clock to the reset period. is there.

  Moreover, although the case where it implements about all FFs without reset by step ST6 was shown in the example mentioned above, about the FF without reset searched once, it memorize | stored in the memory | storage device of the computer which implement | achieves the said apparatus, and it overlapped It may be configured to reduce the execution time by omitting the inspection.

  As described above, according to the first embodiment, the non-reset FF that causes indefinite value propagation is detected for the target circuit 100 including the non-reset FF based on the connection relationship of the non-reset FF in the circuit. Indefinite value generation FF detecting means 1 is provided, so that, for example, even when outputting in a net list of a semiconductor integrated circuit or a hardware description language, the cause of indefinite value propagation occurring promptly without bothering the designer FF without reset can be detected.

  Further, according to the first embodiment, the indeterminate value generation FF detection means 1 is detected by all reset FFs or non-reset FF detection means 3 for detecting input ports and the non-reset FF detection means 3. The FFs without reset connected to the number of stages exceeding the number of clocks corresponding to the determined reset period until the next FF with reset or the output port of the target circuit is reached in order. Since the reset period stage number counting means 2 that identifies the cause of the malfunction is provided, it is possible to easily and reliably detect the non-reset FF that causes the indefinite value propagation to occur.

  Furthermore, according to the first embodiment, the program that causes the computer to function as the indeterminate value generation FF detection means 1 can quickly detect the reset-free FF that causes the indeterminate value propagation to occur without bothering the designer. A semiconductor integrated circuit design support system capable of detection can be realized on a computer.

  Furthermore, according to the first embodiment, there is no reset which causes an indefinite value propagation to occur easily and reliably by a program that causes the computer to function as the resetless FF detection unit 3 and the reset period stage number counting unit 2. A semiconductor integrated circuit design support system capable of detecting FF can be realized on a computer.

Embodiment 2. FIG.
In the second embodiment, a reset permissible period that is a minimum reset period in which indefinite value propagation does not occur is detected.

  FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit design support system according to Embodiment 2 of the present invention and a circuit configuration of a design support target. The target circuit 100 has the same configuration as that of the first embodiment, and redundant description is omitted. The reset permissible period detecting means 4 constituting the semiconductor integrated circuit design support system according to the second embodiment has a function of detecting a reset period that does not cause indefinite value propagation in the target circuit 100. The FF stage number counting means 5, A resetless FF detection means 3 and a longest FF stage number storage means 6 are provided.

  The FF stage number counting means 5 has a function of counting the number of connected stages of FFs without reset until reaching the FF with reset or the output port. The non-reset FF detection means 3 has a function of detecting a non-reset FF and an input port in the target circuit 100. The longest FF stage number storage means 6 has a function of holding the value counted by the FF stage number counting means 5 and rewriting it to the maximum value (longest value). For example, a configuration in which the longest FF stage number is stored using a memory or a register mounted on a computer that embodies the semiconductor integrated circuit design support system according to the second embodiment is conceivable.

  In the reset allowable period detection means 4, the non-reset FF detection means 3 traces the components of the target circuit 100 in the order of connection to detect the number of FF stages without reset in all paths, and the FF stage number count means 5 detects the longest FF stage number storage means. 6 is detected as the minimum reset period length in which indefinite value propagation does not occur.

  The non-reset FF detecting means 3, the reset permissible period detecting means 4, the FF stage number counting means 5, and the longest FF stage number storing means 6 read the semiconductor integrated circuit design support program according to the present invention into a computer and perform the operation thereof. By controlling, it can be realized on the computer as specific means in cooperation with hardware such as a CPU and a memory. In addition, information related to the connection relationship between the components of the target circuit 100 is stored, for example, in a storage device equipped in the computer, and is appropriately read and used by the above means.

  In the following description, the configuration and basic functions of a computer that embodies the semiconductor integrated circuit design support system of the present invention can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. Since it is not directly related to the essence of the present invention, detailed description is omitted.

Next, the operation will be described.
FIG. 4 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the second embodiment, and the same step numbers are assigned to the same processes as those in the first embodiment.
First, the resetless FF detection means 3 detects all the resetless FFs or input ports in the same manner as in the first embodiment (step ST1). In the example of FIG. 3, the FF detection means 3 without reset inputs information about the components of the target circuit 100 described in a netlist, hardware description language, and the like and their connection relations, and the FF2 that is an FF without reset, FF3, FF4, FF6, FF8, FF9 and input ports 101 and 102 are detected.

  Here, a case where FF2 is detected by the FF detecting means 3 without reset will be described as an example. In this case, the non-reset FF detection means 3 sequentially tracks the connection destination of the FF2 output, and detects a non-reset FF (FF3, FF4 is equivalent) in the middle. At this time, the FF stage number counting means 5 counts the number each time the non-reset FF detection means 3 detects the non-reset FF. The process so far corresponds to step ST2.

  Further, the FF stage number counting means 5 determines whether or not the non-reset FF detecting means 3 has detected an FF with reset or an output port (step ST21). At this time, if the FF with reset or the output port is not detected by the FF detection means 3 without reset, the process returns to step ST2, and the FF stage number counting means 5 counts the FF without reset detected by the FF detection means 3 without reset. Continue.

  On the other hand, when the FF with reset or the output port is detected by the FF detection means 3 without reset, the FF stage count means 5 stores the count value when the FF with reset or output port is reached in the longest FF stage storage means 6. (Step ST22). In the example of FIG. 3, FF 5 is detected as FF with reset after FF 2 is detected, and FF 2, FF 3, and FF 4 detected by FF detection means 3 without reset until that time are not reset by FF stage number counting means 5. The count value “3” is sequentially counted as FF and stored in the longest FF stage number storage means 6.

  Subsequently, the process proceeds to step ST23, and the processes up to step ST1, step ST2, step ST21, and step ST22 are repeated for all corresponding paths in the target circuit 100 in the same manner as described above.

  In the implementation after the second pass, the count value is not simply stored in the longest FF stage number storage unit 6 in step ST22, but is larger than the value stored in the longest FF stage number storage unit 6. Only the longest FF stage number storage means 6 stores (rewrites). In the example of FIG. 3, after the FF 6 in the next path is detected as the FF without reset, the FF 7 that is the FF with reset is detected without detecting the other FF without reset. As a result, the count value by the FF stage number counting means 5 is “1”, and does not exceed the count value “3” in the previous pass, so that it is not stored in the longest FF stage number storage means 6. Similarly, in this next pass, the count value by the FF stage number counting means 5 is “2”, so this count value is not stored in the longest FF stage number storage means 6.

  When the implementation is completed for all the paths, the final value stored in the longest FF stage number storage means 6 is the maximum value (longest path stage number). At this time, the reset permissible period detection unit 4 embodies the system according to the second embodiment by setting the maximum value stored in the longest FF stage number storage unit 6 as the minimum reset period length in which indefinite value propagation does not occur. The information is displayed on the display device of the computer (step ST24). In the example of FIG. 3, the longest FF stage number storage means 6 stores a count value “3” as the maximum value. As a result, the reset permissible period detecting means 4 displays on the display device that the minimum reset period length in which the indefinite value propagation does not occur in the target circuit 100 is 3 clocks, and completes the process (step ST7).

  In the above description, the FF having the asynchronous reset signal input terminal is described. However, in the case of the FF having the synchronous reset signal input terminal, the reset allowable period detecting means 4 stores the longest FF stage number. “1” is added to the maximum value stored in the means 6 and displayed on the display device.

  As described above, according to the second embodiment, all the non-reset FFs or the non-reset FF detection means 3 that detects the non-reset FFs by sequentially tracing the connection destinations after the input port, and the next reset FF stage number counting means 5 that counts the number of FF stages detected by the non-reset FF detection means 3 until reaching the output port of the FF or the target circuit, and the longest FF stage number storage that stores the maximum value counted by the FF stage number counting means 5 The reset allowable period detection unit 4 detects the maximum value, which is the number of consecutive non-reset FF stages stored in the longest FF stage number storage unit 6, as the minimum reset period length that does not cause indefinite value propagation. Therefore, the minimum reset period length that does not cause indefinite value propagation does not occur even if you are not the designer and do not perform simulation. It can easily grasp, it is possible to quickly determine directly whether incorporated or the like to the system as IP. As a result, the designer can extend the reset period of the system so that indefinite value propagation does not occur.

  Further, according to the second embodiment, the program that causes the computer to function as the non-reset FF detecting means 3, the reset permissible period detecting means 4, the FF stage number counting means 5, and the longest FF stage number storing means 6 can be easily and reliably performed. It is possible to realize on a computer a semiconductor integrated circuit design support system capable of grasping a minimum reset period length in which undefined value propagation does not occur.

Embodiment 3 FIG.
In the third embodiment, a reset permissible period, which is a minimum reset period in which indefinite value propagation does not occur, is detected, and the number of corresponding portions for each period is stored and provided to the designer.

  FIG. 5 is a diagram showing a configuration of a semiconductor integrated circuit design support system and a circuit configuration of a design support target according to the third embodiment of the present invention. The target circuit 100 has the same configuration as that of the first and second embodiments, and redundant description is omitted. The reset permissible period detection means 4A constituting the semiconductor integrated circuit design support system according to the third embodiment has the same basic configuration as that of the second embodiment, but has a different content from the longest FF stage number storage means 6. The difference is that the number of FF stage corresponding number storage means 7 is provided.

  The reset permissible period detecting means 4A has a function of detecting a reset period that does not cause indefinite value propagation in the target circuit 100. The FF stage number counting means 5, the non-reset FF detecting means 3, and the FF stage number corresponding number storage means 7 It has. The FF stage number counting means 5 has a function of counting the number of connected stages of FFs without reset until reaching the FF with reset or the output port. The non-reset FF detection means 3 has a function of detecting a non-reset FF and an input port in the target circuit 100.

  The FF stage number corresponding number storage means 7 has a function of holding all the values counted by the FF stage number counting means 5 and simultaneously storing the corresponding number of the values. For example, this corresponds to the number of FF stages not reset and the number of FF stages counted by the FF stage number counting means 5 using a memory or a register mounted on a computer that embodies the semiconductor integrated circuit design support system according to the third embodiment. A configuration for storing the number of locations is conceivable.

  The reset permissible period detection means 4A detects the number of FF stages without reset of all paths by tracing the components of the target circuit 100 in the order of connection by the FF detection means 3 without reset and the FF stage count counting means 5 and corresponds to the number of FF stages. A reset permissible period corresponding to the number of stages of the non-reset FF stored in the number storage means 7 and the number of locations corresponding to this reset permissible period (the number of FF stages) are detected.

  The non-reset FF detecting means 3, the reset permissible period detecting means 4A, the FF stage number counting means 5, and the FF stage number corresponding number storage means 7 read the semiconductor integrated circuit design support program according to the present invention into a computer and the operation thereof By controlling the above, it can be realized on the computer as specific means in cooperation with hardware such as a CPU and a memory. In addition, information related to the connection relationship between the components of the target circuit 100 is stored, for example, in a storage device equipped in the computer, and is appropriately read and used by the above means.

  In the following description, the configuration and basic functions of a computer that embodies the semiconductor integrated circuit design support system of the present invention can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. Since it is not directly related to the essence of the present invention, detailed description is omitted.

Next, the operation will be described.
FIG. 6 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the third embodiment. The same step numbers are assigned to the same processes as those in the second embodiment.
First, the resetless FF detection means 3 detects all the resetless FFs or input ports in the same manner as in the first embodiment (step ST1). In the example of FIG. 5, the FF detection means 3 without reset inputs information on the components of the target circuit 100 described in a netlist, hardware description language, and the like and the connection relationship thereof, and the FF2 that is an FF without reset, FF3, FF4, FF6, FF8, FF9 and input ports 101 and 102 are detected.

  Here, a case where FF2 is detected by the FF detecting means 3 without reset will be described as an example. In this case, the non-reset FF detection means 3 sequentially tracks the connection destination of the FF2 output, and detects a non-reset FF (FF3, FF4 is equivalent) in the middle. At this time, the FF stage number counting means 5 counts the number each time the non-reset FF detection means 3 detects the non-reset FF. The process so far corresponds to step ST2.

  Further, the FF stage number counting means 5 determines whether or not the non-reset FF detecting means 3 has detected the FF with reset or the output port (step ST21). At this time, if the FF with reset or the output port is not detected by the FF detection unit 3 without reset, the process returns to step ST2, and the FF stage number counting unit 5 counts the FF without reset detected by the FF detection unit 3 without reset. Continue.

  On the other hand, when the FF with reset or the output port is detected by the FF detection means 3 without reset, the FF stage number counting means 5 calculates the count value when the FF with reset or the output port is reached and the number of the count values as the number of FF stages. The number is stored in the corresponding number storage means 7 (step ST31). In the example of FIG. 5, FF 5 is detected as FF with reset after FF 2 is detected, and FF 2, FF 3, and FF 4 detected by FF detection means 3 without reset until that time are not reset by FF stage number counting means 5. Counted sequentially as FFs, the count value “3” and the cumulative number of path lengths “3” (here, “first” for initial execution) are stored in the FF stage number corresponding number storage means 7. .

  As described above, in step ST31, unlike the second embodiment, the count values of all paths and the number of corresponding points accumulated for each count value are stored in the FF stage number corresponding number storage means 7. Subsequently, the process proceeds to step ST23, and the processes up to step ST1, step ST2, step ST21, and step ST31 are repeatedly performed for all corresponding paths in the target circuit 100 in the same manner as described above.

  When the implementation is completed for all paths, the reset permissible period detection unit 4A sets the count value of each path stored in the FF stage number corresponding number storage unit 7 as the minimum reset period length in which indefinite value propagation does not occur in the path. Along with this, the number of corresponding points accumulated for each count value is displayed as a list on a display device of a computer that embodies the system according to the second embodiment (step ST32). For example, in the case of the target circuit 100 in FIG. 5, “3 clocks: 1 place, 2 clocks: 1 place, 1 clock: 2 places” are displayed.

  Thereby, the reset permissible period detecting unit 4A displays the reset period length in which indefinite value propagation does not occur and the number of corresponding portions for each period length for all paths in the target circuit 100 and completes the process (step ST7). ).

  In the above description, the FF having the asynchronous reset signal input terminal is described. However, in the case of the FF having the synchronous reset signal input terminal, the reset allowable period detection means 4A corresponds to the number of FF stages. “1” is added to each count value stored in the number storage means 7 and displayed on the display device.

  As described above, according to the third embodiment, all reset-free FFs, or no reset until reaching the output port of the target circuit 100 by sequentially tracing the connection destinations after the input port. FF detection means 3 without reset for detecting the FF, FF stage number counting means 5 for counting the number of FF stages detected by the non-reset FF detection means 3 until the next FF with reset or the output port of the target circuit, FF FF stage number corresponding number storage means 7 for storing the value counted by the stage number counting means 5 and the corresponding number of places for each value, and the reset allowable period detecting means 4A is stored in the FF stage number corresponding number storage means 7. Detects the number of FF stages without reset for each path as the minimum reset period length that does not cause indefinite value propagation, and the corresponding location Since also detects, since it is easy to see the reset period length indefinite propagation does not occur and the number of the pertinent portions thereof, or to revise the target circuit, helps when determining prolong the reset period of the system.

  Further, according to the third embodiment, the program for causing the computer to function as the non-reset FF detection means 3, the reset permissible period detection means 4A, the FF stage number count means 5 and the FF stage number corresponding number storage means 7 causes an indefinite value. A semiconductor integrated circuit design support system in which the length of the reset period in which propagation does not occur and the number of corresponding locations can be easily understood can be realized on a computer.

Embodiment 4 FIG.
In the fourth embodiment, the FF with no reset that causes the occurrence of indefinite value propagation is detected and replaced with the FF with reset to automatically correct the place where the indefinite value propagation occurs.

  FIG. 7 is a diagram showing the configuration of a semiconductor integrated circuit design support system according to Embodiment 4 of the present invention and the circuit configuration of a design support target. The target circuit 100 has the same configuration as that of the first embodiment, and redundant description is omitted. The indeterminate value generation FF replacement means 8 constituting the semiconductor integrated circuit design support system according to the fourth embodiment has a function of identifying an unreset FF that causes indefinite value propagation in the target circuit 100 and replacing it with an FF with reset. It has a reset period stage number counting means 2, a non-reset FF detecting means 3, and a non-reset FF replacing means 9.

  The reset period stage number counting means 2 and the non-reset FF detecting means 3 are the same as those in the first embodiment, and the description thereof is omitted. The resetless FF replacement means 9 has a function of replacing the resetless FF with the resetting FF and connecting the input of the reset signal.

  The indefinite value generation FF replacement means 8 detects the number of FF stages without reset by tracing the components of the target circuit 100 in the order of connection by means of the reset period stage count counting means 2 and the non-reset FF detection means 3. Counts the number of stages up to the number of stages in the reset period, and when FFs without reset are connected continuously, the FF without reset is detected as a FF without reset that causes indefinite value propagation, and FF without reset is replaced. The means 9 is controlled to replace the detected non-reset FF with the reset FF and connect the input of the reset signal.

  The above-described reset period stage number counting means 2, non-reset FF detecting means 3 and indeterminate value generation FF replacing means 8 read the semiconductor integrated circuit design support program according to the present invention into a computer and control its operation to control the CPU. It can be realized on the computer as a specific means cooperating with hardware such as memory. In addition, information related to the connection relationship between the components of the target circuit 100 is stored, for example, in a storage device equipped in the computer, and is appropriately read and used by the above means.

  In the following description, the configuration and basic functions of a computer that embodies the semiconductor integrated circuit design support system of the present invention can be easily recognized by those skilled in the art based on the common general technical knowledge in the technical field. Since it is not directly related to the essence of the present invention, detailed description is omitted.

Next, the operation will be described.
FIG. 8 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the fourth embodiment. Here, the same processing steps as those in the first embodiment are given the same step numbers, and the operations from step ST1 to step ST4 are the same as those in the first embodiment, so that the duplicated explanation is omitted. .

  In step ST4, the reset period stage number counting means 2 determines whether or not the reset period stage number has been reached. At this time, if the number of reset period stages has been reached, the process proceeds to step ST41.

  In step ST41, the indefinite value generation FF replacement unit 8 detects a resetless FF that causes indefinite value propagation, and controls the resetless FF replacement unit 9 to replace the detected resetless FF with a reset FF. Connect the reset signal input.

  For example, if the reset period is 2 clocks, the reset period stage number counting means 2 proceeds to step ST41 when “2” is counted. In step ST41, the indefinite value generation FF replacement means 8 detects the FF4 which is the FF without reset at the point where the reset period stage number counting means 2 has counted "2" after the FF2 is detected by the reset FF detection means 3. Detected as non-reset FF causing indefinite value propagation.

  Thereafter, the indefinite value generation FF replacement unit 8 replaces the detected non-reset FF 4 with the reset FF by controlling the non-reset FF replacement unit 9. For example, when the connection circuit of the corresponding circuit is described in the net list, the non-reset FF cell is replaced with a reset FF, and a reset signal input is connected to the reset terminal. Similarly, when the corresponding circuit is described in a hardware description language, the description of the FF without reset is similarly rewritten to the description of the FF with reset.

  When the indeterminate value propagation countermeasure for one path is completed in this way, the indeterminate value generation FF replacement unit 8 similarly repeats steps ST1 to ST41 for all corresponding paths in the target circuit 100. Implement (step ST6). With the operations up to this point, in all paths of the target circuit 100, the non-reset FFs that need countermeasures against indefinite value propagation are replaced with the FFs with resets, and the process is completed (step ST7).

  As described above, according to the fourth embodiment, for a target circuit 100 including an unreset FF, an unreset FF in which indefinite value propagation occurs based on a connection relationship of the unreset FF in the circuit is reset to an FF with reset. Indeterminate value generation FF replacement means 8 is automatically provided for the indeterminate value propagation, so that, for example, even when outputting in a semiconductor integrated circuit netlist or hardware description language, indefinite value propagation occurs quickly without bothering the designer. Can be generated.

  Further, according to the fourth embodiment, a program that causes a computer to function as the indeterminate value generation FF replacement means 8 can quickly generate a circuit in which indefinite value propagation does not occur without bothering the designer. A semiconductor integrated circuit design support system can be realized on a computer.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the semiconductor integrated circuit design support system by Embodiment 1 of this invention, and the circuit structure of a design support object. 3 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the first embodiment. It is a figure which shows the structure of the semiconductor integrated circuit design support system by Embodiment 2 of this invention, and the circuit structure of a design support object. 6 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the second embodiment. It is a figure which shows the structure of the semiconductor integrated circuit design support system by Embodiment 3 of this invention, and the circuit structure of a design support object. 10 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the third embodiment. It is a figure which shows the structure of the semiconductor integrated circuit design support system by Embodiment 4 of this invention, and the circuit structure of a design support object. 10 is a flowchart showing the operation of the semiconductor integrated circuit design support system according to the fourth embodiment.

Explanation of symbols

  1 Indeterminate value generation FF detection means, 2 reset period stage count means, 3 resetless FF detection means, 4, 4A reset allowable period detection means, 5 FF stage number count means, 6 longest FF stage number storage means, 7 FF stage number corresponding number storage Means, 8 indefinite value generation FF replacement means, 9 FF replacement means without reset, 100 target circuit, 101,102 input port, 103 output port, C1-C10 combination circuit, FF1, FF5, FF7 FF with reset, FF2, FF3 FF4, FF6, FF8, FF9 FF without reset.

Claims (10)

There are no reset signal or set signal input terminals that are connected continuously without going through the flip-flops that are provided with reset signal or set signal input terminals by sequentially tracing the connection destinations of the components in the design target circuit. Indeterminate value generation that detects a flip-flop that does not have a reset signal or set signal input terminal that causes indefinite value propagation that occurs after the initial reset is canceled , based on the relationship between the number of flip-flop stages and the number of clock stages corresponding to the reset period. A semiconductor integrated circuit design support system including FF detection means.   The indefinite value generation FF detection means is a result of detecting the non-reset FF detection means for detecting the component in the design target circuit and the non-reset FF detection means tracing the connection destination of the component in the circuit in order. The number of clock stages corresponding to the reset period is the number of stages of flip-flops that do not have a reset signal or set signal input terminal connected continuously without a flip-flop provided with a reset signal or set signal input terminal. 2. A reset period counting means for detecting, as a cause of indefinite value propagation, a flip-flop having no reset signal or set signal input terminal exceeding the number of clock stages. Semiconductor integrated circuit design support system. FF detection means without reset for detecting components in the design target circuit;
FF stage number counting means for counting the number of connected stages of flip-flops that do not have an input terminal for a reset signal or set signal detected by the non-reset FF detection means;
Longest FF stage number storage means for storing the maximum number of connection stages counted by the FF stage number counting means;
The maximum value that is the number of connection stages of the flip-flops that do not have the input terminal of the reset signal or set signal that is stored in the longest FF stage number storage means is the minimum that does not cause indefinite value propagation after the initial reset release. A semiconductor integrated circuit design support system comprising a reset permissible period detecting means for detecting a reset period length. FF detection means without reset for detecting components in the design target circuit;
FF stage number counting means for counting the number of connected stages of flip-flops that do not have an input terminal for a reset signal or set signal detected by the non-reset FF detection means;
FF stage number corresponding number storage means for storing the number of connection stages counted by the FF stage number counting means and the corresponding number of places in the circuit corresponding to each value;
The FF stages corresponding number has been the number of connection stages stored in the storage means, said reset undefined value after the initial reset release of each corresponding part propagation is detected along with its corresponding location number as a minimum reset period length no acceptable period detection And a semiconductor integrated circuit design support system.   An indeterminate value generation FF replacement means for replacing a flip-flop having no reset signal or set signal input terminal detected as a cause of indefinite value propagation with a reset signal or set signal input terminal. 3. A semiconductor integrated circuit design support system according to claim 1 or 2. A flip-flop that does not have a reset signal or set signal input terminal that is connected continuously without going through a flip-flop provided with a reset signal or set signal input terminal by sequentially tracing the connection destinations of the components of the circuit to be designed An indefinite value generation FF that detects a flip-flop that does not have an input terminal for a reset signal or a set signal that causes the indefinite value propagation that occurs after the initial reset is released , based on the relationship between the number of stages of the clock and the number of clock stages corresponding to the reset period. A program for causing a computer to function as detection means.   The indefinite value generation FF detection means is a result of detecting the non-reset FF detection means for detecting the component in the design target circuit and the non-reset FF detection means tracing the connection destination of the component in the circuit in order. The number of clock stages corresponding to the reset period is the number of stages of flip-flops that do not have a reset signal or set signal input terminal connected continuously without a flip-flop provided with a reset signal or set signal input terminal. 7. A reset period counting means for detecting a flip-flop having no reset signal or set signal input terminal exceeding the number of clock stages as a cause of indefinite value propagation. Program. FF detection means for detecting a component in a design target circuit, FF stage number counting means for counting the number of connection stages of flip-flops that do not have an input terminal for a reset signal or a set signal detected by the reset FF detection means, Longest FF stage number storage means for storing the maximum number of connection stages counted by the FF stage number counting means, and a flip-flop having no input terminal for the most continuous reset signal or set signal stored in the longest FF stage number storage means program for the maximum value is connected stages, causing a computer to function as a reset allowable period detection means for indefinite propagation after the initial reset release is detected as a minimum reset period length does not occur. FF detection means for detecting a component in a design target circuit, FF stage number counting means for counting the number of connection stages of flip-flops that do not have an input terminal for a reset signal or a set signal detected by the reset FF detection means, the FF stage number counting means stages connected has counted and FF stages corresponding number storage means for storing the corresponding part number in the circuit in which the value corresponding to each, the number of connection stages stored in the FF stages corresponding number storage means, A program for causing a computer to function as a reset permissible period detecting means for detecting together with the number of corresponding positions as a minimum reset period length that does not cause propagation of an indefinite value after the initial reset release for each corresponding position.   Causes the computer to function as an indefinite value generation FF replacement means for replacing a flip-flop having no reset signal or set signal input terminal detected as a cause of indefinite value propagation with a reset signal or set signal input terminal. The program according to claim 6 or 7.

Images