JP2006285333A - Operation composition device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve design efficiency by converting incidental information added to an operation level circuit description to that added to an RTL circuit description. <P>SOLUTION: An operation composition device comprises an operation composition means for generating the RTL circuit description on the basis of the operation level circuit description, and generating information for indicating the correspondence according to the difference between the operation level circuit description and the RTL circuit description; and an incidental information converting means for converting the incidental information added to the operation level circuit description to that added to the RTL circuit description on the basis of a preset conversion rule and the correspondence information generated by the operation composition means. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a behavioral synthesis apparatus and method for generating an RTL circuit description that describes a specific function (circuit) from a behavioral level circuit description that describes the operation of a semiconductor integrated circuit device.

  Generally, in designing a semiconductor integrated circuit device such as an LSI or VLSI, an LSI design automation / support tool that automates design support or a part thereof is used. As a typical method of VLSI design using this LSI design automation / support tool, there is a top-down design method using various EDA (Electronic Design Automation) tools. The top-down design method can be roughly divided into an operation level design phase, a function design phase, a logic design phase, and a layout design phase from the upstream process.

  FIG. 14 is a flowchart showing a schematic process of the top-down design method.

  As shown in FIG. 14, in the top-down design method, an LSI to be designed is first regarded as a system, and its operation is described as a system specification creation process. This process is called an operation level design phase. The circuit description created in the behavior level design phase is called a behavior level circuit description. For example, C language, C ++ language, or Java language is used to create the behavior level circuit description. In addition, a language in which a convenient feature is added to a circuit expression may be used in C language or C ++ language, such as SystemC or SpecC.

  FIG. 15 is a diagram showing an example of the behavior level circuit description.

  FIG. 15 shows an example of behavior level circuit description described according to a grammar similar to SystemC.

  In the behavioral level circuit description shown in FIG. 15, a 4-bit signal inst and an 8-bit signal cmd are defined in the first and second rows. The third to eighth lines define that the value of the signal cmd is determined by the value of the signal inst using a switch statement.

  In the behavior level design phase, logic verification for confirming whether the operation of the circuit expressed by the behavior level circuit description is correct is also performed. An operation level logic verification device is used for logic verification in the operation level design phase. As the behavior level logic verification device, for example, a dedicated simulation device including a computer is used.

  When performing logic verification, an assertion may be added to the behavior level circuit description. An assertion is information that specifies a property to be satisfied by a design circuit, and is created using a technique described in Non-Patent Document 1, for example.

  The information to be added as an assertion includes, for example, information that specifies that the circuit is not in an undesirable state for the designer, such as “the circuit does not fall into a deadlock state”, “a response signal corresponding to the request signal that becomes active (Acknowledge signal will become active someday) Information specifying that the circuit will always reach the desired state for the designer, or "Multiple of the specified signals will not be active at the same time" Includes information specifying that the signals on the circuit hold in a desirable relationship for the designer.

  The assertion is added not only to the operation level circuit description but also to an RTL (register transfer level) circuit description created in a later process. Therefore, an assertion added to the behavior level circuit description to distinguish them is called a behavior level assertion.

  When the behavioral level circuit description and the behavioral level assertion are input, the behavioral level logic verification apparatus checks whether the design circuit expressed by the behavioral level circuit description satisfies the behavioral level assertion.

  FIG. 16 is a diagram illustrating a description example of the behavior level assertion.

  The always never statement shown in FIG. 16 is a description language for assertion, and inst is a signal defined on the behavior level circuit description as described above. In FIG. 16, it is defined that the value of the signal inst on the behavioral level circuit description does not become 4 using the always never statement.

  In the top-down design method, as shown in FIG. 14, when the behavior level design phase ends, the function design phase is executed. In the function design phase, the behavior level circuit description created in the behavior level design phase is converted into an RTL circuit description using a behavioral synthesis device. The RTL circuit description is a description that embodies the circuit to be designed to the operation for each clock. For the behavioral synthesis device, for example, the configuration described in Non-Patent Document 2 may be used.

  FIG. 17 is a flowchart showing a processing procedure of the behavioral synthesis device shown in FIG.

  As shown in FIG. 17, the behavioral synthesis device first converts the received behavior level circuit description into a format suitable for the processing of the subsequent process such as the cancellation of the function call, and the unnecessary code as the preprocessing process. Deletion, transformation processing by language level optimization, etc. are implemented.

  Next, the behavioral synthesis device performs a scheduling process for determining which process (or state) should be executed in what process (or state) based on the preprocessed circuit description.

  Subsequently, a register for holding the signal value is generated based on the scheduled circuit description, and a variable is assigned to the generated register in consideration of sharing in each process so that the cost is minimized. A register binding process is performed. Further, an arithmetic unit mapping step (also referred to as an arithmetic unit binding step) is performed in which an arithmetic unit is assigned to each operator in the circuit description so that the number of arithmetic units to be used is optimized.

  Finally, the behavioral synthesis device performs a post-processing step of converting the circuit description after the register binding step and the arithmetic unit binding step into an RTL circuit description that can be logically synthesized.

  The designer may specify a directive in the behavior level circuit description described above in order to control processing by the behavioral synthesis device. The directive is information added to the behavior level circuit description that indicates an instruction to the behavioral synthesis device. The directive is exemplified in FIG. 7A, line 6 of Patent Document 1, for example.

  The directive may be added to the RTL circuit description in the same manner as the above assertion. Therefore, a directive added to the behavior level circuit description in order to distinguish them is called a behavior level directive.

  When the behavioral level circuit description and the behavioral level directive are input, the behavioral synthesis device synthesizes the behavioral level circuit description according to the behavioral level directive. The behavior level directive is inserted, for example, in a comment or other format in the behavior level circuit description.

  FIG. 18 is a diagram showing an example of the behavior level circuit description to which the behavior level directive is added. A comment format description // directive “full case” shown in the third line of FIG. 18 is an action level directive.

  In FIG. 18, a 4-bit signal inst and an 8-bit signal cmd are defined in the first to second lines, respectively. The fourth to ninth lines define that the value of the signal cmd is determined by the value of the signal inst using a switch statement.

  Here, since the signal inst is 4 bits as described above, 16 values can be designated. However, FIG. 18 shows only operations for five values of the signal inst. This implies that the value of the signal cmd is maintained as it is when the value of the signal inst is a value (6 to 15) other than that defined in FIG.

  However, the full case statement that is the behavior level directive described in the third line in FIG. 18 specifies that all the conditions that can be assumed by the subsequent switch statement are covered. By inserting such a behavior level directive, the behavioral synthesis device that has received the behavior level circuit description shown in FIG. 18 knows that the value of the signal inst does not change from 6 to 15 when the switch statement is executed. The behavioral level circuit description can be converted into the RTL circuit description without considering the process of holding the value of.

  By specifying the behavior level directive in this way, it is not necessary to provide unnecessary logic and storage elements at the time of behavioral synthesis, so that an increase in circuit scale generated by the behavioral synthesis device can be suppressed.

  Conventionally, in the function design phase, a designer typically creates an RTL circuit description using a well-known hardware description language HDL (Hardware Description Language) or the like. When a designer creates an RTL circuit description, the behavior level directive is not normally specified.

  FIG. 19 shows an example of the RTL circuit description.

  FIG. 19 shows an example of an RTL circuit description created according to the grammar of the well-known hardware description language Verilog-HDL.

  In the RTL circuit description shown in FIG. 19, in the first to third lines, a 4-bit signal REG00, an 8-bit signal MID01, and a 4-bit signal state are defined. The 4th to 12th lines use an always statement to define that the value of the signal MID01 is determined by the value of the signal REG00 when the value of the signal state is 2.

  In the functional design phase for generating such an RTL circuit description, logic verification at a function level for confirming whether the circuit expressed by the RTL circuit description operates as intended or has sufficient performance is also performed. Done. The logic verification at the functional level of the RTL circuit description is executed regardless of whether the RTL circuit description is created by the behavioral synthesis device or the designer.

  A function level logic verification device is used for logic verification in this function design phase. As the function level logic verification device, for example, a dedicated simulation device composed of a computer or the like is used in the same manner as the operation level logic verification device.

  When performing logic verification in the functional design phase, the designer may add properties that the circuit should satisfy as an assertion. Assertions added to the RTL circuit description in the functional design phase are called RTL assertions. In addition, a directive may be added to the RTL circuit description for a logic design phase that is a subsequent process of the function design phase. A directive added to this RTL circuit description is called an RTL directive. These are described in the same manner as assertions and directives added to the behavior level circuit description in the behavior level design phase.

  FIG. 20 is a diagram showing a description example of the RTL assertion.

  The always never statement shown in FIG. 20 is a description language for assertion as described above, and REG00 is a signal defined on the RTL circuit description. In FIG. 20, it is defined that the value of the signal REG00 on the RTL circuit description does not become 4 using an always never statement.

  FIG. 21 is a diagram showing an example of the RTL circuit description to which the RTL directive is added.

  The comment format description // directive “full case” shown in the sixth line of FIG. 21 is an RTL directive.

  In the RTL circuit description shown in FIG. 21, in the first to third lines, a 4-bit signal REG00, an 8-bit signal MID01, and a 4-bit signal state are defined.

  The 4th to 13th lines use an always statement to define that the value of the signal MID01 is determined by the value of the signal REG00 when the value of the signal state is 2. Furthermore, it is defined that the full case statement that is the RTL directive described in the sixth line in FIG. 21 covers all of the conditions that can be assumed by the subsequent case statement.

  When the functional design phase ends, the logical design phase is executed. In the logic design phase, the RTL circuit description created in the function design phase is converted into a logic level circuit description (a description by a logic gate circuit or a net list) using a logic synthesis device. The net list generated by the logic synthesizer is used for layout design in the subsequent layout design phase, and chip design is performed based on the circuit pattern generated by the layout design (see FIG. 14).

  As described above, in the behavior level design phase and the function design phase, in addition to the circuit description describing the operation and function of the circuit to be designed, a plurality of additional information is added. These pieces of information are collectively referred to as incidental information. In the incidental information, information added to the behavior level circuit description (hereinafter referred to as behavior level supplementary information) such as the above behavior level assertion and behavior level directive, or added to the RTL circuit description such as RTL assertion and RTL directive. Information (hereinafter referred to as RTL supplementary information). In the behavior level design phase, information (debug description) used for debugging the behavior level circuit description is added in addition to the description that is not subject to behavioral synthesis, such as the behavior level assertion and behavior level directive.

  These incidental information is added to each circuit description generated in each design phase such as the behavior level design phase and the function design phase, but is created using the same description language as described above. Therefore, it is inefficient to create assertions and directives for each behavior level design phase and function design phase.

  However, since the behavior level circuit description and the RTL circuit description have different names of signals to be used, conditions for applying assertions and directives, etc., the behavior level assertion and behavior level directive added to the behavior level circuit description are changed to the RTL circuit. It cannot be reused and added to the description as it is.

  In addition, because of the scheduling processing performed by the behavioral synthesis device described above, a part of the execution statement of the behavior level circuit description may be parallelized or the execution order may be changed. When adding to a circuit description, it is often difficult to easily determine which process (or state) the process is applied to, or in which process the process is applied.

  In addition, the signal name is changed by the binding process, for example, multiple signals that are not used simultaneously in the behavior level circuit description are mapped to the same signal in the RTL circuit description by the register binding process and the arithmetic unit binding process executed by the behavioral synthesis device. Sometimes it is done. Therefore, in many cases, it is not easy to determine which signal the signal specified by the behavior level assertion or behavior level directive corresponds to in the RTL circuit description.

  Further, as can be seen from the behavior level assertion shown in FIG. 16 and the RTL assertion shown in FIG. 20, the same information can be specified in the behavior level assertion and the RTL assertion, but based on the behavior level circuit description. When the RTL circuit description indicating a specific function (circuit) is generated, the signal name may change. For example, when the behavior level circuit description shown in FIG. 15 is compared with the RTL circuit description shown in FIG. 19, the signals used in the behavior level circuit description are inst and cmd, whereas the signals used in the RTL circuit description are REG00, MID01, state. Therefore, the assertion used in the operation level design phase cannot be used as it is in the function design phase.

  Similarly, when the behavior level circuit description shown in FIG. 18 and the RTL circuit description shown in FIG. 21 are compared, it can be seen that the signal names have changed. If it is not known that the switch statement used in the behavior level circuit description of FIG. 18 is related to the case statement used in the RTL circuit description of FIG. 21, the behavior level directive is reused as an RTL directive. It is not possible.

  By the way, the problem caused by the difference between the behavioral level circuit description and the RTL circuit description causes not only the problem that the above-mentioned assertion and directive are separately required but also the problem that the design efficiency is lowered, and various problems. In order to solve such various problems, various methods have been studied conventionally.

  For example, when the behavioral level circuit description and the RTL circuit description are switched as appropriate in order to simulate the operation of the design circuit at high speed, the difference between the behavioral level circuit description and the RTL circuit description becomes a problem. In order to solve such a problem, Patent Document 2 includes a generation unit that generates a correspondence relationship between the behavior level circuit description and the RTL circuit description. Based on the correspondence relationship, the variable of the behavior level circuit description is stored in the RTL circuit description. A technique for mapping to a register is described.

  Further, Patent Document 3 includes a generation unit that generates a correspondence relationship between an RTL circuit description and a logic circuit description based on information from the logic synthesis device in the logic synthesis device used in the logic design phase. Describes that RTL circuit description and logic circuit description are displayed in comparison.

Patent Document 4 describes that a test sequence for an RTL circuit description is generated based on a behavior level circuit description, an RTL circuit description, and a test sequence in the behavior level circuit description. At this time, it is described that the behavioral level circuit description and the RTL circuit description are analyzed to generate the correspondence necessary for generating the test sequence for the RTL circuit description, or the correspondence obtained from the behavioral synthesis device is used. ing.
US Pat. No. 6,397,341 Japanese Patent No. 3173729 JP-A-5-2621 Japanese Patent No. 3373741 Harry Foster (HD Foster), 3 others, Assertion-based design, Kluwer Academic Publishers, 2003, pp. 1-20. Kazutoshi Wakabayashi and one other, IEEE Transactions on Computer Aided Design, November 2000, pp. 1507-1522.

  As described above, in the conventional technique, there is a problem that design efficiency is lowered because it is necessary to create assertions and directives separately due to the difference between the behavioral level circuit description and the RTL circuit description.

  In order to share assertions and directives to be added to the behavioral level circuit description and the RTL circuit description, the designer uses the behavioral level circuit description and the RTL circuit description for the RTL circuit description generated by the behavioral synthesis device. Considering the difference, a method of translating or converting to an RTL assertion or RTL directive and adding it may be considered. However, such a manual operation usually causes a design error because it is difficult to analyze the circuit description.

  Further, in the technique described in Patent Document 2, a method of exchanging values held by each component as it is based on the correspondence between the component in the behavior level circuit description and the component in the RTL circuit description. Therefore, the accompanying information such as directives and assertions added to the behavior level circuit description cannot be processed and used as the accompanying information of the RTL circuit description.

  In the technique described in Patent Document 3, only the relationship between the component in the RTL circuit description and the component in the logic circuit description is grasped and the corresponding component is displayed in comparison. Therefore, even the technology described in Patent Document 3 cannot process incidental information such as directives and assertions added to the behavior level circuit description and use it as incidental information in the RTL circuit description.

  Similarly, in the technique described in Patent Document 4, the correspondence between the external input / output values in the behavior level circuit description and the external input / output values in the RTL circuit description is grasped, and the external input / output values are exchanged as they are. Since only the method is shown, the incidental information such as directives and assertions added to the behavior level circuit description cannot be processed and used as the incidental information of the RTL circuit description.

  The present invention has been made to solve the above-described problems of the prior art, and enables conversion from incidental information added to the behavior level circuit description to incidental information added to the RTL circuit description. It is an object of the present invention to provide a behavioral synthesis apparatus and method capable of improving design efficiency.

To achieve the above object, the behavioral synthesis device of the present invention generates an RTL circuit description based on the behavioral level circuit description, and generates information indicating the correspondence between the behavioral level circuit description and the RTL circuit description. Behavioral synthesis means to
Ancillary information for converting incidental information added to the behavior level circuit description to incidental information to be added to the RTL circuit description based on the conversion rule set in advance and the information on the correspondence generated by the behavioral synthesis means Information conversion means;
It is the structure which has.

On the other hand, the behavioral synthesis method of the present invention is a behavioral synthesis method for generating an RTL circuit description describing a specific function from a behavior level circuit description describing the operation of a semiconductor integrated circuit device by a processing device,
Generating the RTL circuit description based on the behavior level circuit description;
Based on the step of generating information indicating the corresponding relationship from the difference between the behavior level circuit description and the RTL circuit description, the preset conversion rule, and the information on the correspondence generated by the behavioral synthesis means The method includes a step of converting incidental information added to the behavior level circuit description into incidental information added to the RTL circuit description.

  In the behavioral synthesis apparatus and method as described above, the incidental information in the behavioral level circuit description is converted into the incidental information in the RTL circuit description based on the incidental information conversion rule and the information on the correspondence relationship. There is no need to separately create information and incidental information of the RTL circuit description.

  According to the present invention, since the incidental information of the behavior level circuit description is converted into the incidental information of the RTL circuit description based on the incidental information conversion rule and the information of the correspondence relationship, the incidental information of the behavior level circuit description and the RTL circuit description It is no longer necessary to create each incidental information separately. Therefore, the design efficiency of the semiconductor integrated circuit device is improved. In addition, since there is no need to manually create incidental information, design errors caused by it can be prevented.

  Next, the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the first embodiment of the behavioral synthesis apparatus of the present invention.

  As shown in FIG. 1, the behavioral synthesis device according to the first embodiment includes a processing device 100 that generates an RTL circuit description and RTL supplementary information from a behavioral level circuit description and behavioral level accompanying information, and various types of processing necessary for processing. And a storage device 200 in which information is stored.

  The processing apparatus 100 according to the present embodiment is configured to include a behavioral synthesis unit 101 and an accompanying information conversion unit 102. The storage device 200 includes a behavior level circuit description storage unit 201, a behavior level incidental information storage unit 202, a correspondence relationship storage unit 203, an RTL circuit description storage unit 204, an RTL incidental information storage unit 205, and an incidental information conversion rule storage unit 209. It is the structure which has.

  The behavior level circuit description storage unit 201 stores behavior level circuit descriptions in advance, and the behavior level supplementary information storage unit 202 stores behavior level supplementary information in advance. The behavior level circuit description and behavior level incidental information are prepared by a designer, for example.

  The correspondence relationship storage unit 203 of the storage device 200 stores information indicating the correspondence relationship between the behavior level circuit description generated by the behavioral synthesis unit 101 and the RTL circuit description (hereinafter simply referred to as “correspondence”). Examples of the correspondence between the behavior level circuit description and the RTL circuit description include “signal correspondence”, “operation correspondence”, “description correspondence”, and the like.

  The behavioral synthesis means 101 reads the behavioral level circuit description stored in the behavioral level circuit description storage unit 201, generates an RTL circuit description using a technique similar to the conventional technology, and generates the generated RTL circuit description as an RTL circuit description storage unit. Stored in 204. Further, the correspondence relationship is generated from the difference between the behavior level circuit description and the RTL circuit description, and the generated correspondence relationship is stored in the correspondence relationship storage unit 203.

  The incidental information conversion means 102 includes incidental information conversion rules stored in the incidental information conversion rule storage unit 209, action level incidental information stored in the action level incidental information storage unit 202, and correspondence relationships stored in the correspondence relationship storage unit 203. Are generated from the behavior level incidental information into RTL incidental information based on the information, and stored in the RTL incidental information storage unit 205.

  The incidental information conversion rule stored in the incidental information conversion rule storage unit 209 differs depending on the type of incidental information. For example, a grammar conversion rule used for describing incidental information and a signal of an action level circuit description are replaced with a signal of an RTL circuit description. Rules, and rules regarding the position of incidental information added to the RTL circuit description.

  Note that the behavioral synthesis device according to the present embodiment may be configured by an LSI, a logic circuit, or the like that realizes the functions of the components illustrated in FIG. 1, and is configured by an information processing device (computer) as illustrated in FIG. It may be realized. The information processing apparatus illustrated in FIG. 2 includes a processing device 100 including a CPU, a storage device 200, and a recording medium 500. The processing device 100 reads a behavioral synthesis program stored in the recording medium 500, and In accordance with the behavioral synthesis program, the CPU executes the processes of the behavioral synthesis unit 101 and the accompanying information conversion unit 102 of the present embodiment described below.

  Further, the memory area of the storage device 200 includes the behavior level circuit description storage unit 201, the behavior level incidental information storage unit 202, the correspondence relationship storage unit 203, the RTL circuit description storage unit 204, the RTL incidental information storage unit 205, and the incidental information conversion. It is divided into the rule storage unit 209 and used.

  Next, the operation of the behavioral synthesis apparatus according to the present embodiment will be described with reference to FIG.

  FIG. 3 is a flowchart showing the operation of the first embodiment of the behavioral synthesis apparatus of the present invention.

  As described above, it is assumed that the behavior level circuit description storage unit 201 stores behavior level circuit descriptions in advance, and the behavior level incidental information storage unit 202 stores behavior level incidental information in advance. Also, it is assumed that the incidental information conversion rule storage unit 209 stores incidental information conversion rules in advance.

  The behavioral level circuit description is created using a language in which convenient features for circuit expression are added to C language or C ++ language such as C language, C ++ language or Java language, or SystemC, SpecC, etc. The

  An example of the behavior level circuit description is as shown in FIG. In the behavior level circuit description shown in FIG. 15, a 4-bit signal inst and an 8-bit signal cmd are defined in the first and second rows. The third to eighth lines define that the value of the signal cmd is determined by the value of the signal inst using a switch statement.

  In the following description, behavior level assertion will be described as an example of behavior level incidental information. As described above, the behavior level assertion is information that specifies the property that the operation of the circuit should satisfy, and is created using the technique described in Non-Patent Document 1, for example.

  A description example of the behavior level assertion is as shown in FIG. As described above, in FIG. 16, it is defined that the value of the signal inst on the behavior level circuit description does not become 4 using the always never statement.

  As shown in FIG. 3, the behavioral synthesis device of this embodiment is first stored in the behavioral level circuit description and behavioral level information storage unit 202 stored in the behavioral level circuit description storage unit 201 using the behavioral synthesis means 101. The behavior level supplementary information is read out, and the RTL circuit description is generated based on the behavior level circuit description and the behavior level supplementary information. Further, a correspondence relationship between the behavior level circuit description and the generated RTL circuit description is generated (step A1). The generated RTL circuit description is stored in the RTL circuit description storage unit 204, and the correspondence relationship is stored in the correspondence relationship storage unit 203. The process in step A1 may be performed using a known technique described in Non-Patent Document 2, for example.

  An example of the RTL circuit description generated by the behavioral synthesis device is as shown in FIG. As described above, in the RTL circuit description shown in FIG. 19, the 4-bit signal REG00, the 8-bit signal MID01, and the 4-bit signal state are defined in the first to third lines, respectively. Further, the 4th to 12th lines use an always statement to define that the value of the signal MID01 is determined by the value of the signal REG00 when the value of the signal state is 2. That is, when the value of the signal REG00 is 4'h1, 4'h2, 4'h3, 4'h4, 4'h5, the value of the signal MID01 is 8'h1, 8'h2, 8'h4, 8'h8 , 8'h10, and when the value of the signal REG00 is other than the above, it is indicated that the value of the signal MID01 is not particularly defined.

  FIG. 4 is a diagram illustrating a description example of the correspondence generated by the behavioral synthesis device according to the first embodiment.

  The description shown in FIG. 4 defines the above “signal correspondence”, and the signals included in the behavior level circuit description, the signals included in the RTL circuit description corresponding to the signals, and these signals correspond to each other. And the conditions to do. Specifically, when the condition state == 4′h2 holds, it is defined that the signal inst and the signal cmd in the behavior level circuit description correspond to the signal REG00 and the signal MID01 in the RTL circuit description, respectively.

  When the behavioral synthesis device generates the RTL circuit description and the correspondence relationship using the behavioral synthesis unit 101, the incidental information conversion rule and the correspondence relationship storage unit stored in the incidental information conversion rule storage unit 209 using the incidental information conversion unit 102. Correspondence relation stored in 203 and action level incidental information stored in the action level incidental information storage unit 202 are read out respectively, and the action level incidental information is converted into RTL incidental information based on the incidental information conversion rule and the correspondence relation (step A2). ). The converted RTL supplementary information is stored in the RTL supplementary information storage unit 205.

  For example, when the behavior level circuit description shown in FIG. 15 is converted into the RTL circuit description shown in FIG. 19, the rule for replacing the signal of the behavior level circuit description with the signal of the RTL circuit description is an incidental information conversion rule. Defined. In this case, the incidental information conversion unit 102 converts the signals inst and cmd defined in the operation level assertion according to the incidental information conversion rule based on the correspondence information shown in FIG. 4 into the signals REG00 and MID01 of the RTL assertion. To generate an RTL assertion.

  According to the behavioral synthesis device of the present embodiment, the action level incidental information is RTL incidental information based on the incidental information conversion rule stored in the incidental information conversion rule storage unit 209 and the correspondence relationship stored in the correspondence relationship storage unit 203. Therefore, it is not necessary to separately create the operation level incidental information and the RTL incidental information. Therefore, the design efficiency of the semiconductor integrated circuit device is improved. In addition, since there is no need to manually create incidental information, design errors caused by it can be prevented.

(Second Embodiment)
Next, a second embodiment of the behavioral synthesis device of the present invention will be described with reference to the drawings.

  FIG. 5 is a block diagram showing the configuration of the second embodiment of the behavioral synthesis device of the present invention.

  As shown in FIG. 5, the behavioral synthesis device according to the second embodiment includes a processing device 300 that generates an RTL circuit description and RTL supplementary information from a behavior level circuit description to which supplementary information is added, and a processing necessary for the processing. And a storage device 400 in which various types of information are stored.

  The processing apparatus 300 of this embodiment is configured to include a behavioral synthesis unit 101, an accompanying information conversion unit 102, and an accompanying information extraction unit 103. Further, the storage device 400 includes a behavior level circuit description storage unit 206 with supplementary information, a correspondence relationship storage unit 203, an RTL circuit description storage unit 204, an RTL supplementary information storage unit 205, an supplementary information intermediate description storage unit 207, and an RTL with supplementary information. This is a configuration having a circuit description storage unit 208 and an accompanying information conversion rule storage unit 209.

  The behavior level circuit description storage unit 206 with the accompanying information stores the behavior level circuit description to which the behavior level supplementary information is added.

  The correspondence relationship storage unit 203 stores information indicating the correspondence relationship between the behavioral level circuit description and the RTL circuit description generated by the behavioral synthesis unit 101 as in the first embodiment. Examples of the correspondence between the behavior level circuit description and the RTL circuit description include “signal correspondence”, “calculation correspondence”, “description correspondence”, and the like.

  The supplementary information extraction unit 103 reads the behavioral level circuit description to which the behavioral level supplementary information stored in the behavioral level circuit description storage unit 206 with supplementary information is added, extracts the behavioral level supplementary information, and acquires the supplementary information intermediate description. Then, the supplementary information intermediate description is stored in the supplementary information intermediate description storage unit 207. The supplementary information intermediate description is composed of, for example, information for determining the supplementary information such as line information in the behavior level circuit description to which supplementary information is added, behavior level circuit description information, supplementary information, and the like.

  The behavioral synthesis means 101 reads the behavioral level circuit description to which the behavioral level supplementary information stored in the behavioral level circuit description storage unit 206 with the supplementary information is added, generates an RTL circuit description using a technique similar to the conventional one, The generated RTL circuit description is stored in the RTL circuit description storage unit 204. Further, the correspondence relationship is generated from the difference between the behavior level circuit description and the RTL circuit description, and the generated correspondence relationship is stored in the correspondence relationship storage unit 203.

  The incidental information conversion means 102 includes an incidental information conversion rule stored in the incidental information conversion rule storage unit 209, an incidental information intermediate description stored in the incidental information intermediate description storage unit 207, and a correspondence relationship stored in the correspondence relationship storage unit 203. , The behavior level incidental information is converted into RTL incidental information based on the information, and the RTL incidental information is added to the RTL circuit description read from the RTL circuit description storage unit 204 to store the RTL circuit description with incidental information. Stored in the unit 208.

  The incidental information conversion rule stored in the incidental information conversion rule storage unit 209 differs depending on the type of incidental information. For example, a grammar conversion rule used for describing incidental information and a signal of an action level circuit description are replaced with a signal of an RTL circuit description. Rules, and rules regarding the position of incidental information added to the RTL circuit description.

  Note that the behavioral synthesis device according to the present embodiment may be configured by an LSI, a logic circuit, or the like that realizes the function of each component illustrated in FIG. 5, or is realized by an information processing device as illustrated in FIG. Also good. The information processing apparatus illustrated in FIG. 6 includes a processing device 300 including a CPU, a storage device 400, and a recording medium 500. The processing device 300 reads a behavioral synthesis program stored in the recording medium 500, and According to the behavioral synthesis program, the CPU executes the processes of the behavioral synthesis unit 101, the accompanying information converting unit 102, and the accompanying information extracting unit 103 of the present embodiment described below.

  The memory area of the storage device 400 includes the behavior level circuit description storage unit 206 with additional information, the correspondence relationship storage unit 203, the RTL circuit description storage unit 204, the RTL auxiliary information storage unit 205, and the additional information intermediate description storage unit. 207, an RTL circuit description storage unit 208 with incidental information and an incidental information conversion rule storage unit 209 are used separately.

  Next, the operation of the behavioral synthesis device of the present embodiment will be described with reference to FIG.

  FIG. 7 is a flowchart showing the operation of the second embodiment of the behavioral synthesis apparatus of the present invention.

  As described above, the behavioral level circuit description storage unit 206 with supplementary information stores in advance the behavioral level circuit description to which the behavioral level supplementary information is added, and the supplementary information conversion rule storage unit 209 stores the supplementary information conversion rule in advance. It is assumed that

  The behavioral level circuit description is created using a language in which convenient features for circuit expression are added to C language or C ++ language such as C language, C ++ language or Java language, or SystemC, SpecC, etc. The

  First, the operation of this embodiment will be described by taking as an example the case where an operation level directive is added as operation level supplementary information.

  An example of the behavior level circuit description to which the behavior level directive is added is as shown in FIG. As described above, in FIG. 18, it is defined that the value of the signal cmd is determined by the value of the signal inst using a switch statement. In FIG. 18, it is defined that all the conditions that can be assumed by the subsequent switch statement are covered by using a full case statement that is a description of the behavior level directive.

  By inserting such a behavior level directive, the behavioral synthesis device that has received the behavior level circuit description shown in FIG. 18 knows that the value of the signal inst does not change from 6 to 15 when the switch statement is executed. The behavioral level circuit description can be converted into the RTL circuit description without considering the process of holding the value of.

  As shown in FIG. 7, the behavioral synthesis device of this embodiment first uses the supplementary information extraction unit 103 to add a behavior level to which behavior level supplementary information stored in the behavior level circuit description storage unit 206 with additional information is added. The circuit description is read out, the behavior level incidental information is extracted, and the incidental information intermediate description is acquired (step B1). The acquired supplementary information intermediate description is stored in the supplementary information intermediate description storage unit 207.

  FIG. 8 is a diagram showing an example of the accompanying information intermediate description for specifying the action level directive.

  In FIG. 8, the behavior level directive // directive “full case” is inserted into the behavior level circuit description, and it is defined that the processing target is the switch statement on the fourth line.

  Next, the behavioral synthesis device uses the behavioral synthesis unit 101 to read the behavioral level circuit description to which the behavioral level supplementary information stored in the behavioral level circuit description storage unit 206 with supplementary information is added, and An RTL circuit description is generated based on the behavior level supplementary information. Further, a correspondence relationship between the behavior level circuit description and the generated RTL circuit description is generated (step B2). The generated RTL circuit description is stored in the RTL circuit description storage unit 204, and the correspondence relationship is stored in the correspondence relationship storage unit 203. The processing in step B2 may be performed using a known technique described in Non-Patent Document 2, for example.

  An example of the RTL circuit description generated by the behavioral synthesis device is as shown in FIG.

  As described above, in the RTL circuit description shown in FIG. 19, the 4-bit signal REG00, the 8-bit signal MID01, and the 4-bit signal state are defined in the first to third lines, respectively. Further, the 4th to 12th lines use an always statement to define that the value of the signal MID01 is determined by the value of the signal REG00 when the value of the signal state is 2. That is, when the value of the signal REG00 is 4'h1, 4'h2, 4'h3, 4'h4, 4'h5, the value of the signal MID01 is 8'h1, 8'h2, 8'h4, 8'h8 , 8'h10, and when the value of the signal REG00 is other than the above, it is indicated that the value of the signal MID01 is not particularly defined.

  FIG. 9 is a diagram illustrating a description example of the correspondence relationship generated by the behavioral synthesis device according to the second embodiment.

  The description shown in FIG. 9 defines the above “description correspondence” in addition to the correspondence between the behavior level circuit description signal and the RTL circuit description signal shown in FIG. It is defined that the switch () statement described in the fourth line corresponds to the case () statement described in the sixth line of the RTL circuit description.

  When the behavioral synthesis device generates the RTL circuit description and the correspondence relationship using the behavioral synthesis unit 101, the incidental information conversion rule and the correspondence relationship storage unit stored in the incidental information conversion rule storage unit 209 using the incidental information conversion unit 102. The correspondence relation stored in 203 and the supplementary information intermediate description stored in the supplementary information intermediate description storage unit 207 are read out respectively, and the action level supplementary information is converted into RTL supplementary information based on the supplementary information conversion rule and the correspondence relation (step B3). ). The converted RTL supplementary information is added to the RTL circuit description read from the RTL circuit description storage unit 204 and stored in the RTL circuit description storage unit 208 with supplementary information.

  An example of the RTL circuit description to which the RTL supplementary information is added is as shown in FIG.

  In FIG. 21, a 4-bit signal REG00, an 8-bit signal MID01, and a 4-bit signal state are defined in the first to third rows, respectively. In the fourth to thirteenth lines, an always statement is used to define that when the value of the signal state is 2, the value of the signal MID01 is determined by the value of the signal REG00. Furthermore, in FIG. 21, it is defined that the full case statement on the sixth line, which is the description of the behavior level directive, is used to cover all the conditions that can be assumed by the subsequent case statement.

  For example, when the behavior level circuit description shown in FIG. 18 is converted into the RTL circuit description shown in FIG. 21, the incidental information conversion rule is added to the behavior level circuit description along with the conversion from the behavior level circuit description to the RTL circuit description. A rule for converting the added directive and adding it to the RTL circuit description, and a rule for converting it to the grammar of the RTL circuit description are defined. In this case, the incidental information conversion unit 102 converts the signals inst and cmd defined in the operation level directive according to the incidental information conversion rule based on the correspondence information shown in FIG. 9 into the signals REG00 and MID01 of the RTL directive. Replace with. Also, an RTL directive is generated by inserting a switch () statement on the fourth line of the behavior level circuit description as a case () statement on the sixth line of the RTL circuit description. At this time, the description grammar is converted from the operation directive to the RTL directive.

  Next, the operation of the present embodiment will be described by taking as an example a case where a debug description for debugging a behavior level circuit description is added as behavior level supplementary information. The behavioral synthesis device uses the configuration shown in FIG. 5 or FIG.

  FIG. 10 is a diagram showing an example of the behavior level circuit description to which the debug description is added.

  Printf () shown in the third line of FIG. 10 is the debug description. This debug description is used at the time of logic verification to confirm whether or not the circuit designed in the behavior level design phase is correct.

  In FIG. 10, a 4-bit signal inst and an 8-bit signal cmd are defined in the first to second lines, respectively. The fourth to ninth lines define that the value of the signal cmd is determined by the value of the signal inst using a switch statement. Further, in order to monitor the circuit operation, it is defined by the printf () statement on the third line that the value of the signal inst immediately before the execution of the subsequent switch statement is output to the console screen.

  As shown in FIG. 3, the behavioral synthesis device uses the supplementary information extraction unit 103 to read the behavioral level circuit description to which the behavioral level supplementary information stored in the behavioral level circuit description storage unit 206 with additional information is added. Then, the behavior level supplementary information is extracted to obtain the supplementary information intermediate description (step B1). The acquired supplementary information intermediate description is stored in the supplementary information intermediate description storage unit 207.

  FIG. 11 is a diagram showing an example of the accompanying information intermediate description for designating the debug description.

  In FIG. 11, it is defined that printf () which is a debug description is inserted in the third line of the behavior level circuit description, and the processing target is the signal inst in the behavior level circuit description.

  Next, the behavioral synthesis device uses the behavioral synthesis unit 101 to read the behavioral level circuit description to which the behavioral level supplementary information stored in the behavioral level circuit description storage unit 206 with the supplementary information is added, and the behavioral level circuit description is read out. Based on this, an RTL circuit description is generated. Further, a correspondence relationship between the behavior level circuit description and the generated RTL circuit description is generated (step B2). The generated RTL circuit description is stored in the RTL circuit description storage unit 204, and the correspondence relationship is stored in the correspondence relationship storage unit 203.

  An example of the RTL circuit description generated by the behavioral synthesis device is as shown in FIG.

  FIG. 12 is a diagram illustrating another example of the correspondence relationship generated by the behavioral synthesis device according to the second embodiment.

  The description shown in FIG. 12 defines the above-mentioned “correspondence between operations”. The operations included in the behavior level circuit description, the operations included in the RTL circuit description corresponding to the operation, and these operations correspond to each other. And the conditions to do. Specifically, when the condition state == 4′h2 holds in the RTL circuit description, it is defined that the processing for the signal inst in the behavior level circuit description is replaced with the signal REG00 in the RTL circuit description.

  When the behavioral synthesis device generates the RTL circuit description and the correspondence relationship using the behavioral synthesis unit 101, the incidental information conversion rule and the correspondence relationship storage unit stored in the incidental information conversion rule storage unit 209 using the incidental information conversion unit 102. The correspondence relation stored in 203 and the supplementary information intermediate description stored in the supplementary information intermediate description storage unit 207 are read out respectively, and the action level supplementary information is converted into RTL supplementary information based on the supplementary information conversion rule and the correspondence relation (step B3). ). The converted RTL supplementary information is added to the RTL circuit description read from the RTL circuit description storage unit 204 and stored in the RTL circuit description storage unit 208 with supplementary information.

  FIG. 13 is a diagram illustrating an example of an RTL circuit description to which a debug description is added.

  In FIG. 13, a 4-bit signal REG00, an 8-bit signal MID01, and a 4-bit signal state are defined in the first to third rows, respectively. Further, the 4th to 11th lines use an always statement to define that the value of the signal MID01 is determined by the value of the signal REG00 when the value of the signal state is 2. Further, in FIG. 13, in order to monitor the signal REG00 in the RTL circuit description corresponding to the signal inst in the behavior level circuit description, a debug description is inserted from the 12th line to the 14th line.

  Here, when the condition state == 4'h2, the signal inst in the behavior level circuit description corresponds to the signal REG00 in the RTL circuit description, and when the value of the signal state is 4'h2, the value of the signal REG00 Is output to the screen.

  For example, when the behavior level circuit description shown in FIG. 10 is converted into the RTL circuit description shown in FIG. 13, the value of the signal in the RTL circuit description corresponding to the signal in the behavior level circuit description is included as an incidental information conversion rule. And a rule for outputting in accordance with the grammar of the RTL circuit description at that time.

  In this case, the incidental information conversion means 102 performs the behavioral level circuit description when the condition state == 4′h2 holds in the RTL circuit description according to the incidental information conversion rule based on the correspondence information shown in FIG. The inside signal inst is replaced with the signal REG00 of the RTL circuit description, and output to the screen according to the syntax of the RTL circuit description.

  According to the behavioral synthesis device of this embodiment, the incidental information extraction means 103 extracts the incidental information added to the behavior level circuit description, and stores the incidental information conversion rule and the correspondence relationship stored in the incidental information conversion rule storage unit 209. Based on the correspondence stored in the unit 203, the incidental information conversion means 102 converts the behavior level incidental information into RTL incidental information, so that even if the incidental information has already been added to the behavioral level circuit description, the first As in the case of the embodiment, it is not necessary to separately create the operation level incidental information and the RTL incidental information. Therefore, the design efficiency of the semiconductor integrated circuit device is improved. In addition, since there is no need to manually create incidental information, design errors caused by it can be prevented.

It is a block diagram which shows the structure of 1st Embodiment of the behavioral synthesis apparatus of this invention. It is a block diagram which shows the other structural example of 1st Embodiment of the behavioral synthesis apparatus of this invention. It is a flowchart which shows operation | movement of 1st Embodiment of the behavioral synthesis apparatus of this invention. It is a figure which shows the example of a description of the correspondence produced | generated with the behavioral synthesis apparatus of 1st Embodiment. It is a block diagram which shows the structure of 2nd Embodiment of the behavioral synthesis apparatus of this invention. It is a block diagram which shows the other structural example of 2nd Embodiment of the behavioral synthesis apparatus of this invention. It is a flowchart which shows operation | movement of 2nd Embodiment of the behavioral synthesis apparatus of this invention. It is a figure which shows an example of the incidental information intermediate description which designates a behavior level directive. It is a figure which shows the example of a description of the correspondence produced | generated with the behavioral synthesis apparatus of 2nd Embodiment. It is a figure which shows an example of the behavior level circuit description to which the debug description was added. It is a figure which shows an example of the incidental information intermediate description which designates a debug description. It is a figure which shows the other example of the correspondence produced | generated with the behavioral synthesis apparatus of 2nd Embodiment. It is a figure which shows an example of the RTL circuit description to which the debug description was added. It is a flowchart which shows the schematic process of a top-down design method. It is a figure which shows an example of a behavior level circuit description. It is a figure which shows the example of a description of an action level assertion. It is a flowchart which shows the process sequence of the behavioral synthesis apparatus shown in FIG. It is a figure which shows an example of the behavior level circuit description to which the behavior level directive was added. It is a figure which shows an example of RTL circuit description. It is a figure which shows the example of a description of RTL assertion. It is a figure which shows an example of the RTL circuit description to which the RTL directive was added.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Processing apparatus 101 Behavior synthesis means 102 Attached information conversion means 103 Attached information extraction means 200 Storage apparatus 201 Behavior level circuit description memory | storage part 202 Behavior level incidental information storage part 203 Correspondence relation memory | storage part 204 RTL circuit description memory | storage part 205 RTL ancillary information memory | storage Section 206 Behavior level circuit description storage section with additional information 207 Additional information intermediate description storage section 208 RTL circuit description storage section with additional information 209 Additional information conversion rule storage section 500 Recording medium

Claims (15)

A behavioral synthesis means for generating an RTL circuit description based on the behavioral level circuit description, and generating information indicating a correspondence relationship between the behavioral level circuit description and the RTL circuit description;
Ancillary information for converting incidental information added to the behavior level circuit description to incidental information to be added to the RTL circuit description based on the conversion rule set in advance and the information on the correspondence generated by the behavioral synthesis means Information conversion means;
A behavioral synthesis device. Ancillary information extracting means for extracting the ancillary information from the behavior level circuit description to which the ancillary information is added, and generating an ancillary information intermediate description that is information for determining the ancillary information;
A behavioral synthesis means for generating an RTL circuit description based on the behavioral level circuit description, and generating information indicating a correspondence between the behavioral level circuit description and the RTL circuit description;
Ancillary information for converting incidental information added to the behavior level circuit description to incidental information to be added to the RTL circuit description based on the conversion rule set in advance and the information on the correspondence generated by the behavioral synthesis means Information conversion means;
A behavioral synthesis device. The correspondence information is
Signals included in the behavior level circuit description;
A signal included in the RTL circuit description corresponding to the signal of the behavior level circuit description;
The conditions for these signals to respond,
The behavioral synthesis device according to claim 1, comprising: The correspondence information is
Operations included in the behavior level circuit description;
Operations included in the RTL circuit description corresponding to the operations of the behavior level circuit description;
The conditions for these operations to correspond,
The behavioral synthesis device according to claim 1, comprising: The correspondence information is
A description sentence included in the behavior level circuit description;
A description sentence included in the RTL circuit description corresponding to the description sentence of the behavior level circuit description;
The behavioral synthesis device according to claim 1, comprising: A behavioral synthesis method for generating an RTL circuit description describing a specific function from a behavior level circuit description describing an operation of a semiconductor integrated circuit device by a processing device,
Generating the RTL circuit description based on the behavior level circuit description;
Based on the step of generating information indicating the corresponding relationship from the difference between the behavior level circuit description and the RTL circuit description, the preset conversion rule, and the information on the correspondence generated by the behavioral synthesis means A behavioral synthesis method comprising the step of converting incidental information added to the behavior level circuit description into incidental information added to the RTL circuit description. A behavioral synthesis method for generating an RTL circuit description describing a specific function from a behavior level circuit description describing an operation of a semiconductor integrated circuit device by a processing device,
Extracting the auxiliary information from the behavior level circuit description to which the auxiliary information is added, and generating an auxiliary information intermediate description that is information for determining the auxiliary information;
Generating an RTL circuit description based on the behavior level circuit description;
Based on the step of generating information indicating the corresponding relationship from the difference between the behavior level circuit description and the RTL circuit description, the preset conversion rule, and the information on the correspondence generated by the behavioral synthesis means A behavioral synthesis method comprising the step of converting incidental information added to the behavior level circuit description into incidental information added to the RTL circuit description. The correspondence information is
Signals included in the behavior level circuit description;
A signal included in the RTL circuit description corresponding to the signal of the behavior level circuit description;
The conditions for these signals to respond,
The behavioral synthesis method according to claim 6 or 7, comprising: The correspondence information is
Operations included in the behavior level circuit description;
Operations included in the RTL circuit description corresponding to the operations of the behavior level circuit description;
The conditions for these operations to correspond,
The behavioral synthesis method according to claim 6 or 7, comprising: The correspondence information is
A description sentence included in the behavior level circuit description;
A description sentence included in the RTL circuit description corresponding to the description sentence of the behavior level circuit description;
The behavioral synthesis method according to claim 6 or 7, comprising: A program for causing a computer to generate an RTL circuit description describing a specific function from an operation level circuit description describing the operation of a semiconductor integrated circuit device,
Generating the RTL circuit description based on the behavior level circuit description;
Based on the step of generating information indicating the corresponding relationship from the difference between the behavior level circuit description and the RTL circuit description, the preset conversion rule, and the information on the correspondence generated by the behavioral synthesis means A program for causing a computer to execute a step of converting incidental information added to the behavior level circuit description into incidental information added to the RTL circuit description. A program for causing a computer to generate an RTL circuit description describing a specific function from an operation level circuit description describing the operation of a semiconductor integrated circuit device,
Extracting the auxiliary information from the behavior level circuit description to which the auxiliary information is added, and generating an auxiliary information intermediate description that is information for determining the auxiliary information;
Generating an RTL circuit description based on the behavior level circuit description;
Based on the step of generating information indicating the corresponding relationship from the difference between the behavior level circuit description and the RTL circuit description, the preset conversion rule, and the information on the correspondence generated by the behavioral synthesis means A program for causing a computer to execute a step of converting incidental information added to the behavior level circuit description into incidental information added to the RTL circuit description. The correspondence information is
Signals included in the behavior level circuit description;
A signal included in the RTL circuit description corresponding to the signal of the behavior level circuit description;
The conditions for these signals to respond,
The program according to claim 11 or 12, comprising: The correspondence information is
Operations included in the behavior level circuit description;
Operations included in the RTL circuit description corresponding to the operations of the behavior level circuit description;
The conditions for these operations to correspond,
The program according to claim 11 or 12, comprising: The correspondence information is
A description sentence included in the behavior level circuit description;
A description sentence included in the RTL circuit description corresponding to the description sentence of the behavior level circuit description;
The program according to claim 11 or 12, comprising:

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