JP2006011840A - Integrated system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an integrated system for facilitating countermeasures to large change which cannot be coped with only by the change of software. <P>SOLUTION: A processor 101 of an integrated device 100 executes software processing based on a software code generated by a generating means 1. A variable logic element 103 of the integrated device 100 executes hardware processing based on a hardware code generated by the generating means 1. Software processing is analyzed by the optimization deciding means 10, and information showing the execution rate of software processing and hardware processing is applied to a generation means 1 based on the analysis result. The generation means 1 generates the software code and the hardware code based on it. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an embedded system that changes its operation by changing the internal structure of both software and hardware according to an external environment.

  Conventionally, in an embedded system, in order to change its operation, it has been realized by upgrading only a program, that is, software (see, for example, Patent Document 1).

JP 2002-333990 A

  Since the operation change in the conventional embedded system is performed only by the software change, there is a problem that a large change that cannot be handled only by the software change cannot be made.

  The present invention has been made to solve the above-described problems, and an object thereof is to realize an embedded system that can cope with a large change that cannot be dealt with only by a change in software.

  The embedded system according to the present invention includes a generating means for generating software code and hardware code from a system description in which software and hardware constituting the embedded apparatus are described without distinction, and is provided in the embedded apparatus and generated by the generating means. Software execution means for executing processing based on software code, hardware execution means provided in the embedded device for executing processing by hardware based on the hardware code generated by the generation means, and execution status of the software execution means And an optimization determination unit that analyzes and determines the execution ratio of the hardware execution unit based on the analysis result, and the generation unit generates software code and hardware code based on the determination result of the optimization determination unit It is what you do.

  The embedded system of the present invention analyzes the software execution status of an embedded device that executes processing by both software and hardware, and controls the execution ratio of software processing and hardware processing based on the analysis result. Thus, there is an effect that the internal structure of the embedded device can be changed, and the embedded device can be changed to an embedded device with higher execution speed and lower power consumption.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an embedded system according to Embodiment 1 of the present invention.
The illustrated embedded system is an environment adaptive embedded system in which the hardware and software internal structures of the target embedded device are changed.

  In the figure, the embedded system includes a generating means 1, a compiling means 2, a linking means 3, a memory writing means 4, a high-level synthesis means 5, a logic synthesis means 6, a placement / wiring means 7, a configuration memory writing means 8, and an execution. It consists of status recording means 9 and optimization determination means 10. The embedded device 100 includes a processor 101, a memory 102, a variable logic element 103, a variable logic element configuration memory 104, and a bus 105.

  The generation unit 1 generates a software code, a hardware code, and a software / hardware interface based on a determination result of the optimization determination unit 10 from a system description 11 in which the entire system is described without distinguishing between software and hardware. It has a function to do. In the figure, software code (S / W code) 12 and hardware code (H / W code) 13 indicate the software code and hardware code generated by the generation means 1.

  As a system description 11, there is a system description language such as SpecC as a language that can describe the entire system without distinguishing between software and hardware. Further, from the description using this, the generating means 1 generates C or C ++ language as software code 12 that is a software product, and VerilogHDL or VHDL as hardware code 13 that is a hardware product.

  The compiling unit 2 is a functional unit that compiles the software code 12, and the linking unit 3 is a functional unit that generates information on the correspondence between the function and its locate address. The object code 14 is an object code generated by the compiling unit 2. The memory writing unit 4 is a functional unit for writing the object code 14 into the memory 102 in the embedded device 100.

  The high-level synthesis means 5 is conscious of concepts specific to hardware such as synchronization by registers and clocks, from the operation description that directly describes the algorithm of the target processing, such as the hardware code 13 generated by the generation means 1. This is a functional unit for performing high-level synthesis processing for automatically synthesizing the registered RTL (Register Transfer Level) description. The logic synthesis unit 6 is a functional unit that generates a logic circuit suitable for the structure of the target variable hardware from the RTL description output from the high-level synthesis unit 5. The logic synthesis means 6 has a function of converting a code such as HDL (Hardware Description Language) describing hardware into a logic circuit, for example. The placement / wiring means 7 is a functional unit that outputs configuration data 15 for mounting a logic circuit converted from a code such as HDL on an LSI.

  The configuration data 15 is a net list, for example, and corresponds to data directly representing a circuit corresponding to the object code 14 in software. The configuration memory writing unit 8 is a functional unit for writing the configuration data 15 to the variable logic element configuration memory 104 in the embedded device 100.

  The embedded device 100 is a device in which software processing and hardware processing such as radar, robot, or machine tool are emphasized. The processor 101 executes software code written on the memory 102 and performs various processes. The memory 102 is a memory composed of a RAM or the like. The variable logic element 103 is a variable logic hardware circuit such as an FPGA. The variable logic element configuration memory 104 is a memory for supplying the configuration data 15 written by the configuration memory writing means 8 to the variable logic element 103. The bus 105 is an in-device bus for connecting the processor 101, the memory 102, and the variable logic element 103 to each other.

  The processor 101 and the memory 102 correspond to software execution means in the embedded device 100, and the variable logic element 103 and the variable logic element configuration memory 104 correspond to hardware execution means.

The execution status recording means 9 is a means for recording the execution status of the processor 101, and is specifically configured as follows.
FIG. 2 is an explanatory diagram showing a connection state between the embedded device 100 and the execution status recording unit 9.
FIG. 3 is a block diagram showing the internal configuration of the execution status recording means 9.

  As shown in FIG. 2, the execution status recording means 9 is connected to the address line 16 of the processor 101 in the embedded device 100, and is configured to record the software execution status based on the address of the address line 16. .

  That is, when there is a change in the flow of a program that is normally executed in sequence, such as a jump instruction, a function call, or a subroutine call, during execution of the processor 101, it is notified by issuing an interrupt from the processor 101 to the outside. At that time, the address line of the processor 101 indicates the address after the flow of execution has changed. Therefore, the execution status of the software can be recorded by recording this address.

  As shown in FIG. 3, the execution status recording means 9 includes a processor 91, a timer 92, and an execution recording memory 93. The processor 91 is a processor of the execution status recording unit 9 provided separately from the processor 101 of the embedded device 100, and calculates the execution status of the processor 101 based on the address flowing through the address line 16. The timer 92 is a timer for supplying time information when the processor 91 records the execution status. The execution recording memory 93 is a memory for recording information on addresses and occurrence times recorded by the processor 91 (execution time correspondence table 201).

FIG. 4 is an explanatory diagram of the execution time correspondence table 201 recorded in the execution recording memory 93.
As shown in the figure, the execution time correspondence table 201 records a record of occurrence time and address.

  The optimization determination unit 10 analyzes the recording information of the execution status of the execution status recording unit 9, determines the execution rate of the hardware processing based on the analysis result, and outputs the result to the generation unit 1 It is. In other words, the optimization determination unit 10 has a function of determining the execution ratio so that the processing is executed by the hardware execution unit in the order of processing with a long processing time in the software execution unit.

Next, the operation of the first embodiment will be described.
First, it is arbitrary which part of the system description 1 that describes the entire system is executed by software and which part is executed by hardware. Instruct appropriately. The generation unit 1 generates the software code 12 and the hardware code 13 according to the instruction. Or you may instruct | indicate to the production | generation means 1 to perform by software initially. In that case, the generation means 1 generates the software code 12 so that the system description 1 is entirely executed by software.

  The code generated as described above and executed by the embedded device 100 is recorded by the execution status recording unit 9 during execution. The processor 91 of the execution status recording unit 9 receives the data on the address line 16 when an interrupt signal when the flow of execution of the software code executed by the processor 101 of the embedded device 100 to be recorded is changed is input. Read and write to the execution recording memory 93. At the same time, the time information from the timer 92 provided in the execution status recording means 9 is obtained and recorded. That is, the execution status is recorded in the execution recording memory 93 in a data structure as shown in FIG. However, the first line records the execution start address and the execution start address unique to the processor, such as when the system is turned on. When the power is turned on and the recording is not started at the same time, the recording is started from the interrupt from the processor 101 of the first embedded device 100.

  When the recording data becomes full in the execution recording memory 93 or at an arbitrary timing, the execution of the target embedded device 100 is stopped, and the optimization determination process by the optimization determination unit 10 is executed. The flow of this process is shown below.

FIG. 5 is a flowchart of the optimization determination process.
In the optimization determination process, first, the optimization determination unit 10 reads the data (execution time correspondence table 201) in the execution recording memory 93 of the execution status recording unit 9 (step ST1). Next, a correspondence table between the function generated by the linking means 3 and its locate address is read (step ST2). The correspondence table here is a correspondence table indicating the function name and the address where the function is arranged in the memory 102 of the embedded device 100. Note that the line connecting the link means 3 and the optimization determination means 10 is omitted in FIG.

  Next, invalid information is deleted from the execution time correspondence table 201 based on the read correspondence table (step ST3). The invalid information here has the following meaning. For example, when a system is first generated so as to be executed entirely by software, the execution speed is improved and the power consumption can be further reduced by generally executing the part executed by software by hardware. However, the capacity of the variable logic element 103 and the like is usually not so large that the entire system is made hardware. Therefore, which part of the embedded device 100 is to be executed by hardware must be selected within the range of hardware capacity. In general, it is more effective to implement hardware for a process that takes longer time to be executed by software. However, it is difficult to determine the part in advance, and the operation varies depending on the environment, and there are many embedded devices whose execution pattern cannot be determined until it is actually installed.

  Therefore, it is desirable to determine the part to be hardwareized by the data when it is actually installed. However, in the case of a meaningless process such as an idle loop that is executed when the part is executed for the longest time at the time of execution but nothing is executed, improve the execution speed by hardwareizing the part. Also has no meaning. Therefore, it is necessary to delete a portion that does not make sense even if it is implemented in hardware, and the process of step ST3 is for this purpose.

Next, the optimization determining means 10 creates a function-execution time correspondence table by calculating execution time from the execution time in units of processing based on the data of the execution time correspondence table 201 (step ST4).
FIG. 6 is an explanatory diagram of the execution time correspondence table 202.
The information of the link means 3 described above, the name of the function executed from the execution recording memory 93, and the time for executing it can be calculated. This is because when a function call occurs, its address is recorded in the execution recording memory 93 together with the time of occurrence, and the difference between the execution start time of one function and the next function execution start time becomes the execution time of that function. Of course, there are many cases where the same function is called a plurality of times. In this case, the same address appears in another location in the execution recording memory 93, but it is assumed that they are combined into one. Of course, the execution time is the sum of the execution times of all the same functions.

  The execution time correspondence table 202 is created on a recording memory (not shown) provided in the optimization determination means 10.

  In this way, when the execution time correspondence table 202 is created, a process with the longest execution time is selected from the table, and this information is sent to the generation unit 1 as a determination result (step ST5). The generation means 1 generates a hardware code this time from the part of the system description 11 describing the function (step ST6). Further, the optimization determining means 10 deletes the currently selected portion from the execution time correspondence table 202 (step ST7).

  Next, the optimization determination means 10 compares the hardware code generated in step ST6 with the hardware capacity of the control embedded device, and determines whether it is within the capacity range (step ST8). It is assumed that the optimization determination unit 10 holds hardware capacity information in the embedded device 100 therein. In step ST8, if it is within the capacity range, the high level synthesis means 5 to the configuration memory writing means 8 write to the variable logic element configuration memory 104 of the target embedded device 100 according to the procedure described first (step ST9). ).

  Next, the optimization determination unit 10 updates the remaining hardware capacity (step ST10), and determines whether all the functions of the execution time correspondence table 202 have been checked (step ST11). If the function still remains in step ST11, the process returns to step ST5. If all the functions are examined, the optimization determination process is terminated.

  By such processing, the execution rate is changed so that the hardware processing is performed in the order of the longest execution time of the software processing, and this is set so that the hardware processing is performed up to the capacity of the hardware. The internal structure is different from the first.

  In the first embodiment, in the determination process for converting the part executed by the software shown in FIG. 5 into hardware, the part that has been excluded from the execution time correspondence table 202 is deleted. However, an implementation method in which the number of items in the table is increased and an invalid flag is added has the same effect as the above embodiment.

  Further, in the first embodiment, the target embedded device 100 is stopped and the internal structure is rewritten. However, even if a part different from the part to be changed is rewritten during execution, the same as in the first embodiment is performed. effective.

  As described above, according to the first embodiment, the generation unit that generates the software code and the hardware code from the system description in which the software and the hardware constituting the embedded device are described without distinction, and the generation device Software execution means for executing processing based on the software code generated by the means, hardware execution means provided in the embedded device for executing processing by hardware based on the hardware code generated by the generation means, and software execution Analyzing the execution status of the means, and based on the analysis result, an optimization determination means for determining the execution ratio of the hardware execution means, and the generation means, based on the determination result of the optimization determination means, software code Hardware code is generated. Of changing the internal structure, there is an effect that more execution speed is high and power consumption can be varied in small embedded device.

  Further, according to the first embodiment, the optimization determination unit determines the execution ratio so that the hardware execution unit executes the processing in the order of the processing with the long processing time in the software execution unit. Efficiently, an embedded device with high execution speed and low power consumption can be obtained.

Embodiment 2. FIG.
FIG. 7 is a configuration diagram of the embedded system according to the second embodiment.
In the second embodiment, the generating unit 1, the compiling unit 2, the linking unit 3, the memory writing unit 4, the high-level synthesis unit 5, the logic synthesis unit 6, the arrangement / wiring unit 7, and the configuration, which are different configurations in the first embodiment. The memory writing means 8, the execution status recording means 9, and the optimization determination means 10 are provided in the embedded device 100a. That is, the generation means 1 to the optimization determination means 10 are realized by using the processor 101 in the embedded device 100a.

  Accordingly, the configuration of the system description 11, the software code 12 and the hardware code 13 generated by the generation unit 1, and the object code 14 and the configuration data 15 are the same as those in the first embodiment. Omitted.

  Since the execution status recording means 9 is also configured using the processor 101, the execution of the software code in the processor 101 is recorded by the operation of the processor 101 for realizing the execution status recording means 9. To do.

  Since the optimization processing in the embedded system of the second embodiment configured as described above is performed in the same manner as in the first embodiment, description of the operation is omitted.

  As described above, according to the second embodiment, since the generation unit and the optimization determination unit are integrated into the embedded device, the configuration can be simplified as an embedded system, and software and hardware can be installed at an arbitrary time. It is possible to execute wear optimization.

Embodiment 3 FIG.
FIG. 8 is a configuration diagram of the embedded system according to the third embodiment.
In the third embodiment, the system description 11 is generated by the SLDL code generation means 18 from the system specification 17 described in a model description language such as UML (Unified Modeling Language) having a higher abstraction level than the system description 11. It is. Other configurations of the generation unit 1 to the optimization determination unit 10 and the built-in device 100 are the same as those in the first embodiment, and accordingly, the corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  In the embedded system configured as described above, the SLDL code generation unit 18 generates a system description language having a slightly lower degree of abstraction than the UML from the system specification 17 described in UML, and outputs this as a system description 11. . Subsequent operations are the same as those in the first embodiment.

  As described above, according to the third embodiment, the system description is generated from the model description language having a higher abstraction level than the system description, so that the development efficiency of the embedded system can be further improved. it can.

  In each of the above embodiments, the execution status recording unit 9 and the optimization determining unit 10 are illustrated as different configurations, but of course, the same effect can be obtained even if both are realized as a single device.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the embedded system by Embodiment 1 of this invention. It is explanatory drawing which shows the connection state of the embedded apparatus and execution status recording means in the embedded system of Embodiment 1 of this invention. It is a block diagram which shows the internal structure of the execution condition recording means in the embedded system of Embodiment 1 of this invention. It is explanatory drawing of the execution time corresponding | compatible table in the embedded system of Embodiment 1 of this invention. It is a flowchart of the optimization determination process in the embedded system of Embodiment 1 of this invention. It is explanatory drawing of the execution time correspondence table | surface in the embedded system of Embodiment 1 of this invention. It is a block diagram which shows the embedded system by Embodiment 2 of this invention. It is a block diagram which shows the embedded system by Embodiment 3 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Generation | occurrence | production means, 9 Execution status recording means, 10 Optimization determination means, 17 System specification, 18 SLDL code generation means, 100, 100a Embedded apparatus, 101 Processor, 102 Memory, 103 Variable logic element, 104 Memory for variable logic element structure .

Claims (4)

Generating means for generating software code and hardware code from a system description in which software and hardware constituting the embedded device are described without distinction;
Software execution means that is provided in the embedded device and executes processing based on the software code generated by the generation means;
Hardware execution means that is provided in the embedded device and executes processing by hardware based on the hardware code generated by the generation means;
Analyzing the execution status of the software execution means, and based on the analysis result, comprising an optimization determination means for determining the execution ratio of the hardware execution means,
The embedded system generates the software code and the hardware code based on the determination result of the optimization determination unit.   The embedded system according to claim 1, wherein the generation unit and the optimization determination unit are integrated in the embedded device.   3. The embedded system according to claim 1, wherein the system description is generated from a model description language having a higher abstraction level than the system description.   The optimization determination unit determines the execution ratio so that the processing is executed by the hardware execution unit in the order of processing with a long processing time in the software execution unit. The embedded system according to claim 1.

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