JP4006120B2 - Logic synthesis device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic synthesis device in LSI (Large Scale Integration) design.
[0002]
[Prior art]
In the function / logic design phase of a conventional LSI, an optimum gate / level logic circuit (network) is input by inputting RTL (Register Transfer Level) description expressed in a hardware description language (for example, Verilog, VHDL, etc.) and various control data. The main task is to automatically generate a list. There are many EDA (Electronic Design Automation) tools that perform this automatic generation today, and “Design Compiler” of SYNOPSYS is one of them.
[0003]
When actually performing logic synthesis using a tool for automatically generating the netlist, that is, a logic synthesis tool, the following procedure is necessary.
(1) Create an RTL description. The RTL description is created for each module, which is a functional unit constituting an LSI, and a plurality of modules usually form a hierarchical structure for design efficiency. Therefore, there are usually a plurality of RTL descriptions for one netlist.
(2) Create a control file describing the clock constraints. One control file is required for one netlist.
(3) One synthesis script is created for each RTL description using information in the control file. If there are N RTL descriptions, N synthesis scripts are required. In an LSI circuit in which modules form a hierarchical structure, RTL descriptions and synthesis scripts used in the function / logic design phase also form a hierarchical structure.
{Circle around (4)} (N pieces of the above) synthesis scripts are given, and (the N pieces of) RTL descriptions are input to perform logic synthesis to create one netlist.
[0004]
In the procedures (1) to (4), the logic synthesis tool, which is an EDA tool, performs the automatic operation only in the procedure (4). [However, an EDA tool that partially supports the creation of an RTL description in the procedure (1) is currently commercially available (for example, SYNOPSYS “Behavior Compiler”). ]
[0005]
If the RTL description and the script for synthesis form a hierarchical structure, for example, when a change occurs in the control file, etc., only the RTL description and script related to the relevant module are modified, and the above hierarchical structure If an RTL description or script that contains an RTL description or script and is positioned above them takes in a modified RTL description or script, re-synthesizes it, and connects it to the uncorrected module to re-form the netlist Good. In this way, the hierarchical structure of the RTL description and the synthesis script also has an effect that it is possible to easily repeat the logic synthesis in the LSI function / logic design phase.
[0006]
However, as the LSI scales up and speeds up, the above hierarchical structure becomes increasingly large. At the same time, it becomes increasingly difficult to grasp the range of RTL descriptions and synthesis scripts that are affected when a change occurs in RTL descriptions and control files (upper hierarchical structure). As a result, errors are likely to occur in the re-logic synthesis RTL description and the range of the synthesis script. On the other hand, if there is any change in the RTL description or control file, if the policy of re-synthesizing the entire netlist based on all the RTL descriptions and synthesis scripts is taken, the scale-up complexity will increase. In an integrated LSI, it takes an enormous amount of time, and trial synthesis of logic synthesis in the function / logic design phase is not easy.
[0007]
[Problems to be solved by the invention]
Even if the LSI scales up and speeds up, and the hierarchical structure in the netlist becomes enormous, the re-logic synthesis time can be reduced by performing the minimum modification work in the modification in the function / logic design phase. The purpose is to prevent the occurrence of errors in the re-logic synthesis work by making the work short and performing the work to be performed at the time of modification correction without leakage.
[0008]
[Means for Solving the Problems]
In the functional logic design phase of the LSI, the EDA tool automatically generates a netlist from a control file, one or more RTL descriptions, and the same number of synthesis scripts as the RTL descriptions generated from each RTL description. A logic synthesis device for generating,
(1) means for analyzing the hierarchical structure of the RTL description from the contents of the RTL description;
(2) A means for creating a computer system command for performing logical synthesis at once based on the hierarchical structure of the RTL description,
When there is a change or addition to the RTL description or synthesis script, the RTL description or synthesis script that includes the RTL description or synthesis script in the hierarchical structure and is positioned above them is changed or added. Means for taking in an RTL description and a synthesis script, performing re-logic synthesis, creating a computer system command to re-form a netlist by connecting to an RTL description and synthesis module without change;
(3) means for automatically generating a synthesis script from the control file and the individual RTL descriptions ;
(4) means for holding the generated script for synthesis if the script for synthesis automatically generated by the means of (3) above is a script having the same name among existing scripts for synthesis ; ,
(5) If the content of the synthesis script automatically generated by the means of (3) matches the existing synthesis script with the same name, the generated synthesis script is deleted and the existing synthesis script with the same name is deleted. and the remaining to means,
(6) If the content of the synthesis script automatically generated by means of (3) above does not match the content of the existing synthesis script with the same name, the generated synthesis script is overwritten with the existing synthesis script with the same name. And means for leaving the contents of the generated synthesis script,
(7) The synthesis script held by the means of (4), the synthesis script left by the means of (5), and the composition left by the means of (6) And a means for re-creating a net list by the computer system command created by the means for creating the computer system command of (2) above by inputting the script and the RTL description. Using this, we aim to solve the above problems.
[0009]
In the system apparatus, the computer system command may be a Makefile used when using a make command in a UNIX (registered trademark) operating system.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the method of the present invention will be described below with reference to the accompanying drawings.
[0011]
FIG. 1 shows an embodiment of a hardware configuration of a system apparatus for realizing the present invention. The apparatus is, for example, a UNIX computer 2 equipped with a CAD system including a logic synthesis tool in LSI design. In FIG. 1, software related to a system for realizing the present invention is stored in a magnetic disk 4, mounted in a memory 6 in response to a request from a system user, and a control command 8 or a mouse device 10 input from the outside. The display device 14 displays predetermined information on the display device 14. Magnetic signal information such as an RTL description file, a control file, and a script file output library, which will be described later, is held in the magnetic disk 4, and a software request or a user request related to a system for realizing the present invention. In response to this, it is mounted in the memory 6 or is changed in the memory 6 and is held in the magnetic disk 4 again.
[0012]
FIG. 4 shows a flowchart of the processing of the apparatus according to the present invention. From the process of reading the created RTL description file and control file to the process of performing netlist logic synthesis by the make command is included.
[0013]
In processes 22 and 24, the apparatus reads an RTL description file and a control file in which various control data such as clock restrictions are described. The RTL description file and the control file are provided in the CAD system library. As described above, the RTL description is expressed in a hardware description language such as Verilog, and for one gate level logic circuit (netlist), there is one control file and one RTL description. The above is prepared.
[0014]
In processing 26, the hierarchical structure of the RTL description is analyzed and grasped from the contents of the read RTL description file using, for example, PLI (programmable language interface) provided in Verilog (see FIG. 6).
[0015]
In process 28, a Makefile (makefile) to be described later is automatically generated based on the hierarchical structure of the RTL description. When a modification change occurs in the RTL description or logic synthesis script, the RTL description or logic synthesis script that includes the RTL description or logic synthesis script in the hierarchical structure and is positioned above them is modified. The contents of the Makefile are generated so that the RTL description and logic synthesis script are taken in, re-logic synthesis is performed, and the netlist is re-formed by connecting to the uncorrected modules (see FIGS. 2 and 3).
[0016]
The following processing 30 to processing 42 are performed for each RTL description. First, in processing 30, one logic synthesis script corresponding to the RTL description is automatically generated as a file from one of the RTL description files and the contents of the control file.
[0017]
If the output directory holding the existing logic synthesis script file does not have the same name as the logic synthesis script file generated in the process 30 (decision 32), the logic synthesis script is supported. Since the RTL description to be performed, that is, the module is newly created, it is output to the output directory (process 34).
[0018]
If the output directory holding the existing logic synthesis script file has the same name as the logic synthesis script file generated in the process 30 (determination 32), the existing logic synthesis script having the same name is used. The file is aliased and output to the output directory (process 36).
[0019]
In decision 38, the entire contents of the existing logic synthesis script file of the same name and the aliased logic synthesis script file are compared. When a change is made in the RTL description or the control file, the logic synthesis script may be changed, and the object is to confirm it. If the contents match, the original logic synthesis script file has not changed. At this time, in preparation for logic synthesis by a subsequent make command, the original logic synthesis script file is left and the aliased logic synthesis script file is deleted (process 42).
[0020]
If the contents are different, it means that the original logic synthesis script file has changed. At this time, in preparation for logic synthesis by a subsequent make command, the aliased logic synthesis script file is changed again to its original logic synthesis script file name and overwritten (process 40).
[0021]
After all the RTL descriptions and all the scripts have been processed, the make command of the UNIX operating system is executed to process the contents of Makefile (process 44). 2, 3 and 6 show the same module hierarchical structure. FIG. 7 shows an example of a Makefile output from the module hierarchical structure via the apparatus of the present invention. In this Makefile, for example, rule (5) is the file “MOD_D. v ”time stamp (file creation date and time) and the file“ MOD_D. db ”timestamps are compared, and the file“ MOD_D. scr "time stamp and file" MOD_D. db ”timestamps are compared, and the file“ MOD_D. v "and the file" MOD_D. one of the files “MOD_D. If it is newer than "db", the command "dc_shell -f MOD_D. "scr" is executed. In FIG. v ”is an RTL description file, and an identifier“. “scr” indicates that it is a logic synthesis script file. “db” indicates that the file is an intermediate file.
[0022]
When a make command is executed using Makefile and logical synthesis is performed, the script file that is not affected by the change in the RTL description or control file does not change its contents and the time stamp is not updated. Don't be. Therefore, the total synthesis time can be shortened. Furthermore, there is no synthesis omission for modules that require resynthesis.
[0023]
In the following, an example will be described in which the control file shown in FIG. 5 and the RTL description having the hierarchical structure shown in FIG. 6 are input to one embodiment of the apparatus according to the present invention.
[0024]
The control file of FIG. 5 is described as using the above-mentioned “Design Compiler” of SYNOPSYS. Here, designation of the wire load model for each module, clock restrictions, compilation method, and the like are described.
[0025]
The hierarchical structure of the module in FIG. 6 is the result of the RTL description analysis by Verilog PLI (see process 26 in FIG. 4). When a Makefile is created from the analysis result through the apparatus of the present invention, it is as shown in FIG. 7 (“dc_shell-f” in FIG. 7 is also a command related to “Design Compiler” of SYNOPSYS, Inc.).
[0026]
When the first logic synthesis script output is performed in the logic synthesis of the LSI to be designed in this embodiment using this apparatus, the process 34 of FIG. 4 is performed for all the logic synthesis scripts. Therefore, a script file for all logic synthesis (TOP.scr, MOD_A.scr, MOD_B.scr, MOD_C.scr, MOD_D.scr, MOD_E.scr) is newly created and output to the output library.
[0027]
When these logic synthesis script files are given and the first Makefile shown in FIG. 7 is executed, logic synthesis is performed in all modules (TOP, MOD_A, MOD_B, MOD_C, MOD_D, and MOD_E).
[0028]
Next, it is assumed that the control file is modified and the second execution of the flowchart of FIG. 4 is performed. Processes 22 to 28 are performed in exactly the same way as the first time. The processing 30 is executed in the same way as the first time, but since a script file with the same name already exists in the output directory, each script file is output with a different file name from the file output the first time (see FIG. 4 decision 32 process 36). For example, the script file of the module MOD_A is MOD_A. If it was output with the file name scr. MOD_A. The file name is “scr”.
[0029]
Then, the contents are compared with the existing logic synthesis script file of the same name (see decision 38 in FIG. 4). If the contents are exactly the same, it means that no modification has been made to the module related to the script, so the newly output script file is deleted (see process 42 in FIG. 4). In the above example,. MOD_A. Scr can be an object to be erased. If the contents are different, it means that the module related to the script has been modified, and therefore re-logic synthesis of the module related to the script is necessary. Therefore, the contents of the newly output script file are overwritten on the existing logical synthesis script file of the same name to obtain an existing file name, which is connected to processing by the subsequent make command. For example, if only the script content of MOD_D is changed, the upper layer modules that are affected by the change of the module MOD_D are TOP, MOD_B, and MOD_C from FIG. 2, FIG. 3, and FIG. Then, the logic synthesis process to be executed is a process command of the rules (1), (3), (4), and (5) in FIG. When the make command using the Makefile in FIG. 7 is executed, the make command and the Makefile function are executed reliably from the bottom up. On the other hand, rules (2) and (6) are not executed.
[0030]
In the above embodiment, the case where the control file is modified has been described. However, even when the RTL description file is modified or when the RTL description file is added, the module to be resynthesized is reliably re-synthesized and re-synthesized. Re-synthesize only the modules that should be. Therefore, also in these cases, the time for re-logic synthesis can be shortened as much as possible, and work leakage in re-logic synthesis can be prevented.
[0031]
【The invention's effect】
As is clear from the above description, the following effects can be obtained by using the system apparatus of the present invention.
[0032]
The present invention provides a functional logic design of a large-scale semiconductor integrated circuit at the stage of functional logic design of a large-scale semiconductor integrated circuit in which a circuit is divided into modules for each function and a plurality of modules form a hierarchical structure. It is a device that operates when making correction changes. Modules that include the module to be changed in the hierarchical structure and that are positioned above them take in the module to be changed after being changed, are synthesized again, and are connected to the unmodified module to re-gate the gate level logic circuit. The apparatus of the present invention comprises a system for automatically generating computer system commands designed so as to be formed using the RTL description related to the module hierarchical structure. By using this apparatus of the present invention, only the minimum modification / correction work is performed, the re-synthesis time is shortened, and the work to be performed at the modification / correction is performed without omission. Generation of errors in logic synthesis work is prevented.
[0033]
In the above system apparatus, if the computer system command is a Makefile used when using the make command in the UNIX operating system, the command itself is a technique well known to those skilled in the art. The effect that it is easy to use is also obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of a hardware configuration of a system apparatus that implements the present invention.
FIG. 2 is a block diagram of an LSI and a plurality of modules configured by functionally dividing the LSI for one specific example of the LSI.
3 is a block diagram showing a hierarchical relationship structure between the LSI and a plurality of modules configured by dividing the LSI in the specific example of FIG. 2;
FIG. 4 is a flowchart of processing of an apparatus according to the present invention.
FIG. 5 is an example of a control file input by logic synthesis.
6 is a schematic diagram showing a hierarchical relationship structure between the LSI and a plurality of modules configured by dividing the LSI in the specific example of FIG. 2;
7 is an example of a Makefile generated using the apparatus according to the present invention with respect to the specific example of FIG.
[Explanation of symbols]
2 ... computer, 4 ... magnetic disk, 6 ... memory, 8 ... control command, 10 ... mouse device, 14 ... display device

Claims (2)

Logic synthesis that automatically generates a netlist using the EDA tool from the control file, one or more RTL descriptions and the same number of RTL descriptions generated from each RTL description in the LSI functional logic design phase A device,
(1) means for analyzing the hierarchical structure of the RTL description from the contents of the RTL description;
(2) A means for creating a computer system command for performing logical synthesis at once based on the hierarchical structure of the RTL description,
When there is a change or addition to the RTL description or synthesis script, the RTL description or synthesis script that includes the RTL description or synthesis script in the hierarchical structure and is positioned above them is changed or added. Means for taking in an RTL description and a synthesis script, performing re-logic synthesis, creating a computer system command to re-form a netlist by connecting to an RTL description and synthesis module without change;
(3) means for automatically generating a synthesis script from the control file and the individual RTL descriptions ;
(4) means for holding the generated script for synthesis if the script for synthesis automatically generated by the means of (3) above is a script having the same name among existing scripts for synthesis ; ,
(5) If the content of the synthesis script automatically generated by the means of (3) matches the existing synthesis script with the same name, the generated synthesis script is deleted and the existing synthesis script with the same name is deleted. and the remaining to means,
(6) If the content of the synthesis script automatically generated by means of (3) above does not match the content of the existing synthesis script with the same name, the generated synthesis script is overwritten with the existing synthesis script with the same name. And means for leaving the contents of the generated synthesis script,
(7) The synthesis script held by the means of (4), the synthesis script left by the means of (5), and the composition left by the means of (6) A logic composition comprising: a script and the RTL description as input, and means for re-creating a net list by the computer system command created by the means for creating the computer system command of (2) above apparatus.   The logic synthesis apparatus according to claim 1, wherein the computer system command is a Makefile used when a make command is used in a UNIX operating system.

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