JPH11502646A - Generation and use of synthetic shells in ASIC design - Google Patents

Abstract

(57) Summary A practical approach for ASICs consisting of millions of gates, based on the use of a synthetic shell. A synthesis shell is created by starting with a gate-level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates, resulting in a composite shell of the composited block. The synthesis shell includes an input load and fanout for the block, an output delay for the block's clock, a setup / hold constraint on the input signal for the block's clock, and an input to output delay for the passing signal of the circuit block. save. Such a synthesis shell can be used as a substitute for the original design netlist, is portable for hierarchical synthesis in a customer's design environment, or from the ASIC service provider, and is provided by such a provider. Can be used to protect the intellectual property rights of This shell is very accurate because all the information needed by the synthesizer is available in the synthesis shell in the form of a netlist. The synthesis shell described above includes a gate-level description that is a subset of the synthesized blocks. This description is reduced by removing elements of the gate level description according to a set of pre-specified criteria.

Description

DETAILED DESCRIPTION OF THE INVENTION Generation and Use of Synthetic Shells in ASIC Designs Limited Disclaimer of Copyright Some portions of the disclosure of this patent document contain material whose copyright protection is sought. The copyright holder does not object to facsimile reproduction by anyone of this patent document or patent disclosure as it appears in the United States Patent and Trademark Office files or records, but reserves all other rights. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuit development, and more particularly, to tools used in the design and development of application specific integrated circuits (ASICs). 2. Description of the Related Art Automated design tools for ASIC design enable the design of ASICs containing millions of available gates on a single chip. The development process of such a complex ASIC relies on development and verification tools implemented in a data processing system that automates the design. These tools are provided by major electronic design automation equipment or ASIC vendors, such as LSI Logic Corporation, the assignee of the present invention. For example, LSI Logic offers a product called the C-MDE (TM) design tool, which provides all the functions necessary to move a design to working silicon. Design tools in commercially available design automation systems include timing analysis tools, floor planning tools, layout tools, synthesis tools, packaging tools, and the like. The design process typically includes an ASIC specification with a description of the behavioral (or register-migration level). In a process known as synthesis, this behavioral description is processed to create an optimized gate-level netlist for the design. The netlist is very large because there are millions of gates in one design. Since synthesis is a recursive process, the entire netlist must be processed before it can be stored in a data processing system and created in its final form. As the density of ASIC designs increases, the available computing power has become more difficult to keep up with. Therefore, system execution tools for ASIC design require powerful computers with large amounts of memory. As the number of available gates grows exponentially, speed and memory bottleneck problems arise, which substantially slow down the development process for complex designs. To address this problem, Synopsys, a vendor of electronic design automation equipment, has created a hierarchical design that can be converted to a library cell that has delay information for the cell in the form of timing arcs. The "model" used is proposed. This model is used in place of the original design, which can be removed from memory during the bottom-up synthesis process for that design. This technique has proven inaccurate not only in its own environment, but also when the model is ported to a new environment. This model-dependent synthesis results in a design that is very different from that obtained with the actual gate-level netlist of the modeled block. In trying to reduce memory requirements, this technique loses an unacceptable amount of precision. Also, as the ASIC industry matures, many vendors provide users of ASIC design tools with proprietary core blocks of circuits. These proprietary circuits substantially reduce the design time required for ASIC development. However, vendors of such circuits must disclose details of the design of the core circuit for use in synthesizing the entire ASIC. This would end up disclosing proprietary information that would otherwise be confidential, which is undesirable. Therefore, it is desirable to provide a tool that can help improve compilation speed and reduce memory requirements when hierarchically synthesizing large ASIC designs without sacrificing accuracy. Further, it is desirable that the results of running such tools be portable between multiple design environments and synthesis tools to facilitate design reuse. Furthermore, it would be desirable to provide information about a proprietary module in a format that protects the intellectual property of the owner of the module, while at the same time allowing accurate synthesis of ASICs using the module. SUMMARY OF THE INVENTION The present invention provides a practical approach for the synthesis of ASICs consisting of millions of gates based on the use of synthesis shells. A synthetic shell is created by starting with a gate-level description of a fully characterized block. This gate-level description is generated by removing internal gates and creating a gate-level synthesis shell that is a subset of the synthesized block. The synthesis shell provides the input load and fanout of the block, the output delay of the block to the clock, the output drive of the block, the setup / hold constraints on the input signal for the block's clock, and the input to output delay for the passing signal of the block. Save. Such a synthetic shell can be used instead of the original design netlist. Therefore, the synthetic shell is used for hierarchical synthesis in a customer's design environment or as an offering from an ASIC service provider to protect the intellectual property rights of the provider. be able to. All the information needed by the compositing side is available in the compositing shell in the form of a netlist, and the shell is very accurate since additional information is provided to reconstruct the original loading and region information. It is. The synthesis shell described above includes a gate-level description that is a subset of the synthesized blocks. This reduced description is obtained by removing elements of the gate level description according to a set of criteria, including: That is, storing the combination path from the input port to the first storage element (element), storing the combination path from the last storage element to the output port, and setting the direct combination path from the input port to the output port. Preserving, preserving clock distribution path, preserving feedback path from output port to storage element with its storage element, preserving feedback path to direct combination path in design, to asynchronous RAM If the write signal is traced to the input port, save the asynchronous RAM, otherwise treat the asynchronous RAM as combinatorial logic and treat the synchronous RAM as a storage element, clocked by the resulting internal clock. Any storage element can be combined with input port or output port If the via to or is directly connected, to save the storage element to produce internal clock, and an asynchronous path, reset, be stored as such clear, it is. To generate the composite shell, area difference data indicating the difference between the area required for the original block and the area required for the elements stored in the composite shell is generated, and the area difference data is used by the composite shell. Including the step of including. In addition, load information is stored using a synthesis shell, which indicates the load inside the synthesis shell associated with the synthesis process, and on each node in the path from the last storage element to the output in the block. 5 shows the load and shows incremental loads on the clock and asynchronous paths. Here, the incremental load is a load on the net that compensates for the removal of the gate connected to the net. The shell's direct implementation is expressed in the form of a netlist, despite a subset of the original netlist for the subject of the shell's blocks. The shell maintains sufficient information in a subset of the netlist so that if the original netlist is replaced by this subset, it has no effect on the synthesizer, and It is still possible to access all the information that would have been obtained. The size of the shell netlist is much smaller, because its composition depends on a subset of the original netlist. Therefore, the memory requirement for storing the shell netlist is smaller. The shell is portable between different process, voltage, and temperature (PVT) conditions, can be ported from vendors to integrated circuit designers, and can be generated by designers during hierarchical synthesis. You can also. Accordingly, the present invention is characterized as a method of synthesizing a gate level description of an integrated circuit module including a plurality of blocks from a behavior or register transfer level description of the module. The method communicates design constraints and synthesizes a plurality of first blocks from the behavioral description of the block. This synthesized gate level description is reduced to a synthesis shell, as described above. Next, the method combines the second block in the plurality of blocks by processing the action description of the second block with reference to the combining shell to create a gate-level description of at least one other block. About doing. This method of synthesizing an integrated circuit module further completes the overall design of a further block in a recursive manner with reference to the synthesis shell of the first and second blocks and the behavioral description of the other blocks. Up to processing to combine. Further, the process includes integrating the two-block composite shell into a higher-level composite shell. The merged file is then reduced to a merged synthetic shell that can replace a lower level synthetic shell combination. The present invention includes resources for creating and / or storing a composite shell created by performing the above-described method and / or processing resources for executing a composite algorithm utilizing the composite shell. Characterized as a device. Therefore, the processing time and memory required for synthesizing a large-scale ASIC having several million gates can be reduced. According to the prior art, the synthesis of large designs has limited available computing power, creating speed and resource bottleneck problems. The main cause of this bottleneck is that in the prior art, the entire design netlist must be held in memory even for a block that has been optimized. The synthesized block was required to be present in memory because it could have a break in characterizing other blocks in the synthesis. The synthesis shell according to the invention is based on the extraction of relevant information from the synthesized block, and the characterization of other blocks during synthesis is still accurate. The advantage of this shell is that storing the extracted blocks requires a much smaller memory requirement than storing the entire netlist of the synthesized blocks in memory. Therefore, the advantages of the present invention include the following. That is, 1. 1. reduction of memory requirements; 2. reduction of run time; 3. The accuracy of representation and use in hierarchical design synthesis is not different from the original design. 4. Relying on a netlist approach to a synthesis shell that is portable between multiple synthesis tools and design environments; 5. In a system where a designer provides a previously designed cell for use in his or her own ASIC, the accuracy of the usage information is preserved; 6. Compatible with the hierarchical top-down characterization and bottom-up optimization methods used in ASIC synthesis; Protect intellectual property rights to the proprietary core that Shell represents. Other features and advantages of the invention can be understood by reference to the following drawings, detailed description, and claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified block diagram of a system that includes processing resources for generating a composition shell and performing composition based on the composition shell according to the present invention. FIG. 2 illustrates the process of ASIC design including synthesis based on the use of a synthesis shell and synthesis shell generation according to the present invention. FIG. 3 is a flowchart of a recursive synthesis process based on synthesis shell generation according to the present invention. FIG. 4 is an exemplary block diagram used to illustrate the synthesis flow according to the present invention. FIG. 5 is an exemplary block diagram used to illustrate cell deletion based on pre-specified rules for shell generation. FIG. 6 is an exemplary block diagram used to illustrate one rule, the storage of internally generated clocks, according to the present invention. FIG. 7 is an example illustrating an integrated shell according to one aspect of the present invention. FIG. 8 is a flow chart illustrating the process of shell creation according to the present invention. FIG. 9 is a flowchart illustrating the technique of region balancing during shell generation according to the present invention. FIG. 10 is a flowchart illustrating a technique for storing load information on a specific net in a synthetic shell. 11 to 16 are schematic diagrams of representative circuit blocks and shells of the circuit blocks represented by the code samples of the appendixes (Appendix AC), which are examples of the synthetic shell process according to the present invention. Is explained. DETAILED DESCRIPTION A detailed description of a preferred embodiment of the present invention is provided with reference to FIGS. Here, FIG. 1 gives an overview of the apparatus used in the generation of a synthetic shell and the use of the synthetic shell in the synthesis of an ASIC according to the invention. FIGS. 11 to 16 are used to illustrate examples of entire netlists and composite shells in the appendix. The apparatus shown in FIG. 1 includes a central processing unit (CPU) 10 coupled to a bus 11. Further, an input / output device 12 and a display system 13 are connected to the bus 11. In this device, a data memory 14 and an instruction memory 15 are provided and connected to the bus 11 for use by the CPU 10. The data memory according to the present invention includes a register tran sfer level of the ASIC under development and other behavioral descriptions. The data memory is also used to store the gate-level description of the ASIC after synthesis and the shell of the synthesis shell or circuit blocks within the ASIC under development. This block diagram provides a heuristic view of the apparatus for storing and processing a synthesis shell and process in accordance with the present invention. This figure is intended to represent, for example, components of a commercial work station or personal computer that include the additional elements described in this application. According to the invention, the instruction memory 15 includes a synthesis tool, with a synthesis shell generation process according to the invention and a region balancing process for synthesis shell generation. In addition, the synthesis tool can synthesize blocks within the ASIC under development, relying on the synthesis shell for already synthesized blocks. Thus, the instruction memory includes development and verification tools used to implement a hardware description language such as VELILOG or VHDL. These design tools provide all the functionality needed to port a design from the hardware description level to a workstation. These features include synthesis tools, timing analysis tools, floor planning tools, layout tools, packaging tools, and more. According to the present invention, these functions also include the generation of a synthetic shell having a region balancing function as described above and described in more detail below. FIG. 2 illustrates the content of creating and using a synthetic shell according to the present invention. Accordingly, FIG. 2 illustrates a design flow for ASIC development, which includes generation of an ASIC specification (block 100) and synthesis of an ASIC gate-level description based on this specification (block 100). 101) and the resulting layout of the gate-level description (block 102), which are used during ASIC fabrication. The present invention provides an improvement in synthesis resources. Thus, synthesizing includes, for example, providing an ASIC behavioral description using a hardware description language at the register transfer level (RTL) (block 103). This behavior description is translated and optimized (block 104). The result of the translation and optimization steps is a gate-level netlist for the ASIC (block 105). According to the present invention, a synthetic shell is used during translation and optimization of the synthesis. In accordance with the synthesis method, action codes, for example, RTL codes, and design constraints for the ASIC are provided (block 106). Based on this information, the ASIC is characterized and optimized to provide a gate level description (block 107). Finally, a synthesis shell netlist is obtained for the block being synthesized (block 108). The shell is marked "don't touch" and stored for synthesis of further blocks in the ASIC (block 109). This composite shell netlist is obtained using a shell generation process that includes reading the optimized block (block 110). Rules that apply a set of criteria are applied to remove gates from the synthesized design for the circuit block (block 111). Finally, the shell netlist and other necessary files for the shell are written for use in the synthesis of the ASIC balance and the original block is removed (block 112). The rules applied in block 111 include the basic shell generation rules, which result in the removal of gates from inside the circuit blocks that are not necessary for ASIC balance synthesis (block 113). Special cases and hierarchical considerations are then added to the resulting gate list level shell (block 114). The load on the net required for further synthesis is restored in the synthesis shell (block 115). Region information for the original gate-level description for the circuit block is saved by region balancing in a reduced netlist used as a synthesis shell (block 116). Finally, the results of the synthesis shell can be used for further synthesis of other blocks (block 117). FIG. 3 provides a more detailed block diagram of the synthesis process according to the present invention. Thus, FIG. 3 defines the synthesis flow used to characterize and optimize large designs. Given the input / output attributes and timing constraints, characterize the module (block 200). Characterization is a top-down process that provides the calculation of all I / O attributes on the pins of the module being characterized. This process is performed by communicating the I / O characteristics of the top-level module and the remaining effects of the circuit to the input and output of the module being characterized. Characterization is a top-down process because the characteristics of the module at the top level of the hierarchy must be determined before the characteristics of the sub-modules can be determined. Having characterized the module, the process proceeds to optimize the module (block 201). Optimization is a bottom-up process that starts with a small block of the design. The synthesis shell for a module is created as soon as the module is fully optimized and mapped to a gate, ie, synthesized in the current environment. This is also the point where the module is marked "don't touch". As shown in block 202, after the delay prediction and timing analysis, if the timing and other constraints are satisfied, the attribute "don't touch" is given to the module (block 203) and the synthetic shell is Once created, the module is replaced by the shell (block 204). If the timing and other constraints are not satisfied at block 202, the shell is re-optimized starting at block 201. The composite shell is created at block 204 by a rules-based technique that reduces the gate-level description of the optimized block based on a set of criteria. The module for which the shell is created must satisfy the following constraints: That is, 1. Must be completely synchronized. 2. It must be fully verified that all design constraints are satisfied. 3. Must be at the gate level. 4. It must be optimized to the point where it can be marked "don't touch". If these constraints are satisfied, the module can be converted to a synthetic shell. The synthetic shell must store the following information: That is, 1. 1. Input load and fanout 2. Output delay with respect to clock 3. Setup / hold constraints on input signal to clock Input to Output Delay for All Passed Signals FIG. 4 is a circuit diagram used to provide an example of a synthesis flow based on a synthesis shell according to the present invention. First, the circuit shown in FIG. 4 is defined at the activity level. The purpose (object) is to optimally synthesize the circuit. The hierarchy defined by circuit block A includes a top level having block B, and shells C and D. Shells C and D are shown to emphasize that the synthesis process may depend on a shell that has already been created. Block B includes another level of the hierarchy defined by blocks E and F. The connection relationship is indicated by arrows, and arrow 11 is an input given to blocks A, B and E. 12 is an input connected to blocks A, B, E and F. Also, 12 is provided as an input to shells D and C. 13 is an input to the block A and the shell C. 13 is an input to the block A and the shell C. 14 is an input to the block A and the shell D. The outputs O1 to O3 are connected as follows. Output O1 is the output from blocks E, B and A. Output O2 is the output from shell c and block A. Output O3 occurs in shell D and is provided as output from block A. The internal nets N1 and N2 are connected as follows. The net N1 is generated in the block E and supplied to the block F. Net N2 is generated in block F, provided as an output from block B, and connected as an input to shells C and D. In this example, input 12 represents a clock. All other inputs and outputs are specified in relation to the clock. In this case, the following processes of synthesis and characterization are performed to provide an optimal circuit. In the next list of steps, shells C and D are created from the actual blocks C and D. (Timing analysis can be performed as soon as the block's gate-level netlist becomes available.) Characterize all blocks from the top down (eg, B then E and F). Synthesize E, floorplan it, and characterize E again. Characterize B and then F again. Synthesize F, floorplan it, and characterize F again. Characterize E again. E and F are timing analyzed. If necessary, re-synthesize and re-characterize E. Do the same for F. (However, this can result in a sequential process that does not converge, in which case the criteria to stop the process apply.) Mark E and F as "do not touch". Create shells for E and F and substitute them for each shell. Characterize B again. Combine B and floorplan it (this can change the floor planning of E and F). Characterize B again and perform timing analysis. If necessary, characterize and floorplan B again. Mark B as "Do not touch." Create a shell for B and substitute B for that shell. Characterize C and D again. Synthesize C, floorplan it, and characterize C again. Characterize D again. Synthesize D, floorplan it, and characterize D again. Timing analysis of C and D. If necessary, resynthesize and characterize C again. Do the same for D. (However, this can result in a sequential process that does not converge, in which case the criteria for stopping the process apply.) Mark C and D as "do not touch." Create shells for C and D and substitute them for each shell. Combine A and floorplan it (this can change the floor planning of B, C and D). A is analyzed for timing. The composition manager produces a rule-based characterization for every block in the hierarchy. For example, input I1 to block E is well specified by assumptions made for the associated wire delay. The clock connected to 12 is specified by assumptions on wire delays and loads on the net, because the other two blocks to which I2 is connected are also at the RTL level. Similarly, net N1 is identified based on assumptions while the output connected to O1 is completely identified. Block E and all other blocks are characterized in this way. In this case, the following process of synthesis and characterization is performed to provide the optimal circuit. (Timing analysis can be performed as soon as a gate-level example of a block becomes available.) Characterize all blocks top down (eg, B then E and F). Synthesize E, floorplan it, and characterize E again. Characterize B and then F again. Synthesize F, floorplan it, and characterize F again. Characterize E again. E and F are timing analyzed. If necessary, re-synthesize and re-characterize E. Do the same for F. (However, this can result in a sequential process that does not converge, in which case the criteria for stopping the process apply.) Mark E and F as "do not touch". Create shells for E and F and substitute them for each shell. Characterize B again. Combine B and floorplan it (this can change the floor planning of E and F). Characterize B again and perform timing analysis. If necessary, characterize and floorplan B again. Mark B as "Do not touch." Create a shell for B and substitute B for that shell. Characterize C and D again. Synthesize C, floorplan it, and characterize C again. Characterize D again. Synthesize D, floorplan it, and characterize D again. Timing analysis of C and D. If necessary, resynthesize and characterize C again. Do the same for D. (However, this can result in a sequential process that does not converge, in which case the criteria to stop the process apply.) Mark C and D as "do not touch." Create shells for C and D and substitute them for each shell. The output of the register 318 is provided via the inverter 314 and the inverter 321 to generate the output Out1. The output of register 320 is provided to inverter 322, provides output Out2, and becomes one input to AND gate 324 via buffer 323. The second input to AND gate 324 is the Out2 signal. The output of AND gate 324 provides signal Out4. Input signal 302 is provided via inverter 325 to a combination cloud 326 that generates signal Out3. Referring to FIG. 5, the timing rules for removing cells from the gate list can be discussed. In FIG. 5, elements marked X are not saved to the shell. 1. The combination path from the input port to the first storage element on the path of the circuit needs to be preserved. This is necessary to reconstruct any input delays and calculate storage element setup and hold times. Thus, for example, the cells along arrow K1 in FIG. 5 need to be saved, including NAND gate 305, AND gate 306, and register 310. Similarly, gate 304, gate 308, and register 309 need to be saved. The net from the output of register 309 to the input of gate 306 is not saved. 2. Any combination path from the last storage element to the output port needs to be maintained. This is necessary in order to be able to reconstruct the data arrival time for the block dependent on this output port and the delay after which data will be available at the output port. Therefore, the elements near arrow K2 in FIG. 5 need to be saved. That is, register 320 and gate 322 should be saved according to this rule. Also, register 318, gate 314, and gate 321 should be preserved. 3. Any direct combinatorial paths from the input ports to the output ports of the block for which the shell is made need to be preserved. This is essential for reconstructing the data arrival time from the shell at the input of other blocks dependent on this output. Therefore, the elements along arrow K3 in FIG. 5 need to be preserved. Therefore, the inverter 325 and the combination cloud 326 should be saved. 4. Clock distribution networks need to be preserved. Therefore, the net defined by line 303 needs to be preserved. 5. Feedback paths arising from unbuffered output ports affect the setup time of the storage elements to which they are connected based on output loading. Therefore, such a feedback path should be preserved with the affected storage element. Thus, for example, the elements on the branch of the route defined by output Out1 along path K4 in FIG. 5 need to be preserved. As a result, the gate 307, the gate 304, the gate 308, and the register 309 are saved. 6. Feedback paths from the output, including pure combinational logic, need to be preserved. Thus, in FIG. 5, buffer 323 and AND gate 324 are saved, along with a branch along arrow K5 from output Out2 to the input of AND gate 324. 7. Asynchronous structures such as resets and sets need to be preserved. Thus, if any of the registers in the circuit of FIG. 5 include a set or reset input, the net used to generate these signals should be preserved in the synthesis shell. Although not shown in FIG. 5, in the case of a memory device, the following special cases need to be considered. That is, 1. If the memory cell is an asynchronous RAM, it should be treated like any other combinational logic and should not be deleted unless the data provided to it comes from storage elements. This special case occurs when the write signal to this RAM can be traced to the input port. In such a case, the RAM should be saved. 2. A synchronous RAM is treated like a storage element. If all the signals arriving and leaving the RAM are latched, the RAM can be deleted, otherwise it should be preserved. 3. The flip-flops that generate the internal clock need to be preserved if any of the storage elements they clock are connected to input or output ports via combinatorial logic or directly. This case is illustrated in FIG. 6, which includes a combination cloud 360 that receives input A on line 361. A clock signal for clocking register 363 is provided on line 362. The output of register 363 is provided via combination cloud 364 which provides data input to register 365. This register is clocked by the signal on line 322. The output of this register 365 is used to clock register 366. The data input to register 366 is provided at the output of combination cloud 360. Thus, element 365 needs to be saved because it clocks register 366, which receives its data from input A via combinational logic. According to the above criterion, cells can be deleted from the gate level description of a circuit block to create a composite shell. In addition, many blocks can be optimized into cells. In this case, the interconnected shells can be integrated into one. Next, the two shells are viewed from the top level and the preceding rules are applied, resulting in a super shell consisting of existing subshells as illustrated in FIG. Accordingly, the first shell 400 and the second shell 401 shown in FIG. 7 are combined into an integrated shell 402. First shell 400 includes storage element 403 and storage element 404 that provides output via combinational logic 405. The output of logic 405 is provided out of first shell 400 as an input to second shell 401. The second shell includes an input register 406 and a register 407 that provides an output via combinational logic 408. An integrated shell is created, resulting in the deletion of registers 404 and 406 and combination logic 405 for super shell 402. In addition, it needs to be preserved according to the rules described above and has some deleted gates in its transitive fanout, ie connected to the nodes in the path but stored in the shell Paths with deleted gates that do not need to be loaded need to be load restored. Such load balancing is necessary when the internal feedback gate from the buffered output is removed because the load on the path from the storage device to the output is affected. It is. The load on each node in the path from the last storage element to the output port needs to be restored. Thus, the capacitance on the net heuristically represented by the capacitor 351 of FIG. 5 needs to be restored and retained, satisfying this case, where the gate 315 has the internal feedback feedback removed. It is a gate and affects the load on Out1. Incremental loads that appear along the clock net are dumped out and need to perform load recovery on the clock net. Therefore, incremental loads on clock net 303 that compensate for removal of elements 312 and 316 need to be preserved. Since the two main goals of synthesis are area and timing, the area (area) of the shell evaluated by the synthesizer must be the same as the netlist from which the shell was created. The original region is available based on the original gate-level description, as is the region of the reduced netlist generated for the shell. Therefore, model a dummy cell that has no function, but has a region parameter set equal to the region difference between the original netlist and the reduced netlist, and replaces the dummy cell with the reduced netlist. By giving an example at, the equilibrium of the regions is given. Three types of regions are evaluated by the synthesizer. That is, a combination area, a non-combination area, and a net area. Combined, uncombined and net regions can be restored by showing examples of dummy combined cells, dummy sequential cells and dummy nets. These dummy elements have no function but provide area information. Dummy cells are specific to each design technique, and are therefore modeled as library files and compiled into the user's home directory. The region balancing cells are separate from the shell netlist because the wireload module actually determines the net region and only one wireload module can be selected for each level of the hierarchy. Is illustrated as a block. Therefore, under the assumption that the top-down design has one level of the hierarchy where three blocks (Block 1, Block 2 and Block 3) exist, calling the synthetic shell generation routine with the synthetic shell option Will result in the following files under the following options: That is, 1. A synthetic shell netlist containing the gates that remain after rule-based gate removal and dummy gate inclusion for region balancing. The netlist also includes distinct levels of the hierarchy below the top level, called dum_area, which illustrates the three components dum_comb, dum_seq, and dum_net. The dum_comb cell is connected to the dum_seq cell by one net. Descriptions of these components are available in library files. 2. Library files in synopsys format or any synthesis tool format. It has one combination cell called dum_comb, which has no function but has a region equal to the region (area) of the deleted combination cell. It also includes a cell called dum_seq that has an area equal to the entire area of the non-combined cell that has no function but has been removed from the design. dum_net is a wireload model where the wireload area per unit fanout is equal to the difference between the estimated net area of the original netlist and the netlist with the gate removed. 3. A block loading file that contains loading information for all components and nets in the original design. In the case of an integrated shell, the composite shell program collapses Block 1 and Block 2 into one level of hierarchy, creating one shell. As far as the output file is concerned, the program produces two files: a corrupted netlist for block 1 and a corrupted netlist for block 2. The only difference between the original shell netlist and the corrupted netlist file is that in the case of the original shell netlist file, the netlist is generated assuming one top level. It is. However, a collapsed netlist file is a netlist that is created after combining two or more levels to create a shell, as described above with reference to FIG. FIGS. 8, 9 and 10 provide the shell generation flow, region balancing and load recovery used in shell generation according to the present invention. In FIG. 8, the following terms are used to help understand the concepts behind shell creation. "Root". Any input or output port of a circuit block is called a root. For example, in FIG. 5, the nodes 300, 301, and 302 are the roots. The outputs Out1, Out2, Out3, and Out4 are also routes. "Branch". A branch is a fan-out resulting from a root. Thus, referring to FIG. 1, the path from point 300 represented by line 353 to the input of gate 304 is a branch, and the path from node 300 represented by net 354 to the input of gate 305 is also This is a branch because it is a fan-out of the input port 300. "Shoot". A shoot is a fanout resulting from a macrocell. In FIG. 5, the input of the inverter 321 to the inverters 314 and 313 is a shoot. "Shoot in". Shoot-in is a shoot connected to the input of the cell. For example, the net Sin1 in FIG. 5 is a shoot-in to the gate 313. "Shoot out". Shoot out is the shoot connected to the output of the cell. For example, the net Sout1 in FIG. 5 is a shoot out to the gate 314. "Leaf". A leaf is any storage element that terminates a timing path. Every flip-flop and latch in a design is a leaf. FIG. 8 gives the process flow for shell creation. The algorithm starts from the beginning (block 500). The first step is to locate the next route to be processed and identify whether it is an input or an output (block 501). Next, the algorithm determines whether the route carries a clock, set or clear signal (block 502). At block 502, if it does not issue a clock, set or clear signal, the algorithm locates the next (or first) branch on the route (block 503). For this branch, the cells on the branch are marked for holding (block 504). Next, it is determined whether the cell is a leaf (block 505). If not, the level index i is set to 1 (block 516) and the next shot on the cell for this level is located (block 507). Next, the algorithm determines whether the corresponding route is an input route (block 508). If so, it is determined whether the shot is a shoot-in (block 509). If it is a shoot-in at block 509, the cell is marked for load recovery (block 510) and the algorithm loops back to block 507 to locate the next shoot. If not, or if the corresponding route was an input at block 508, the algorithm marks the cell as being retained (block 511). Next, the algorithm determines whether the cell marked to be retained is a leaf (block 512). If it is not a leaf, index i is incremented (block 513); otherwise, index i remains unchanged. Next, the algorithm determines whether all shots on this index level i have been processed (block 514). Otherwise, the algorithm loops back to block 507 to process the next shot. If at block 514 all shots have been processed for this level, the algorithm determines whether index i is zero (block 515). If i is not zero, i is decremented by one (block 516) and the algorithm loops to block 514. If i is zero at block 505, the algorithm determines at block 517 whether all branches for that route have been processed. Otherwise, loop back to block 503 to process the next branch. If all branches on the route have been processed, the algorithm determines whether all routes have been processed (block 518). Otherwise, the algorithm branches back to point A at block 501, as shown. If all routes have been processed, the algorithm ends, as indicated by the end (block 519). If the route is determined to be a clock, set or clear signal at block 502, the algorithm locates the next (or first) branch to process (block 520). Next, it is determined whether the cell on this branch is a leaf (block 521). If so, the algorithm determines if there are other branches on the route (block 530). If all branches on the route have been processed, the algorithm loops back to block 520. If it is determined at block 530 that all branches for that route have been completed, the algorithm branches back to block 501 to process the route. If the cell is not a leaf at block 521, the algorithm branches to block 522 and sets index i to zero. Next, the algorithm marks the cell as to be retained (block 523) and increments index i by one (block 524). After incrementing the index, the algorithm locates the first or next shoot at level i (block 525). Then, it is determined whether the cell on the shoot is a leaf (block 526). If the cell is not a leaf, the algorithm branches to block 523 and marks the cell as holding. If the cell is a leaf, the algorithm determines whether all shots at level i have been processed (block 527). If not, the algorithm returns to block 525 to process the next shot. If all shots have been processed, the algorithm determines whether the index is equal to one (block 528). If the index is not one, it is decremented by one (block 529) and the algorithm returns to block 527 to process other shots at lower levels. If the index i is equal to 1 at block 528, the algorithm branches to block 530 and determines whether all branches have been processed. If not, the algorithm returns to block 520 and proceeds to the next branch. If all branches have been processed in block 530, the algorithm loops back to block 501 and continues processing. FIG. 9 illustrates the region balancing process for the timing shell netlist. The process begins at start block 600. The first step involves reading a technology library for the circuit block being synthesized (block 601). Next, combinations, uncombinations, and net regions of the original design are determined (block 602). Next, the combination, non-combination, and net area of the created shell are determined (block 603). The difference between these two files is written to the library file (block 604). Next, the combined, uncombined, and net regions of the shell are created by compiling the library file (block 605). These dummy cells are inserted into the timing shell and the process ends (block 606). FIG. 10 illustrates the process of load recovery for a composite shell generated according to FIGS. 8 and 9. The algorithm begins at start block 600. The first step involves positioning the first or next leaf in the circuit (block 601). The next step is to determine if this leaf has been marked for retention in the cell generation process (block 602). Otherwise, the clock, clear and load on the set net for that leaf is restored (block 603). If so, the algorithm loops back to block 601. After block 603, the algorithm determines whether all leaves have been processed (block 604). Otherwise, the algorithm loops back to block 601 to process the next leaf. If all leaves have been processed at block 604, the algorithm proceeds to block 605, where loads on cells marked for load recovery in the shell generation process are load recovered. After this process, the algorithm ends (block 606). This is followed by Appendices A, B and C. Appendix A is a sample behavior code in the VELILOG language for an adder; Appendix B is a synthesized netlist in NDL format for the adder represented by the code in Appendix A; Appendix C is a synthetic shell in NDL format created according to the present invention. The complete synthesized netlist shown in Annex B describes a circuit with 28 macrocells. For example, FIGS. 11, 12 and 13 show the top-level circuits of this synthesized netlist. As shown in FIG. 11, fourteen registers labeled FD 1 and sub-blocks labeled BITADD are present in this top-level schematic. FIG. 12 shows a sub-block of a first adder having five gates, and FIG. 13 shows a sub-block of a second adder having nine gates. This corresponds to the 28 gates defined by the full gate-level netlist of the adder described in Appendix B. Appendix C shows a reduced netlist for a synthetic shell according to the present invention. This reduced netlist has only 14 gates and one dummy cell, as shown by the circuit diagram of FIG. As shown, FIG. 14 has a block with 14 gates and 2 gates removed. The block with the gate removed can be represented by the circuits shown in FIGS. As shown, FIGS. 15 and 16 are simply the inputs and outputs of the sub-blocks in the circuit. Thus, Appendix C shows the resulting composite shell in netlist format. In Appendix C, the dummy cells are represented by lines 71. As described above, this dummy cell provides a reference to the cell library where the description of the dummy cell for the reduced netlist has been provided. A representative dummy module begins at line 122 of Appendix C. Line 128 corresponds to the fake cell fk_arseq () in the region balancing library for the sequential region, and line 129 points to the fake cell fk_ar_com () for the combination region. The net defined in the dummy module is the above-mentioned area-balancing dum_net. Thus, new tools useful for the synthesis of large scale integrated circuits (LSIs) are provided based on the synthesis shell configuration used in data processing environments. Synthetic shells can be ported to customers who rely on circuit blocks represented for ASIC design, or generated as part of the synthesis of large scale integrated circuits. The use of a synthesis shell greatly reduces processing requirements in terms of time and memory consumption when synthesizing large ASICs. The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. There is no iT OTAL, such as trying to be exhaustive or to limit the invention to the exact form disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. It is intended that the scope of the invention be defined by the following claims and their equivalents:

[Procedure of Amendment] Article 184-8, Paragraph 1 of the Patent Act [Submission date] March 4, 1997 [Correction contents]   The description in the claims is amended as follows.   [1. Include multiple circuit blocks from the behavioral description of the module A method for synthesizing a gate level description of an integrated circuit module, comprising:   The first block in the plurality of blocks is referred to as the row of the first block. The first block is synthesized by processing the dynamic description. Generating a predicate;   Reducing the number of gates in the gate level description of the first block Has fewer gates than the gate level description of the first block Generating a synthesized shell including a gate level description of the circuit, wherein The composite shell has the same number of input loads and fanouts as the first block, The output delay for the same clock as the first block, the same as the first block Output drive, set to an input signal for the same clock as the first block Up / hold constraints and input for the same pass signal as in the first block A step having a delay from force to output;   At least one other block in the plurality of blocks is Processing the action description of the at least one other block with reference to the To produce a gate-level description of said at least one other block. Steps to make   A method comprising:   2. The method of claim 1, wherein a gate level description of the first block. Includes a parameter specifying an area required for the first block. Wherein the step of reducing includes:   Area required for the first block and elements in the composite shell Generating region difference data indicating a difference from a region required for Using the method to include the region difference data.   3. 2. The method of claim 1, wherein the step of reducing comprises:   Load on each node in path from last storage element to output port Information indicating (load) and clock and incremental load on asynchronous path Storing the method.   4. 2. The method of claim 1, wherein the composite shell comprises a first shell. A gate-level description that is a subset; Deleting elements of the gate level description of the first block according to a standard A method comprising:   5. 5. The method of claim 4, wherein a gate level description of the first block. Identifying the area required for the first block and the step of reducing ,   Area required for the first block and elements in the composite shell Generates area difference data indicating a difference from the required area, and For use in combining at least one other block in a plurality of blocks Associating with the composite shell.   6. 5. The method of claim 4, wherein the set of criteria is:   Storing the combined path from the input port to the first storage element. How to sign.   7. 5. The method of claim 4, wherein the set of criteria is:   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic A method characterized by including treating.   8. 5. The method of claim 4, wherein the set of criteria is:   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly Storing the storage element that produces the internal clock. Way.   9. 5. The method of claim 4, wherein the set of criteria is:   Including storing the combined path from the last storage element to the output port. How to sign.   10. 5. The method of claim 4, wherein the set of criteria is:   Including storing the direct combination path from the input port to the output port. Features method.   11. 5. The method of claim 4, wherein the set of criteria is:   A method comprising storing a clock distribution path.   12. 5. The method of claim 4, wherein the set of criteria is:   Stores feedback path from output port to storage element with that storage element A method comprising:   13. 5. The method of claim 4, wherein the set of criteria is:   Saving the feedback path to the path composed of combinational logic A method comprising:   14． 5. The method of claim 4, wherein the set of criteria is:   A method comprising storing an asynchronous path.   15. 5. The method of claim 4, wherein the set of criteria is:   Storing a combination path from the input port to the first storage element;   Storing the combined path from the last storage element to the output port;   Storing the direct combination path from the input port to the output port;   Preserving the clock distribution path,   Stores feedback path from output port to storage element with that storage element To do   Storing a feedback path to a path composed of combinational logic; ,   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic And treat   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly In some cases, including storing a storage element that produces an internal clock;   Preserving the asynchronous route,   A method comprising:   16. The method of claim 1, wherein the at least one other block is combined. The steps performed are:   The gate level description of the second block is entered into the input log for the second block. Mode and fan-out, output delay with respect to the clock of the second block, An output drive for the second block, an input signal for the clock of the second block; To the setup / hold constraints on the signal and the signal passing through the second block Reducing the input-to-output delay to a second composite shell that preserves the delay; ,   Combining the other blocks in the plurality of blocks with the composite of the first block The other block with reference to the shell and the second composite shell of the second block. By processing the behavioral description of the block to generate the at least one other block. Generating a gate-level description of the   A method comprising:   17． The method of claim 16,   A synthetic shell merging the synthetic shells of the first and second blocks And the integrated composite shell includes the first and second composite shells. Input load and fanout for the block, this integrated first and second Output delay for block clock, integrated first and second blocks Output drive, clock for the integrated first and second blocks Setup / hold constraints on the input signal, and the integrated first and second Saving delay from input to output for passing signal of block 2 how to.   18. A method of creating a gate level description of a circuit block, comprising:   Processing the gate-level description and, according to a set of criteria, Deleting the elements of the gate level description, wherein the set of criteria comprises: , Input load and fan-out for the circuit block, Output delay with respect to clock, output drive of said circuit block, said circuit block Setup / hold constraints on the input signal to the clock of the clock, and Preserving the delay from input to output for the passing signal of the circuit block, ,   The gate-level description of the remaining elements is Memorizing in the memory,   A method comprising:   19. 20. The method according to claim 18, wherein the gate level of the circuit block is determined. The statement identifies the area needed for the circuit block and the processing steps. The top   The area required for the circuit block and the elements in the composite shell are Generate area difference data indicating the difference from the required area, and use the Including the step of including region difference data.   20. 19. The method of claim 18, wherein said processing comprises:   Load on each node in path from last storage element to output port And information indicating the clock and the incremental load on the asynchronous path. A method comprising the steps of:   21. 20. The method of claim 18, wherein the set of criteria is:   The combination path from the input port to the first storage element in the circuit block is maintained. To exist,   Save the combination path from the last storage element of the circuit block to the output port That   Saving a direct combination path from an input port to an output port of the circuit block And   Storing a clock distribution path in the circuit block;   A flow from an output port of the circuit block to a storage element in the circuit block Storing the feedback path with the storage element;   Feedback in the circuit block to a path composed of combinational logic To save the traffic route,   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic And treat   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly In some cases, including storing a storage element that produces an internal clock;   Preserving the asynchronous route,   A method comprising:   22. 20. The method of claim 18, wherein the circuit block comprises first and second Including a sub-block, wherein the processing step comprises: Processing a gate-level description to generate the first sub-block according to the set of criteria; Reading the elements of the gate level description of the Processing a gate-level description of the second sub-block according to the set of criteria And removing the remaining elements of the first and second sub-blocks. A gate-level description consisting of a combination of gate-level descriptions is processed to process the composite system. Generating a gel.   23. 19. The method of claim 18, wherein said processing comprises:   The input and output ports for the circuit block are recursively checked and If the signal on the port is not a clock, set, or clear signal, the port Inspecting the branch of   Mark each branch so that the cells on that branch are maintained. Determining whether the cell is a leaf;   If the cell is not a leaf, shoot each cell against the cell. Inspection until the leaf is reached on the cell, and the shoot on the cell is the output of another cell. Or if the port being inspected is an input, keep the other cell Mark to be held, otherwise, on the shoot to be loaded Marking the cell as restored;   If the signal on the port is a clock, set or clear signal, Inspect the branch of the port, then the leaf on each branch of said port Cells so that they are maintained until each shot on the Working steps,   Add a dummy cell to the resulting gate level description and add Equilibrating the area of   All clock, clear and set nets in the gate level description Load on all cells and on all cells marked for load recovery. Storing the data to be recovered;   A method comprising:   24. Includes memory for storing a synthesized shell of gate-level descriptions of circuit blocks. Device, the device comprising:   Processing the gate-level description and, according to a set of criteria, Deleting the elements of the gate level description, wherein the set of criteria comprises: , Input load and fan-out for the circuit block, Output delay with respect to clock, output drive of said circuit block, said circuit block Setup / hold constraints on the input signal to the clock of the clock, and Preserving the delay from input to output for the passing signal of the circuit block, ,   The gate-level description of the remaining elements is Memorizing in the memory,   An apparatus characterized by being created by a method comprising:   25. 25. The device according to claim 24, wherein the gate level of the circuit block is determined. The statement identifies the area needed for the circuit block and the processing steps. The top   The area required for the circuit block and the elements in the composite shell are Generate area difference data indicating the difference from the required area, and use the A step of including the region difference data.   26. 25. The apparatus according to claim 24, wherein the processing comprises:   Each in the path from the last storage element to the output port of the circuit block Load on the node and clock on the circuit block and on the asynchronous net Storing information indicative of an incremental load. Equipment to do.   27. 25. The apparatus of claim 24, wherein the set of criteria comprises:   The combination path from the input port to the first storage element in the circuit block is maintained. To exist,   Save the combination path from the last storage element of the circuit block to the output port That   Saving a direct combination path from an input port to an output port of the circuit block And   Storing a clock distribution path in the circuit block;   A flow from an output port of the circuit block to a storage element in the circuit block Storing the feedback path with the storage element;   Feedback in the circuit block to a path composed of combinational logic To save the traffic route,   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic And treat   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly In some cases, including storing a storage element that produces an internal clock;   Preserving the asynchronous route,   An apparatus comprising:   28. 25. The apparatus of claim 24, wherein said circuit block of said composite shell is Synthesizing a gate-level description of an integrated circuit module including a subject and other circuits, Processing resources synthesized from a shell and the behavioral description of the other circuit in the module A device comprising a source. 』

────────────────────────────────────────────────── ─── Continuation of front page    (81) Designated countries EP (AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, L U, MC, NL, PT, SE), OA (BF, BJ, CF) , CG, CI, CM, GA, GN, ML, MR, NE, SN, TD, TG), AP (KE, LS, MW, SD, S Z, UG), AM, AT, AU, BB, BG, BR, B Y, CA, CH, CN, CZ, DE, DK, EE, ES , FI, GB, GE, HU, IS, JP, KE, KG, KP, KR, KZ, LK, LR, LT, LU, LV, M D, MG, MN, MW, MX, NO, NZ, PL, PT , RO, RU, SD, SE, SG, SI, SK, TJ, TM, TT, UA, UG, UZ, VN (72) Inventors Ramachandran, Ravichandran             United States California 94089,             Sunnyvale, Wildwood Aveni             View 1235, Number 72 (72) Inventor Agrawal, Sarika             United States California 95054,             Santa Clara, Riverside Court               420, number 206 (72) Inventor Adkar, Sanjay             United States CA 94514,             San Jose, Humberside Court 3114 [Continuation of summary] Contains a subset of gate-level descriptions. This description Gate level according to a set of pre-specified criteria. By deleting the elements of the file description.

Claims (1)

[Claims]   1. A collection containing multiple circuit blocks from a behavioral description of a module A method for synthesizing a gate level description of an integrated circuit module, comprising:   The first block in the plurality of blocks is referred to as the row of the first block. The first block is synthesized by processing the dynamic description. Generating a predicate;   The gate level description of the first block to the first block Input load and fanout, output delay with respect to the clock of the first block. The output drive of the first block, with respect to the clock of the first block. Setup / hold constraints on the input signal, and the communication of the first block. Steps to reduce the input-to-output delay for over-signals into a synthetic shell that preserves When,   At least one other block in the plurality of blocks is Processing the action description of the at least one other block with reference to the To produce a gate-level description of said at least one other block. Steps to make   A method comprising:   2. The method of claim 1, wherein a gate level description of the first block. Includes a parameter specifying an area required for the first block. Wherein the step of reducing includes:   Area required for the first block and elements in the composite shell Generating region difference data indicating a difference from a region required for Using the method to include the region difference data.   3. 2. The method of claim 1, wherein the step of reducing comprises:   Load on each node in path from last storage element to output port Information indicating (load) and clock and incremental load on asynchronous path Storing the method.   4. 2. The method of claim 1, wherein the composite shell comprises a first shell. The method includes a subset of gate level descriptions, and the step of reducing includes a set of rules. Deleting elements of the gate level description of the first block according to a standard A method comprising:   5. 5. The method of claim 4, wherein a gate level description of the first block. Identifying the area required for the first block and the step of reducing ,   Area required for the first block and elements in the composite shell Generates area difference data indicating a difference from the required area, and For use in combining at least one other block in a plurality of blocks Associating with the composite shell.   6. 5. The method of claim 4, wherein the set of criteria is:   Storing the combined path from the input port to the first storage element. How to sign.   7. 5. The method of claim 4, wherein the set of criteria is:   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic A method characterized by including treating.   8. 5. The method of claim 4, wherein the set of criteria is:   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly Storing the storage element that produces the internal clock. Way.   9. 5. The method of claim 4, wherein the set of criteria is:   Including storing the combined path from the last storage element to the output port. How to sign.   10. 5. The method of claim 4, wherein the set of criteria is:   Including storing the direct combination path from the input port to the output port. Features method.   11. 5. The method of claim 4, wherein the set of criteria is:   A method comprising storing a clock distribution path.   12. 5. The method of claim 4, wherein the set of criteria is:   Stores feedback path from output port to storage element with that storage element A method comprising:   13. 5. The method of claim 4, wherein the set of criteria is:   Saving the feedback path to the path composed of combinational logic A method comprising:   14． 5. The method of claim 4, wherein the set of criteria is:   A method comprising storing an asynchronous path.   15. 5. The method of claim 4, wherein the set of criteria is:   Storing a combination path from the input port to the first storage element;   Storing the combined path from the last storage element to the output port;   Storing the direct combination path from the input port to the output port;   Preserving the clock distribution path,   Stores feedback path from output port to storage element with that storage element To do   Storing a feedback path to a path composed of combinational logic; ,   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic And treat   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly In some cases, including storing a storage element that produces an internal clock;   Preserving the asynchronous route,   A method comprising:   16. The method of claim 1, wherein the at least one other block is combined. The steps performed are:   The gate level description of the second block is entered into the input log for the second block. Mode and fan-out, output delay with respect to the clock of the second block, An output drive for the second block, an input signal for the clock of the second block; To the setup / hold constraints on the signal and the signal passing through the second block Reducing the input-to-output delay to a second composite shell that preserves the delay When,   Combining the other blocks in the plurality of blocks with the composite of the first block The other block with reference to the shell and the second composite shell of the second block. By processing the behavioral description of the block to generate the at least one other block. Generating a gate-level description of the   A method comprising:   17． The method of claim 16,   A synthetic shell merging the synthetic shells of the first and second blocks And the integrated composite shell includes the first and second composite shells. Input load and fanout for the block, this integrated first and second Output delay for block clock, integrated first and second blocks Output drive, clock for the integrated first and second blocks Setup / hold constraints on the input signal, and the integrated first and second Saving delay from input to output for passing signal of block 2 how to.   18. A method of creating a gate level description of a circuit block, comprising:   Processing the gate-level description and, according to a set of criteria, Deleting the elements of the gate level description, wherein the set of criteria comprises: , Input load and fan-out for the circuit block, Output delay with respect to clock, output drive of said circuit block, said circuit block Setup / hold constraints on the input signal to the clock of the clock, and Preserving the delay from input to output for the passing signal of the circuit block, ,   The gate-level description of the remaining elements is Memorizing in the memory,   A method comprising:   19. 20. The method according to claim 18, wherein the gate level of the circuit block is determined. The statement identifies the area needed for the circuit block and the processing steps. The top   The area required for the circuit block and the elements in the composite shell are Generate area difference data indicating the difference from the required area, and use the Including the step of including region difference data.   20. 19. The method of claim 18, wherein said processing comprises:   Load on each node in path from last storage element to output port And information indicating the clock and the incremental load on the asynchronous path. A method comprising the steps of:   21. 20. The method of claim 18, wherein the set of criteria is:   The combination path from the input port to the first storage element in the circuit block is maintained. To exist,   Save the combination path from the last storage element of the circuit block to the output port That   Saving a direct combination path from an input port to an output port of the circuit block And   Storing a clock distribution path in the circuit block;   A flow from an output port of the circuit block to a storage element in the circuit block Storing the feedback path with the storage element;   Feedback in the circuit block to a path composed of combinational logic To save the traffic route,   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic And treat   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly In some cases, including storing a storage element that produces an internal clock;   Preserving the asynchronous route,   A method comprising:   22. 20. The method of claim 18, wherein the circuit block comprises first and second Including a sub-block, wherein the processing step comprises: Processing a gate-level description to generate the first sub-block according to the set of criteria; Reading the elements of the gate level description of the Processing a gate-level description of the second sub-block according to the set of criteria And removing the remaining elements of the first and second sub-blocks. A gate-level description consisting of a combination of gate-level descriptions is processed to process the composite system. Generating a gel.   23. 19. The method of claim 18, wherein said processing comprises:   The input and output ports for the circuit block are recursively checked and If the signal on the port is not a clock, set, or clear signal, the port Inspecting the branch of   Mark each branch so that the cells on that branch are maintained. Determining whether the cell is a leaf;   If the cell is not a leaf, shoot each cell against the cell. Inspection until the leaf is reached on the cell, and the shoot on the cell is the output of another cell. Or if the port being inspected is an input, keep the other cell Mark to be held, otherwise, on the shoot to be loaded Marking the cell as restored;   If the signal on the port is a clock, set or clear signal, Inspect the branch of the port, then the leaf on each branch of said port Cells so that they are maintained until each shot on the Working steps,   Add a dummy cell to the resulting gate level description and add Equilibrating the area of   All clock, clear and set nets in the gate level description Load on all cells and on all cells marked for load recovery. Storing the data to be recovered;   A method comprising:   24. Includes memory for storing a synthesized shell of gate-level descriptions of circuit blocks. Device, the device comprising:   Processing the gate-level description and, according to a set of criteria, Deleting the elements of the gate level description, wherein the set of criteria comprises: , Input load and fan-out for the circuit block, Output delay with respect to clock, output drive of said circuit block, said circuit block K Setup / hold constraint on the input signal for the clock of Saving the input-to-output delay for the passing signal of the road block;   The gate-level description of the remaining elements is Memorizing in the memory,   An apparatus characterized by being created by a method comprising:   25. 25. The device according to claim 24, wherein the gate level of the circuit block is determined. The statement identifies the area needed for the circuit block and the processing steps. The top   The area required for the circuit block and the elements in the composite shell are Generate area difference data indicating the difference from the required area, and use the A step of including the region difference data.   26. 25. The apparatus according to claim 24, wherein the processing comprises:   Each in the path from the last storage element to the output port of the circuit block Load on the node and clock on the circuit block and on the asynchronous net Storing information indicative of an incremental load. Equipment to do.   27. 25. The apparatus of claim 24, wherein the set of criteria comprises:   The combination path from the input port to the first storage element in the circuit block is maintained. To exist,   Save the combination path from the last storage element of the circuit block to the output port That   Saving a direct combination path from an input port to an output port of the circuit block And   Storing a clock distribution path in the circuit block;   A flow from an output port of the circuit block to a storage element in the circuit block Storing the feedback path with the storage element;   Feedback in the circuit block to a path composed of combinational logic To save the traffic route,   If the write signal to the asynchronous RAM is traced to the input port, Save the asynchronous RAM, otherwise combine it with combinational logic And treat   Any storage element that is clocked by the internal clock so generated Connected to input port or output port via combinational logic or directly In some cases, including storing a storage element that produces an internal clock;   Preserving the asynchronous route,   An apparatus comprising:   28. 25. The apparatus of claim 24, wherein said circuit block of said composite shell is Synthesizing a gate-level description of an integrated circuit module including a subject and other circuits, Processing resources synthesized from a shell and the behavioral description of the other circuit in the module A device comprising a source.