JP2014038471A - Layout model creation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To create a layout model capable of achieving a layout prototype under the consideration of the internal layout and wiring property of a model while maintaining secrecy in the case of modeling a module constituting an LSI.SOLUTION: The layout model creation device includes: a storage section for storing the net list of a selected object module, timing constraint data and the library of cells; a delay model creation section for modeling a delay between each port of the object module and an I/F register corresponding to the port by a buffer for the delay on the basis of the net list and the timing constraint data to replace the external I/F section of the net list; and a wiring model creation section for creating a wiring model by replacing the cells between the I/F registers in the net list of the object module with specific cells of the same pin constitution on the basis of the list of the cells obtained from the library to change inter-I/F register wiring in the net list.

Description

  The present invention relates to an apparatus for creating a layout model relating to layout prototyping of a semiconductor integrated circuit.

  When prototyping a layout at the design stage of a semiconductor integrated circuit at the customer side, it is necessary to create a layout model for each module for modules that are classified as confidential.

  A gate simulation model and design data in which delay information is added to an RTL-based pre-layout logic simulation model for verifying the logic operation of a semiconductor integrated circuit, and circuit information is deleted based on a netlist Such as converting the names of the functional blocks in the block, changing the cell names using a table indicating the correspondence between the cells of the first library and the cells of the second library, and replacing them with equivalent cells Therefore, it is proposed to keep circuit information know-how secret.

JP 2006-127449 A JP 2007-26178 A JP-A-11-353356

  The above-described gate simulation model is a technique in which only delay information (timing) and shape information of a black boxed module are used. Customers can use this model to confirm the validity of the floor plan (ie, the validity of macro and pin placement and wiring) at the early stage of LSI design, and to predict and estimate the timing area. Therefore, the target design is laid out and evaluated. This is called prototyping.

  In recent years, LSI miniaturization has progressed, and when prototyping is performed using only delay information and module shape information, gate placement and wiring congestion in the model cannot be considered, and the actual layout The divergence is large and rework occurs.

  Further, there is a problem that the module function remains only by changing the name of the functional block and the cell, so that the secrecy is low, and the accuracy is low as a delay model only by replacing the equivalent cell.

  Therefore, an object of the present invention is to create a layout model that enables a layout prototype that takes into account the placement and wiring properties inside the model while maintaining secrecy when modeling the modules that make up the LSI. is there.

  According to one aspect of the present embodiment, the layout model creation device includes a storage unit that stores a net list of selected target modules, timing constraint data, and a library of cells, the net list, and the timing constraint data. Based on the above, the delay between each port of the target module and the I / F register corresponding to the port is modeled by the buffer corresponding to the delay, and the external I / F portion of the netlist is replaced. Based on a delay model creation unit and a list of cells obtained from the library, a wiring model is created by replacing cells between the I / F registers in the net list of the target module with specific cells having the same pin configuration. And a wiring model creation unit for changing between the I / F registers of the netlist.

  Further, as means for solving the above problems, a layout model creation method, a program for causing a computer to function as the layout model creation apparatus, and a recording medium on which the program is recorded can be used.

  With the disclosed technology, it is possible to create a layout model in which highly confidential modules constituting an LSI are modeled so that arrangement and wiring properties can be considered.

It is a figure for demonstrating the model creation method which concerns on a present Example. It is a figure which shows the hardware constitutions of a layout model production apparatus. It is a figure for demonstrating the whole structure which concerns on a layout model production apparatus. It is a figure which shows the function structural example of a model preparation part. It is a figure for demonstrating reproduction of the delay and wiring property in a present Example. It is a figure for demonstrating an example of a delay model creation process. It is a figure for demonstrating an example of a wiring model creation process. It is a figure which shows the example of replacement to a specific combination cell. It is a figure for demonstrating the creation example of the delay constraint data between registers by the wiring model preparation part. It is a figure which shows an example which divides a delay constraint. It is a figure for demonstrating an example of area adjustment. It is a figure for demonstrating the example of a change method of a driving capability. It is a flowchart figure (the 1) for demonstrating a model creation process. FIG. 12 is a flowchart (part 2) for describing model creation processing; FIG. 10 is a flowchart (part 3) for describing model creation processing; It is a figure which shows the example of a change of a net list. It is a figure which shows an example of the delay constraint data between registers. It is a figure which shows an example of attracting arrangement | positioning restrictions data. It is a figure for demonstrating an example of related technology. It is a figure which shows an example of modeling by related technology. It is a figure which shows an example of modeling by a present Example. It is a figure for demonstrating the comparison with related technology and a present Example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining a model creation method according to the present embodiment. The model creation method according to the present embodiment will be described by taking as an example the module 2 to be modeled among a plurality of modules constituting the LSI shown in FIG.

  In the model creation method according to the present embodiment, the delays from the input port 3 and the output port 4 of the modeling target module 2 to the first stage register are reproduced by the buffers 5b and 7b. I / F registers 5r and 7r are inserted so as to correspond to each other.

  By arranging the I / F register 5r and the buffer 5b as the attracting arrangement 5, it is possible to prevent the arrangement from being separated by the layout and the delay of the buffer 5b from changing. Similarly, the I / F register 7r and the buffer 7b are set to the attracting arrangement 7, thereby preventing the arrangement from being separated by the layout and changing the delay of the buffer 7b.

  The register 6r in the inter-I / F register logic 6 corresponding to the logic part between the I / F register 5r and the I / F register 7r is replaced with a specific combination cell having the same number of pins. In order to increase confidentiality, the clock path or reset path to the register 6r is disconnected and reconnected to the input / output of the combination cell that replaces the data input / output, the enable signal, and the like of the register 6r. By this processing, it is possible to leave the wiring property.

  By adjusting the driving capability of the inter-I / F register logic 6 replaced with the combination cell, it is adjusted to the area of the original net.

  By modeling the target module 2 by the model creation method described above, it is possible to perform timing analysis that can consider highly accurate placement and wiring while maintaining secrecy. Accordingly, by reducing rework, it is possible to reduce the number of times of providing data files related to LSI design to customers.

  A layout model creation apparatus having such a model creation method has a hardware configuration as shown in FIG. FIG. 2 is a diagram illustrating a hardware configuration of the layout model creation apparatus. In FIG. 2, the layout model creation device 100 is a device controlled by a computer and includes a CPU (Central Processing Unit) 11, a main storage device 12, an auxiliary storage device 13, an input device 14, and a display device 15. And an output device 16, a communication I / F (interface) 17, and a drive device 18, which are connected to the bus B.

  The CPU 11 controls the layout model creation device 100 in accordance with a program stored in the main storage device 12. The main storage device 12 uses a RAM (Random Access Memory) or the like, and stores a program executed by the CPU 11, data necessary for processing by the CPU 11, data obtained by processing by the CPU 11, and the like. A part of the main storage device 12 is allocated as a work area used for processing by the CPU 11.

  The auxiliary storage device 13 uses a hard disk drive and stores data such as programs for executing various processes. A part of the program stored in the auxiliary storage device 13 is loaded into the main storage device 12 and executed by the CPU 11, whereby various processes are realized. The storage unit 130 includes the main storage device 12 and / or the auxiliary storage device 13.

  The input device 14 includes a mouse, a keyboard, and the like, and is used for a user to input various information necessary for processing by the layout model creation device. The display device 15 displays various information required under the control of the CPU 11. The output device 16 has a printer or the like and is used for outputting various types of information in accordance with instructions from the user. The communication I / F 17 is a device that is connected to, for example, the Internet, a LAN (Local Area Network), etc., and controls communication with an external device.

  A program that realizes processing performed by the layout model creation apparatus 100 is provided to the layout model creation apparatus 100 by a storage medium 19 such as a CD-ROM (Compact Disc Read-Only Memory). That is, when the storage medium 19 storing the program is set in the drive device 18, the drive device 18 reads the program from the storage medium 19, and the read program is installed in the auxiliary storage device 13 via the bus B. Is done. When the program is activated, the CPU 11 starts its processing according to the program installed in the auxiliary storage device 13. The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.

  FIG. 3 is a diagram for explaining the overall configuration of the layout model creation apparatus 100. In FIG. 3, a layout model creation apparatus 100 is an apparatus introduced to a developer who develops functional blocks mounted on an LSI, and a customer system 200 is concealed by being developed and modeled by the developer. This corresponds to a development environment including a computer device for performing layout prototyping 400 on the customer side based on design data relating to LSI design including at least one functional block.

  The layout model creation apparatus 100 includes a model creation unit 200 as a processing unit according to the present embodiment. The layout model creation apparatus 100 also stores in the storage unit 130 a pre-change netlist 31 before performing model creation processing, an SDC (Synopsys Design Constraints) 32 including timing constraint data, a library of cells 33 constituting an LSI, a model. Data such as the post-change netlist 34 after the creation processing, the inter-register delay constraint data 35, and the location constraint data 36 are stored.

  The model creation unit 200 is a processing unit that performs modeling so that arrangement and wiring properties can be taken into consideration even for confidential modules among a plurality of modules (a plurality of functional blocks) constituting the designed LSI. . The configuration of the model creation unit 200 will be described with reference to FIG.

  The pre-change netlist 31 shows connection information between cells before the model creation processing by the model creation unit 200 is performed. The SDC 32 is a data file that defines timing constraints. The library 33 is a library that includes data such as logic functions, electrical characteristics, and driving capability for each cell.

  The post-change netlist 34 is a netlist in which the pre-change netlist 31 is changed by the model creation process by the model creation unit 200.

  The inter-register delay constraint data 35 indicates the delay constraint in the inter-I / F register logic 6 (FIG. 1), and is data added to the SDC 32 in the customer system 300.

  The attraction arrangement constraint data 36 is data defining the attraction arrangement of the buffers and registers of the I / F delay model so that the delay is not changed by the arrangement change by layout pro and typing on the customer side. The placement change constraint data 36 defines a placement change constraint.

  The customer system 300 uses the post-change netlist 34 obtained after the model creation process in the layout model creation apparatus 100, the SDC 32, the library 33, the inter-register delay constraint data 35, and the attraction placement constraint data 36. Layout prototyping 400 is performed.

  In the customer system 300, the inter-register support constraint data 35 is added to the SDC 32, and the attracting arrangement constraint data 36 is added to the floor plan setting value 53. The post-change netlist 34 is used as provided by the developer.

  FIG. 4 is a diagram illustrating a functional configuration example of the model creation unit. In FIG. 4, the model creation unit 200 includes a delay model creation unit 21, a wiring model creation unit 22, an area adjustment unit 23, and a concealment processing unit 24.

  The delay model creation unit 21 refers to the pre-change netlist 31 and the SDC 32, reproduces the delay from the input / output port of the modeled module to the first stage I / F register with a buffer, and has a one-to-one relationship with the port. A processing unit for inserting a register.

  The wiring model creation unit 22 is a processing unit that refers to the library 33 and replaces all logic between the I / F registers with a specific combination cell having the same number of pins. In order to increase confidentiality, the wiring model creation unit 22 disconnects the clock path and the reset path to the register and reconnects to the input / output of the combination cell that replaces the data input / output of the register and the enable signal.

  The area adjustment unit 23 refers to the library 33 and adjusts the logic driving capability between the I / F registers created by the wiring model creation unit 22 so as to correspond to the original number of gates. Processing section.

  The concealment processing unit 24 is a processing unit that converts the names of modules, instances, and nets into meaningless character strings.

  FIG. 5 is a diagram for explaining the reproduction of delay and wiring properties in the present embodiment. In FIG. 5, the highest module 1 corresponds to the entire LSI or one of functional blocks constituting the LSI. The target module 2 is a module selected as a highly confidential module among a plurality of modules included in the highest module 1.

  In this module example, the delay model creation unit 21 in the model creation unit 200 reproduces the delay from the input port to the first stage I / F register 5r with four buffers 5b, and from the output port to the first stage I / F register 7r. The delay until is reproduced by two buffers 7b.

  The delay model creation unit 21 inserts a register in a one-to-one relationship with each port, and if there is a register, the delay model creation unit 21 clones the register. The original register clock is used. Further, the I / F register 5r and the buffer 5b are attracted and arranged. Similarly, the I / F register 7r and the buffer 7b are attracted and arranged. By this processing, the I / F delay is reproduced. The attracting arrangement constraint data 36 is generated by the delay model creation unit 21 and stored in the storage unit 130.

  The logic between the I / F register 5r and the I / F register 7rt is replaced with another combination cell having the same pin configuration by the wiring model creation unit 22 in the model creation unit 200. Further, the wiring model creation unit 22 deletes the clock path and the reset path of the existing register and replaces only the data path with the combination cell. Then, the wiring model creation unit 22 gives a delay constraint for the actual period to the path between the I / F register 5r and the I / F register 7r. By considering the delay, it is possible to prevent excessive arrangement and wiring deterioration, and to hide the function while reproducing the wiring property. The wiring model creation unit 22 generates the inter-register delay constraint data 35 and stores it in the storage unit 130.

  The cells in the target module 2 that are modeled by the delay model creation unit 21 and the wiring model creation unit 22 are set to have no change (don't touch) attributes in the layout except for the size change.

  Furthermore, the confidentiality can be enhanced by bringing the original size into account by changing the size by the area adjusting unit 23 and converting the name into a meaningless character string by the confidential processing unit 24.

  An example of the delay model creation process by the delay model creation unit 21 will be described in detail with reference to FIG. FIG. 6 is a diagram for explaining an example of the delay model creation process. The target module 2-1 illustrated in FIG. 6 shows a case where three input / output ports of ports A, B, and C and a clock CLK terminal are included.

  In the target module 2-1, on the path from the input port A to the output port B, the input port A, combinational logic 51, register 52, combinational logic 53, register 54, combinational logic 55, register 56, combinational logic 57, There are an I / F register 58, combinational logic 59, and output port B.

  On the path from input port A to output port C, there are input port A, combinational logic 51, register 52, combinational logic 53, register 54, combinational logic 60, register 61, combinational logic 62, and output port C. To do.

  The combination model 51 is replaced with two buffers 51b, the combination logic 59 is replaced with three buffers 59b, and the combination logic 62 is replaced with four buffers 62b by the wiring model creation unit 22 in the model creation unit 200. . The combinational logic 51, the combinational logic 59, and the combinational logic 62 are each replaced with a buffer for the maximum delay.

  Next, an example of the wiring model creation processing by the wiring model creation unit 22 will be described in detail with reference to FIG. FIG. 7 is a diagram for explaining an example of the wiring model creation process. In FIG. 7, the wiring model creation unit 22 deletes the clock path and reset path of the internal register, and replaces only the data path with the combination cell. The paths 54d, 56d, and 60d that are clock paths or reset paths are deleted.

  Further, the registers 54, 56 between the I / F register 52 and the I / F register 58 or 61 are replaced by the combination cells 54n, 56n, and 60n for internal register replacement. Further, the existing cells 55 and 60 are replaced with specific combination cells 55s and 60s having the same pin configuration.

  An example of replacing the existing cell 55 with a specific combination cell 55s will be described with reference to FIG. FIG. 8 is a diagram illustrating an example of replacement with a specific combination cell. In FIG. 8, an existing cell 55 inputs an AND circuit that outputs an AND operation result for three inputs, an AND circuit that outputs an AND operation result for four inputs, and inputs these two outputs. In the case of a combination cell with an OR circuit that outputs an OR operation result, a NAND circuit that outputs a NAND operation result for three inputs, a NAND circuit that outputs a NAND operation result for four inputs, and these It is replaced with a specific combination cell 55s by a NAND circuit that inputs two outputs and outputs a NAND operation result. Thus, the specific combination cell 55 s that replaces the existing cell 55 is a cell having the same pin configuration as that of the existing cell 55.

  FIG. 9 is a diagram for explaining an example of creation of delay constraint data between registers by the wiring model creation unit. 9, I / F registers 52, 58, and 61 in FIG. 7 are described as reg1, reg2, and reg3.

  The wiring model creation unit 22 calculates a period T1 from reg1 to the combination cell 54n, a period T2 from the combination cell 54n to the combination cell 56n, and a period T3 from the combination cell 56n to reg2, respectively, from reg1 to reg2. Calculate the maximum delay constraint between registers.

  Further, the period T4 from the combination cell 54n to the combination cell 56n and the period T5 from the combination cell 56n to reg2 are calculated, respectively, and the maximum delay constraint between registers from reg1 to reg3 is calculated.

reg1-> reg2: maximum delay constraint = T1 + T2 + T3
reg1-> reg3: maximum delay constraint = T1 + T4 + T5
If there is no delay constraint between registers, the layout tool determines that there is no problem even if the arrangement of cells is far away or the wiring is detoured. By providing the delay constraint, the layout tool can perform proper placement and wiring.

  Further, in addition to the above, the delay constraint may be delimited only when the timing margin between the registers is biased. FIG. 10 is a diagram illustrating an example of delimiting delay constraints. In FIG. 10, when the timing margin between reg1 and comb1 is large and the timing margin is small in other sections, if the maximum delay constraint between reg1 and reg2 is the sum of periods T1, T2, and T3, between reg1 and comb1 The margin may be used in other sections, and as a result, the arrangement may be changed.

  By inserting the comb1 buffer 63b on the output side of comb1, the delay constraint can be set as follows.

Between reg1 and comb1 buffer: T1
From comb1 buffer to reg2: T2 + T3
By inserting a buffer and delimiting the delay constraint, it is possible to suppress a change in arrangement due to a margin between reg1 and comb1 being used in another section.

  Next, the area adjustment processing by the area adjustment unit 23 will be described with reference to FIG. FIG. 11 is a diagram for explaining an example of area adjustment. In FIG. 11, when the area of the model of the target module 2-1 is smaller than the original area, the specific combination cell 60 s is changed to a cell having a high driving capability. In this example, the driving capability “1” is changed to the driving capability “8”.

  An example of a method for changing the driving capability will be described with reference to FIG. In FIG. 12, by referring to the library 33, a list 33-2 in which the cell name including the size of the driving capability is associated with the size of the cell area is created. The list 33-2 corresponds to a list of available technology cells.

In the library 33,
cell (NANDx2)
...
area 10;
...
cell (NANDx4)
...
area 20;
Existed,
NANDx2,10
NANDx4,20
A list containing is created. The cell name may be in a format indicating the type and driving capability of the logic circuit.

If the netlist of the target module 2-1 is identified by NET (Model) and the total area in the NET (Model) is smaller than “100” with respect to the original area “110”, the NET (Model) of
NANDx2 XXX ()
Rewrite the cell name in the description part of `` NANDx4 '' with high driving ability obtained by referring to the list,
NANDx4 XXX ()
And

  13 to 15 are flowcharts for explaining the model creation process. In FIG. 13, the delay model creation unit 21 of the model creation unit 200 reads the pre-change netlist 31, the SDC 32, and the library 33, and then modularizes the pre-change netlist 31 because the function is highly confidential. A target module is extracted (step S11). The delay model creation unit 21 causes the developer to select a module to be modeled from among a plurality of modules constituting the LSI, and a netlist related to the target module selected by the developer is extracted.

  The delay model creation unit 21 calculates the number of gates in the netlist of the target module (step S12). The calculated number of gates is stored in the storage unit 130. The number of gates is referred to during area adjustment described later.

  Then, the delay model creation unit 21 calculates the maximum delay from each port to the register (step S13). The delay model creation unit 21 calculates the maximum delay from the input port 3 to the data in the I / F register 5r. Similarly, the delay model creation unit 21 calculates the maximum delay from the data in the I / F register 7r to the output port 7r.

  The number of buffer stages equivalent to the calculated maximum delay is calculated (step S14). Calculation is performed for each of the input port 5r and the output port 7r.

The number of buffer stages to be inserted = delay value ÷ delay buffer for one stage of buffer may be selected using cell data based on the pre-change netlist 31, for example, the list 33-2. The delay of one stage of the selected buffer can be acquired by referring to the library 33.

  The delay model creation unit 21 creates an I / F circuit (step S15). In the I / F circuit, buffers 5b corresponding to the number of stages calculated in step S14 are inserted between the input port 3 and the I / F register 5r, and the number of stages calculated in step S14 between the output port 4 and the I / F register 7r. It is created by inserting the minute buffer 7b.

  The delay model creation unit 21 creates attracting arrangement constraint data 36 for the created I / F circuit (step S16). The created attracting arrangement constraint data 36 is stored in the storage unit 130.

  The delay model creation unit 21 replaces the I / F circuit portion in the pre-change netlist 31 with the I / F circuit created in step S15 (step S17). Thereafter, the delay model creation unit 21 determines whether all ports have been extracted for the target module selected by the developer (step S18). If all ports have not been extracted, the delay model creation unit 21 returns to step S13 and repeats the same processing as described above. On the other hand, when all the ports have been extracted, the processing by the delay model creation unit 21 ends, and the model creation unit 200 proceeds to step S19 in FIG. 14 in order to perform the processing by the wiring model creation unit 22.

  In FIG. 14, the wiring model creation unit 22 refers to the SDC 32 and calculates the maximum value extension between the I / F registers 5r and 7r (step S19). Between the F registers 5r and 7r, the maximum value spread is calculated and summed up with each internal register 6r as a separator.

Maximum delay between I / F registers = T1 + T2 + T3
A value obtained by adding the periods between the registers is defined as a delay constraint. Inter-register delay constraint data 35 including the calculated maximum value extension value is stored in the storage unit 130.

  The wiring model creation unit 22 disconnects a clock path and a reset path of registers existing between the I / F registers (step S20). Then, the wiring model creation unit 22 refers to the list 33-2 and replaces the register existing between the I / F registers with a specific combination cell (step S21). A register in which the clock path and the reset path are disconnected is replaced with a NAND cell.

  Further, the wiring model creation unit 22 replaces the combination cell between the I / F registers with a specific combination cell (step S22). Here, in order to finish the processing in the wiring model creation unit 22 and perform the processing by the area adjustment unit 23, the model creation unit 200 proceeds to step S23 in FIG.

  In FIG. 15, the area adjustment unit 23 adjusts the driving ability of the combination cell (step S23). If the number of gates of the target module calculated by the delay module creation unit 21 in step S12 is smaller than the original number of gates, the cell is changed to a cell having a high driving capability of the same combination cell with reference to the list 33-2. In this way, you can meet the original area. For example, when changing a NAND cell having a driving capability of 1 time, the NAND cell having a driving capability of 4 times is changed with reference to the list 33-2.

  Then, the area adjustment unit 23 determines whether or not the number of original gates is equal to the number of model gates (step S24). When the number of original gates and the number of gates of the model are not equal, the area adjustment unit 23 returns to step S23 and adjusts the area merging again.

  On the other hand, when the number of original gates is equal to the number of gates of the model, the process in the area adjustment unit 23 is terminated and the process in the concealment processing unit 24 is performed. The concealment processing unit 24 converts names such as module names, instance names, and net names in the net list of the target module into meaningless character strings (step S25).

  Through the processing described above, the net list of the entire LSI including the net list in which the target module has been changed is stored in the storage unit 130 as the changed net list 34.

  The design data 39 provided to the customer includes a post-change netlist 34, inter-register delay constraint data 35, and attracting location constraint data 36.

  FIG. 16 is a diagram illustrating an example of changing the netlist. In FIG. 16, in the pre-change netlist 31, in the description 31a, the NAND cell is connected to the input port IN1, the NOR cell is connected to the input port IN2, the NAND cell is connected to the NOR cell, and the FF cell. It is shown.

  In the post-change netlist 34, the delay from the input port to the I / F register is replaced with a buffer. In this example, the NAND cell “inst1” in the description 31a of the pre-change netlist 31 is replaced with four BUF cells “buf1_reg1_1”, “buf1_reg1_2”, “buf1_reg1_3”, and “buf1_reg1_4” connected in series ( Description 31b). The BUF cell “buf1_reg1_4” at the final stage is connected to the data of the FF cell “reg1” by wire_buf1_4.

  Further, the NOR cell “inst2” is replaced with three BUF cells “buf2_reg1_1”, “buf2_reg1_2”, and “buf2_reg1_3” connected in series (description 31c). The BUF cell “buf2_reg1_3” at the final stage is connected to the data of the FF cell “reg1” by wire_buf2_3.

FIG. 17 is a diagram illustrating an example of inter-register delay constraint data. In FIG. 17, the restriction on the maximum delay of the path I from reg1 to reg2 and the restriction on the maximum delay of the path II from reg1 to reg3 are as follows:
I: set_max_delay [expre T1 + T2 + T3] -from reg1 / CLK -to reg2 / DATA
II: set_max_delay [expre T1 + T2 + T3] -from reg1 / CLK -to reg3 / DATA
It is described as follows.

  FIG. 18 is a diagram illustrating an example of attracting arrangement constraint data. In FIG. 18, the attraction placement constraint data 36 is associated with one or more target buffers to be attracted to the register name.

  In this example, buffers “buf_reg1_1” and “buf_reg1_2” are attracted to the register name “reg1”. Buffers “buf_reg2_1”, “buf_reg2_2”, and “buf_reg2_3” are assigned to the register name “reg2”. Buffers “buf_reg3_1”, “buf_reg3_2”, “buf_reg3_3”, and “buf_reg3_4” are assigned to the register name “reg3”.

  Hereinafter, a comparison between related technology and conventional technology will be described. ETM modeled mainly by the I / F timing library of the target module and its module shape as a related technology for modeling the target module of confidential handling included in the net list provided to the customer who performs layout prototyping (Extracted Timing Model), a netlist obtained by extracting only the I / F logic of the target model, and a model ILM (Interface Logic Model) of the module shape.

  An example of such related technology is shown in FIG. In FIG. 19, the vendor system 101 implemented by the developer refers to the modeling target module selected by the developer by referring to the net list 71, the SDC 72, and the library 73. A target module cutout unit 78 that cuts out timing information from each of the netlist 71 and the SDC 72, an I / F timing extraction unit 7a that extracts I / F timing from the cut out information, and a shape extraction unit 7b are used as processing units. Have.

  The target module cutout unit 78 cuts out the target net 1 and SDC1, the target net 2 and SDC2, and so on for each of the target modules 1, 2,. Using the target net 1 and the SDC 1, the timing information 1 is output by the I / F timing extraction unit 7a, and the shape information 1 is output by the shape extraction unit 7b.

  The processing by the I / F timing extraction unit 7a and the shape extraction unit 7b is executed for each of the target modules 1, 2,. And the timing information 1 and the shape information 1 are output for every object module 1, 2,.

  The customer system 301 that performs layout prototyping 401 is provided with the top net 79 after being cut out, timing information 1, 2,..., And shape information 1, 2,.

  In the related art described above, as shown in FIG. 20, when the LSI 8 is modeled with a plurality of highly confidential target modules 8c, a black box is formed with a plurality of rectangular models 8m including the target portion. In the black box, the layout prototyping 401 cannot take into consideration the arrangement and wiring properties.

  However, in the layout model creation apparatus 100 according to the above-described embodiment, as illustrated in FIG. 21, even if the target module 8c is modeled, the target module 8c is not formed into a black box and has a layout and wiring property. It can be concealed in consideration.

  FIG. 22 is a diagram for explaining a comparison between related technology and the present embodiment. FIG. 22 shows a comparison table between ETM and ILM of the related art and this example. In FIG. 22, with respect to each comparison item of the model shape, I / F timing, confidentiality, wiring congestion degree, and arrangement congestion degree, the shape is expressed as “rectangle” in the ETM, and the I / F timing is modeled. However, it can be considered, and confidentiality is also protected. On the other hand, the wiring congestion degree and the placement congestion degree cannot be considered after modeling.

  Also in the ILM, the shape is expressed by “rectangle”, and the I / F timing after modeling can be considered, but the secrecy is not sufficient. Also, the wiring congestion level and the placement congestion level cannot be considered after modeling.

  In the case of a rectangular model such as ETM, ILM, etc., the layout and wiring property inside the model cannot be considered, and a correct layout prototype cannot be made in the customer system 301. Also, since the bus portion is arranged on the entire chip, it is difficult to make a rectangular model. Although division for rectangular modeling is possible, a processing load is imposed on the division method, the connection between the divided modules, and the like.

  However, in this embodiment, the shape is not limited (Free) and is not changed from the original. Also, the I / F timing can be taken into consideration, the confidentiality is protected, and the operation of the function is not known outside. Furthermore, it is possible to consider both the wiring congestion degree and the arrangement congestion degree.

  As described above, according to the present embodiment, while maintaining the arrangement and wiring properties from the original net list, a highly concealed net list is provided in which the contents of the function are not known even if provided to the customer. be able to. In addition, it is possible to model a module in which cells such as buses are spread over the entire chip.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The following additional notes are further disclosed with respect to the embodiment including the above examples.
(Appendix 1)
A storage unit for storing a netlist of selected target modules, timing constraint data, and a library of cells;
Based on the netlist and the timing constraint data, a delay between each port of the target module and the I / F register corresponding to the port is modeled by a buffer corresponding to the delay, and the netlist A delay model creation unit that replaces the external I / F unit;
Based on a list of cells obtained from the library, a wiring model is created by replacing cells between the I / F registers in the net list of the target module with specific cells having the same pin configuration, and the net list A wiring model creation unit for changing between the I / F registers
A layout model creation device.
(Appendix 2)
The delay model creation unit
The maximum value extension for each port and the clock of the port FF are extracted, the number of buffers corresponding to the delay is calculated, and the above-mentioned I / F register and the buffer corresponding to the maximum value extension are one-to-one for the port. The layout model creation according to appendix 1, wherein an external I / F unit is modeled, and attractive allocation constraint data is generated and stored in a storage unit so that the buffer and the I / F register are attractively allocated. apparatus.
(Appendix 3)
The wiring model creation unit
The supplementary note 1 or 2, wherein a clock path and a reset path of an existing register are deleted from the net list, and the existing register in which the data path remains is replaced with a combination cell by referring to the list. Layout model creation device.
(Appendix 4)
The wiring model creation unit
The layout model creating apparatus according to claim 3, wherein an existing cell in the net list is replaced with a specific cell having the same pin configuration with reference to the list.
(Appendix 5)
The wiring model creation unit
The layout model creation device according to appendix 3 or 4, wherein a delay between combination cells replaced with the I / F register and the existing register is calculated to create inter-register delay constraint data and store it in a storage unit .
(Appendix 6)
The delay model creation unit calculates the number of gates of the target module before modeling based on the netlist before modeling,
An area adjustment unit that adjusts an area by changing the driving capability of the combined cell after modeling so that the number of gates of the target module after modeling becomes equal to the calculated number of gates. The layout model creation device according to any one of appendices 1 to 5.
(Appendix 7)
The layout according to claim 6, further comprising a concealment processing unit that converts at least a module name, an instance name, and a net name in the net list after modeling the target module into a meaningless character string. Model creation device.
(Appendix 8)
A layout model creation method executed by a computer,
Based on the net list of the selected target module stored in the storage unit and the timing constraint data, the delay between each port of the target module and the I / F register corresponding to the port is set to the delay amount. Modeling with a buffer, replacing the external I / F part of the netlist,
Based on the list of cells obtained from the library stored in the storage unit, a wiring model is created by replacing the cells between the I / F registers in the net list of the target module with specific cells having the same pin configuration Then, the layout model creation method is characterized by changing between the I / F registers of the netlist.
(Appendix 9)
Based on the net list of the selected target module stored in the storage unit and the timing constraint data, the delay between each port of the target module and the I / F register corresponding to the port is set to the delay amount. Modeling with a buffer, replacing the external I / F part of the netlist,
Based on the list of cells obtained from the library stored in the storage unit, a wiring model is created by replacing the cells between the I / F registers in the net list of the target module with specific cells having the same pin configuration Then, a program for causing a computer to execute a process of changing between the I / F registers of the netlist.

2 Target module 3 Input port 4 Output port 5, 7 Attracting arrangement 5r, 7r I / F register 6 I / F register logic 11 CPU
12 Main storage device 13 Auxiliary storage device 14 Input device 15 Display device 16 Output device 17 Communication I / F
18 drive 19 storage medium 31 netlist before change 32 SDC
33 Library 34 Netlist after change 35 Inter-register delay constraint data 36 Attraction placement constraint data 53 Floor plan setting value 100 Layout model creation device 200 Model creation unit 300 Customer system 400 Layout prototype

Claims (5)

A storage unit for storing a netlist of selected target modules, timing constraint data, and a library of cells;
Based on the netlist and the timing constraint data, a delay between each port of the target module and the I / F register corresponding to the port is modeled by a buffer corresponding to the delay, and the netlist A delay model creation unit that replaces the external I / F unit;
Based on a list of cells obtained from the library, a wiring model is created by replacing cells between the I / F registers in the net list of the target module with specific cells having the same pin configuration, and the net list A wiring model creation unit for changing between the I / F registers
A layout model creation device. The delay model creation unit
The maximum value extension for each port and the clock of the port FF are extracted, the number of buffers corresponding to the delay is calculated, and the above-mentioned I / F register and the buffer corresponding to the maximum value extension are one-to-one for the port. 2. The layout model according to claim 1, wherein an external I / F unit is modeled, and attraction placement constraint data is created so that the buffer and the I / F register are attracted and arranged and stored in the storage unit. Creation device. The wiring model creation unit
3. A clock path and a reset path of an existing register are deleted from the netlist, and the existing register in which a data path remains is replaced with a combination cell by referring to the list. The described layout model creation device. The wiring model creation unit
4. The layout model creating apparatus according to claim 3, wherein an existing cell in the net list is replaced with a specific cell having the same pin configuration with reference to the list. The wiring model creation unit
The layout model creation according to claim 3 or 4, wherein a delay between combination cells replaced with the I / F register and the existing register is calculated to create inter-register delay constraint data and store it in a storage unit. apparatus.