JP2009237904A - Method for creating design data for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure the drive of the stable performance of hard macro on an LSI chip. <P>SOLUTION: This method for creating design data of a semiconductor integrated circuit includes steps for: creating a circuit block library in which the shape information, terminal position information and timing information of a circuit block are described; creating a netlist in which the connection information of a circuit block and a module circuit having a unit cell connected to the circuit block is described; creating layout data of the module circuit in which a circuit block arrangement region in which the circuit block is arranged and a unit cell arrangement region in which the unit cell is arranged are arranged in a prescribed state by using a unit cell library in which the shape information, terminal position information and timing information of the unit cell are described, the circuit block library and the netlist. The timing information of the circuit block when the circuit block arrangement region and the unit cell arrangement region are arranged in prescribed states is described in the circuit block library. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for creating design data of a semiconductor integrated circuit used for designing by a computer.

When designing a large scale integration (LSI, large scale integrated circuit) chip using a hard macro circuit containing confidential information (hereinafter also referred to as a hard macro), the hard macro designer discloses the circuit structure of the hard macro. Therefore, it is necessary to provide hard macro design data to the LSI chip designer. As hard macro design data, LSI chip designers are provided with layout data including coordinate information of hard macro frame size and terminal position, and a timing library including hard macro timing standards (also referred to as timing conditions). Since the arrangement of cells connected to the external terminals of the hard macro differs depending on the design status of the LSI chip, the timing standards at the interface between the hard macro and the LSI chip also differ. In general, a hard macro timing library is sufficiently verified within the scope of a hard macro designer.
Japanese Patent Laid-Open No. 11-307728 JP 2004-15032 A

  At the stage of designing a general-purpose hard macro, it is difficult for the hard macro designer to determine how the hard macro and the cells connected to the hard macro are arranged and routed on the LSI chip. . Therefore, a hard macro designer creates a hard macro timing library by assuming a large number of situations in which hard macros are arranged and wired on an LSI chip, and provides them to the LSI chip designer. However, if the placement and routing outside the range assumed by the hard macro designer is performed in the LSI chip design, the timing standard for the placement and routing is not fully verified, and there is a possibility that an operation failure may occur. An object of the present invention is to provide a technique that allows a hard macro to be driven on an LSI chip with stable performance.

  The present invention employs the following means in order to solve the above problems. That is, the present invention is a method for creating design data of a semiconductor integrated circuit used for design by a computer, in which the computer describes circuit block shape information, terminal position information, and timing information having predetermined functions. Creating a block library; creating a netlist in which connection information of module circuits having unit cells connected to the circuit blocks and the circuit blocks is described; shape information of the unit cells; terminal position information; Using a unit cell library in which timing information is described, the circuit block library, and the netlist, a circuit block arrangement area in which the circuit block is arranged and a unit cell arrangement area in which the unit cell is arranged are in a predetermined state. The moji provided in Generating layout data of a module circuit, and the circuit block library includes timing information of the circuit block when the circuit block arrangement area and the unit cell arrangement area are provided in a predetermined state. Is described.

In the layout data of the module circuit created by this creation method, a circuit block placement area and a unit cell placement area are provided in a predetermined state. The circuit block library created by this creation method describes circuit block timing information when the circuit block placement area and the unit cell placement area are provided in a predetermined state. Therefore, when the LSI chip is designed using the layout data of the module circuit, it is possible to ensure driving with stable performance of the hard macro on the LSI chip.

  In addition, the present invention may be a computer or other device, machine, or the like that executes any one of the processes described above. Furthermore, the present invention may be a program that causes a computer, other devices, machines, or the like to realize any of the above functions. Further, the present invention may be a program in which such a program is recorded on a computer-readable recording medium.

  According to the present invention, it is possible to drive a hard macro on an LSI chip with stable performance.

  A design support apparatus according to the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described below with reference to the drawings. The configuration of the following embodiment is an exemplification, and the present invention is not limited to the configuration of the embodiment.

<System overview>
The design support apparatus activates a layout creation system and creates hard macro layout data using a hard macro netlist and cell library. A hard macro is a functional block (also called a circuit block) that realizes a predetermined function. For example, a central processing unit (CPU), a random access memory (RAM), a read only memory
(ROM) etc. The hard macro is a core in which the arrangement of logic blocks and internal wiring are fixed in advance.

  The hard macro netlist is data in which cell connection information included in the hard macro is described. The cell library includes data in which cell size (size), shape, coordinate information of terminal positions, and the like are described, and data in which cell timing information is described. The hard macro layout data is data including cell placement information and wiring information between the cells. That is, the hard macro layout data is data describing the layout of the hard macro.

  The design support apparatus activates a library creation system and creates a hard macro library using the layout data of the hard macro and the cell library. The hard macro library includes a hard macro layout library and a hard macro timing library. The hard macro layout library has data such as hard macro size (size), shape, and coordinate information of terminal positions. The hard macro timing library includes a timing table in which hard macro timing standards (also referred to as timing information) are described. The timing standard is, for example, a setup time and hold time for an input signal, and a maximum delay time and a minimum delay time for an output signal.

  In the hard macro timing library, a timing standard considering external conditions of the hard macro is described. As an external condition of the hard macro, a first logic circuit connected to an external terminal of the hard macro is a buffer (also referred to as a signal relay circuit or a unit cell). Then, regarding the arrangement of the hard macro and the buffer, it is assumed that the buffer is arranged close to the external terminal of the hard macro. That is, the design support apparatus creates a hard macro timing library on the assumption that the buffer is arranged close to the external terminal of the hard macro.

  The state where the buffer is placed close to the external terminal of the hard macro means that the length of the wiring connecting the external terminal of the hard macro and the buffer is physically the minimum value so that the external terminal of the hard macro On the other hand, it means a state in which a buffer is arranged. By arranging the buffer close to the external terminal of the hard macro, the hard macro can be driven with stable performance. Therefore, it can be said that the state in which the buffer is arranged close to the external terminal of the hard macro is an arrangement state in which the hard macro can be driven with stable performance. In this specification, the state in which the buffer is arranged close to the external terminal of the hard macro is also referred to as a predetermined state or a predetermined arrangement state.

  Further, in the creation of the hard macro timing library described above, a margin is added to the timing standard. In this case, a margin is added to the timing standard in consideration of the arrangement position of the buffer connected to the external terminal of the hard macro. By adding a margin to the timing standard, it is possible to guarantee the operation of the hard macro when the LSI chip is designed using the hard macro timing library.

  The design support apparatus also activates the net list creation system and creates a net list of the wrapper module. The wrapper module is a module circuit including a hard macro and a buffer. The wrapper module netlist is data describing connection information between a hard macro and a buffer.

  In addition, the design support apparatus activates the layout data creation system, and uses the hard macro library, the wrapper module netlist, and the buffer library (also referred to as a signal relay circuit library or buffer cell library) to generate the layout data of the wrapper module. create. The buffer library (also referred to as a unit cell library) includes data in which buffer size, shape, terminal position coordinates, and the like are described, and data in which buffer timing information is described.

  The wrapper module layout data is data in which hard macros and buffer arrangement / wiring information connected to external terminals of the hard macros are described. The buffer in the wrapper module is arranged close to the external terminal of the hard macro.

  In addition, in the layout data of the wrapper module created using the hard macro library, the wrapper module netlist, and the buffer library, the internal structure (circuit structure) of the hard macro is in a black box state. That is, the layout data of the wrapper module created using the hard macro library, the wrapper module netlist, and the buffer library is layout data in which the internal structure of the hard macro is not described. This is because the internal structure of the hard macro is not described in the hard macro library used in creating the layout data of the wrapper module.

  Hereinafter, the layout data of the wrapper module created using the hard macro library, the wrapper module netlist, and the buffer library will be referred to as black box layout data. The design support apparatus describes a fixed layout attribute related to buffer layout in the layout data of the wrapper module created using the hard macro library, the wrapper module netlist, and the buffer library.

In addition, this design support apparatus starts the layout data creation system, and uses the hard macro layout data, the wrapper module netlist, and the buffer library,
Create wrapper module layout data. The hard macro layout data, the wrapper module netlist, the hard macro created using the buffer library, and the buffer layout data have the internal structure of the hard macro in a white box state.

  That is, the layout data of the hard macro, the wrapper module netlist, and the wrapper module layout data created using the buffer library are layout data in a state where the internal structure of the hard macro is described. This is because the internal structure of the hard macro is described in the hard macro layout data used in the creation of the wrapper module layout data.

  Hereinafter, the layout data of the hard macro, the netlist of the wrapper module, and the layout data of the wrapper module created using the buffer library are referred to as white box state layout data.

  In addition, the design support apparatus activates the timing verification system, and performs timing verification of the layout data in the black box state and the layout data in the white box state. The design support apparatus then activates the timing comparison system and compares the result of the timing verification of the layout data in the black box state with the result of the timing verification of the layout data in the white box state.

  When the result of timing verification of the black box state layout data is the desired result, the hard macro designer designs the LSI chip design for the black box state layout data, the wrapper module netlist, and the hard macro library data. To provide Here, since both the hard macro designer and the LSI chip designer prepare common data in the buffer library, the hard macro designer does not provide the buffer library data to the LSI chip designer.

  The black box layout data provided to the LSI chip designer does not describe the internal structure of the hard macro. For this reason, even when the layout data in the black box state is provided to the LSI chip designer, it is possible to prevent the LSI chip designer from knowing the internal structure of the hard macro.

  Then, the LSI chip designer designs the LSI chip using the black box layout data. The layout data in the black box state provided to the LSI chip designer is a state in which the buffer is arranged close to the external terminal of the hard macro. In addition, the hard macro library provided to the LSI chip designer includes a timing library in which a buffer is arranged close to an external terminal of the hard macro.

  Since the layout data in the black box state is given a fixed arrangement attribute relating to the arrangement of the buffer, the buffer is arranged close to the external terminal of the hard macro on the LSI chip. For example, even when LSI design is performed using automatic placement of layout tools, a buffer is always placed close to an external terminal of a hard macro on an LSI chip. Therefore, in designing an LSI chip using layout data in a black box state, it is possible to arrange and use hard macros with stable performance on the LSI chip.

The design data of the LSI chip is received by the user who uses this design support apparatus. Then, by creating an LSI chip based on this design data, the LSI chip can be manufactured without the LSI chip designer knowing the internal structure of the hard macro.

  FIG. 1 shows a hardware configuration of a computer 1 for realizing the design support apparatus. As shown in FIG. 1, the computer 1 includes a CPU 2 that controls the computer 1 by executing the computer program, and a memory 3 that stores the computer program executed by the CPU 2 and data processed by the CPU 2. As shown in the figure, the computer 1 includes an interface 4 for connecting the CPU 2 to various devices, a hard disk drive device 5, a portable medium drive device 6, an input device 7, and a display device 8.

The memory 3 stores a program executed by the CPU 2 and data processed by the CPU 2. The memory 3 is, for example, a volatile RAM or a nonvolatile ROM. The interface 4 may be either a serial interface such as Universal Serial Bus (USB) or a parallel interface such as Peripheral Component Interconnect (PCI). Although the CPU 2 and each device are connected by the interface 4, the CPU 2 and each device may be connected by different interfaces. A plurality of interfaces may be bridge-connected.

  The hard disk drive 5 stores a program loaded into the memory 3. Further, the hard disk drive device 5 stores data processed by the CPU 2. The portable medium drive device 6 is a drive device such as a Compact Disc (CD), Digital Versatile Disk (DVD), HD-DVD, or Blu-ray Disc. Further, the portable medium driving device 6 may be an input / output device for a card medium having a nonvolatile memory such as a flash memory. The medium driven by the portable medium driving device 6 stores, for example, a computer program installed in the hard disk driving device 5, input data, and the like. The input device 7 is, for example, a keyboard, a mouse, a pointing device, a wireless remote controller, or the like.

  The display device 8 displays data processed by the CPU 2 and data stored in the memory 3. The display device 8 is, for example, a liquid crystal display device, a plasma display panel, a Cathode Ray Tube (CRT), an electroluminescence panel, or the like.

  FIG. 2 is a functional block diagram of the present design support apparatus. The design support apparatus includes an operation unit 11, a storage unit 12, a layout unit 13, a verification unit 14, a library creation unit 15, a library verification unit 16, an external terminal extraction unit 17, a net list creation unit 18, a timing standard extraction unit 19, A timing standard calculation unit 20 and a timing standard comparison unit 21 are included. Each of these functional units can be realized by a computer including the CPU 2, the memory 3, and the like, each device, a program executed on the computer, and the like.

  The operation unit 11 is operated when receiving input from a user and inputting a predetermined command or necessary data.

  The storage unit 12 includes a netlist database (hereinafter referred to as netlist DB) 30, a library database (hereinafter referred to as library DB) 31, and a layout database (hereinafter referred to as layout DB) 32.

  The netlist DB 30 stores hard macro netlist data and wrapper module netlist data. The library DB 31 stores cell library data, hard macro library data, and buffer library data. The layout DB 32 stores hard macro layout data, black box layout data, and white box layout data.

  The layout unit 13 creates hard macro layout data using a hard macro netlist and cell library. The layout unit 13 stores the created hard macro layout data in the layout DB 32.

  Furthermore, the layout unit 13 uses the hard macro library, the wrapper module netlist, and the buffer library to create black box layout data. The layout unit 13 stores the created black box state layout data in the layout DB 32.

  Further, the layout unit 13 creates white box layout data using the hard macro layout data, the wrapper module netlist, and the buffer library. The layout unit 13 stores the created white box state layout data in the layout DB 32.

  Note that the layout unit 13 uses a common floor plan in creating the black box layout data and the white box layout data. That is, the layout position and state of the hard macro and the buffer are the same in the layout data in the black box state and the layout data in the white box state. This is to prevent differences in layout data timing verification depending on the positions and states of hard macros and buffers.

  The verification unit 14 verifies whether or not the hard macro described in the layout data created by the layout unit 13 satisfies a predetermined function or performance with actual wiring. For example, the verification unit 14 verifies whether the hard macro operates at a predetermined driving speed or a predetermined clock.

  The library creating unit 15 creates a hard macro library using the hard macro layout data and the cell library. The library creation unit 15 creates a hard macro timing library by adding a margin to the timing standard. Then, the library creation unit 15 stores the created hard macro library data in the library DB 31.

  The library verification unit 16 verifies whether or not the hard macro library is a desired library. For example, the library verification unit 16 verifies whether the timing standard described in the hard macro timing library is an appropriate value. When a margin is added to the timing standard described in the hard macro timing library, the library verification unit 16 verifies whether or not the added margin is accurately reflected.

  The external terminal extraction unit 17 uses the hard macro netlist to extract external terminals of the hard macro described in the hard macro netlist. For example, when a hard macro module name is designated by a user such as a hard macro designer, an external terminal of the hard macro corresponding to the hard macro module name is extracted. Alternatively, a hard macro external terminal corresponding to a specific hard macro module name may be previously extracted from the hard macro netlist.

The net list creation unit 18 uses the buffer library and the external terminals extracted by the external terminal extraction unit 17 to generate a net list of a wrapper module including a hard macro and a buffer connected to the external terminal of the hard macro. create. Then, the netlist creation unit 18 stores the created wrapper module netlist in the netlist DB 30.

  The timing standard extraction unit 19 uses the black box state layout data and the hard macro library to extract the timing standard described in the hard macro library. For example, the timing standard extraction unit 19 obtains the position where the buffer is arranged from the layout data in the black box state. Then, the timing standard extracting unit 19 extracts a timing standard corresponding to the buffer arrangement position from the hard macro library. In this case, the timing standard extraction unit 19 extracts a timing standard corresponding to the buffer arrangement position for each external terminal of the hard macro. The black box layout data is layout data in which the internal structure of the hard macro is not described. Therefore, by using the black box layout data and the hard macro library, the timing standard extraction unit 19 extracts the timing standard described in the hard macro library.

  The timing standard calculation unit 20 calculates the timing standard using the layout data in the white box state. For example, the timing standard calculation unit 20 obtains the position where the buffer is arranged from the layout data in the white box state. Then, the timing standard calculator 20 uses the white box layout data to calculate a timing standard corresponding to the buffer arrangement position. In this case, the timing standard calculation unit 20 calculates a timing standard corresponding to the buffer arrangement position for each external terminal of the hard macro. The white box layout data is layout data in which the internal structure of the hard macro is described. Therefore, by using the layout data in the white box state, the timing standard calculation unit 20 calculates the timing standard corresponding to the buffer arrangement position.

  The timing standard comparison unit 21 compares the timing standard extracted by the timing standard extraction unit 19 with the timing standard calculated by the timing standard calculation unit 20 for each external terminal of the hard macro. Specifically, the timing standard comparison unit 21 has a condition that the timing standard extracted by the timing standard extraction unit 19 is more marginally conditional than the timing standard extracted by the timing standard calculation unit 20 for each external terminal of the hard macro. It is determined whether or not there is. For example, when the timing standard is a setup time, the timing standard comparison unit 21 determines whether the setup time extracted by the timing standard extraction unit 19 is longer than the setup time extracted by the timing standard calculation unit 20. judge.

  When the timing standard extracted by the timing standard extracting unit 19 has a condition that is not marginally larger than the timing standard extracted by the timing standard calculating unit 20 for one or more external terminals of the hard macro, the timing standard comparing unit 21 Notifies the layout unit 13. Upon receiving the notification from the timing standard comparison unit 21, the layout unit 13 changes the floor plan, and again creates black box layout data and white box layout data.

  FIG. 3 is a flowchart showing the flow of provided data creation processing executed by the design support apparatus. The design support apparatus executes provided data creation processing when necessary data and commands are input via the operation unit 11. First, the design support apparatus creates hard macro layout data using a hard macro netlist and cell library (S01).

Next, the design support apparatus verifies the timing with the actual wiring as to whether or not the hard macro described in the layout data created in the process of S01 satisfies a predetermined function or performance (S02). .

  When the hard macro described in the layout data created in the process of S01 does not satisfy the predetermined function or performance (NO in the process of S02), the present design support apparatus returns to the process of S01, and the hard macro Recreate the layout data.

  On the other hand, when the hard macro described in the layout data created in the process of S01 satisfies a predetermined function or performance (YES in the process of S02), the design support apparatus proceeds to the process of S03. The design support apparatus creates a hard macro library using the hard macro layout data and the cell library (S03). Next, the design support apparatus verifies whether or not the hard macro library is a desired library (S04).

  If the hard macro library is not the desired library (NO in the process of S04), the design support apparatus returns to the process of S03 and recreates the hard macro library. On the other hand, when the hard macro library is a desired library (YES in the process of S04), the design support apparatus proceeds to the process of S05. The design support apparatus extracts the external terminals of the hard macro described in the hard macro netlist (S05).

  Next, the design support apparatus creates a netlist of wrapper modules including a hard macro and a buffer connected to an external terminal of the hard macro (S06). The design support apparatus creates black box layout data using the hard macro library, the wrapper module netlist, and the buffer library (S07).

  Next, the design support apparatus uses the hard macro layout data, the wrapper module netlist, and the buffer library to create white box layout data (S08).

  Then, the present design support apparatus uses the black box layout data and the hard macro library to extract the timing standard described in the hard macro library (S09). Next, the design support apparatus calculates a timing standard using the layout data in the white box state (S10).

  Then, the present design support apparatus compares the timing standard extracted in the process of S09 with the timing standard calculated in the process of S10 (S11). Specifically, it is determined for each external terminal of the hard macro whether or not the timing standard extracted in the process of S09 has a conditional margin than the timing standard calculated in the process of S10.

  If the timing standard extracted in S09 for one or more of the external terminals of the hard macro has no conditional margin than the timing standard calculated in S10 (NO in S11), this design The support apparatus returns to the process of S07 and recreates the layout data. In this case, the present design support apparatus changes the floor plan and creates layout data again.

  On the other hand, for all the external terminals of the hard macro, when the timing standard extracted in the process of S09 has a conditional margin than the timing standard calculated in the process of S10 (YES in the process of S11), this design The support device ends the provided data creation process.

The hard macro library created in the process of S03, the wrapper module netlist created in the process of S06, and the black box layout data created in the process of S07 are data provided to the LSI chip designer. Since the buffer library used in the processes of S07 and S08 is common to the buffer library used by the LSI chip designer, it is not included in the data provided to the LSI chip designer.

<Explanation of timing table>
Next, the timing table in the hard macro timing library will be described with reference to FIGS. When designing a hard macro and a buffer in designing an LSI chip, a timing table in the hard macro timing library is referred to. In the timing table, the hard macro timing standard is described corresponding to the external condition of the hard macro. The external condition of the hard macro in this case is waveform rounding of the input signal (degradation of the waveform) at the input terminal of the hard macro, and external capacitance (external load) of the output terminal at the output terminal of the hard macro.

  4, 6, and 8 are arrangement examples of the hard macro 40 and the buffer 42 when the buffer 42 is connected to the external terminal 41 of the hard macro 40. The buffer 42 and the clock buffer 43 can be connected to the external terminal 41 of the hard macro 40 by connecting a wiring 45 to an arbitrary portion of the external terminal side 44. The buffers 42A, 42B, 42C, 42D, and 42E shown in FIGS. 4, 6, and 8 have the same drive capability, and are connected to the external terminals 41 of the hard macro 40 on a one-to-one basis. The clock buffer 43 is a cell that supplies a clock to the hard macro 40. In FIGS. 4, 6 and 8, the clock of the hard macro 40 is one system. 4 to 9, the buffers 42A, 42B, 42C, 42D, and 42E are collectively referred to as the buffer 42.

  5, 7, and 9 are examples of the timing table 50, and are explanatory diagrams of reference parts of the timing table 50 when the timing library of the hard macro 40 is referred to. FIG. 5 is an explanatory diagram of reference locations in the timing table 50 when the arrangement of the hard macro 40 and the buffer 42 is the arrangement example of FIG. FIG. 7 is an explanatory diagram of reference locations in the timing table 50 when the arrangement of the hard macro 40 and the buffer 42 is the arrangement example of FIG. FIG. 9 is an explanatory diagram of reference locations in the timing table 50 when the arrangement of the hard macro 40 and the buffer 42 is the arrangement example of FIG.

  The row parameter of the timing table 50 shown in FIGS. 5, 7, and 9 indicates the degree of influence of waveform rounding of the signal input from the clock buffer 43. Specifically, the position of the clock buffer 43, the length of the wiring 45, and the like correspond to the row parameter of the timing table 50, and the timing table 50 corresponds to the position of the clock buffer 43, the length of the wiring 45, and the like. The row parameter is referenced. When the upper row parameter of the timing table 50 is referred to, it means that the waveform rounding is less affected than the lower row parameter and a steep waveform is input from the clock buffer 43.

The column parameter of the timing table 50 indicates the degree of influence of waveform rounding of a signal input from the buffer 42 when the external terminal 41 of the hard macro 40 is an input terminal. The column parameter of the timing table 50 indicates the degree of influence of the external capacitance of the output terminal when the external terminal 41 of the hard macro 40 is an output terminal. Specifically, the position of the buffer 42, the length of the wiring 45, and the like correspond to the column parameter of the timing table 50, and the column of the timing table 50 corresponds to the position of the buffer 42, the length of the wiring 45, and the like. The parameter is referenced. When the external terminal 41 is an input terminal, if the left column parameter is referred to, it means that the waveform rounding is less affected than the right column parameter, and a steep waveform is input from the buffer 42. . Further, when the external terminal 41 is an output terminal, when the left column parameter is referred to, it means that the external capacitance has less influence than the right column parameter.

  4 and 5 will be described. In FIG. 4, the buffer 42 </ b> B and the clock buffer 43 are arranged close to the external terminal 41 of the hard macro 40, but the buffers 42 </ b> A, 42 </ b> C, 42 </ b> D and 42 </ b> E are connected to the external terminal 41 of the hard macro 40. Are not placed close together. The arrangement shown in FIG. 4 may occur when a floor plan in which the buffer 42 is arranged close to the external terminal 41 of the hard macro 40 is not used.

  In FIG. 4, the clock buffer 43 is disposed in the vicinity of the external terminal 41 of the hard macro 40, so the top row parameter is referenced in the timing table 50 shown in FIG. 5. Then, according to the position of the buffer 42, the length of the wiring 45, etc., the column parameters of the timing table 50 in FIG. 5 are referred to, and the timing standard for the input terminal or the output terminal is determined.

  For example, in the design of an LSI chip, when the hard macro 40 and the buffer 42 are arranged as shown in FIG. 4, the timing standards described in the fields 1A, 1B, 1C, 1D and 1E of the timing table 50 in FIG. Is referenced.

  6 and 7 will be described. In FIG. 6, the clock buffer 43 and the buffers 42 </ b> A, 42 </ b> B, 42 </ b> C, 42 </ b> D, and 42 </ b> E are not disposed close to the external terminal 41 of the hard macro 40. The arrangement shown in FIG. 6 may occur when a floor plan in which the clock buffer 43 and the buffer 42 are arranged close to the external terminal 41 of the hard macro 40 is not used.

  In FIG. 6, since the clock buffer 43 is disposed farthest from the external terminal 41 of the hard macro 40, the lowest row parameter is referred to in the timing table 50 shown in FIG. Then, according to the position of the buffer 42, the length of the wiring 45, and the like, the column parameter of the timing table 50 in FIG. 7 is referred to, and the timing standard for the input terminal or the output terminal is determined.

  In FIG. 6, since the buffer 42 and the clock buffer 43 are not arranged close to the external terminal 41 of the hard macro 40, the wiring 45 becomes long and is easily affected by the wiring delay. Therefore, in the timing table 50 shown in FIG. 7, the timing standard is determined by referring to the lowest row parameter and the row parameters C, D, and E. For example, in the design of an LSI chip, when the hard macro 40 and the buffer 42 are arranged as shown in FIG. 6, the timing standards described in the fields 5C, 5D, and 5E in FIG. 7 are referred to.

  8 and 9 will be described. In FIG. 8, the buffer 42 and the clock buffer 43 are arranged close to the external terminal 41 of the hard macro 40. The arrangement of FIG. 8 is a case where the buffer 42 and the clock buffer 43 are arranged using a floor plan in which the buffer 42 and the clock buffer 43 are arranged close to the external terminal 41 of the hard macro 40.

  In FIG. 8, the clock buffer 43 is disposed close to the external terminal 41 of the hard macro 40, and therefore, the top row parameter is referred to in the timing table 50 illustrated in FIG. 9. Then, according to the position of the buffer 42, the length of the wiring 45, etc., the column parameters of the timing table 50 in FIG. 9 are referred to, and the timing standard for the input terminal or the output terminal is determined.

In FIG. 8, the buffer 42 and the clock buffer 43 are the external terminals 4 of the hard macro 40.
1, the wiring 45 is shortened and is not easily affected by the wiring delay. Therefore, in the timing table 50 shown in FIG. 9, the timing standard is determined by referring to the uppermost row parameter and column parameter A. For example, in the design of an LSI chip, when the hard macro 40 and the buffer 42 are arranged as shown in FIG. 8, the timing standard described in the field 1A of the timing table 50 in FIG. 9 is referred to.

  The support design apparatus creates a hard macro timing library on the assumption that the buffer 42 is disposed close to the external terminal 41 of the hard macro 40. That is, this support design apparatus assumes a state in which the hard macro 40 and the buffer 42 are arranged by using a floor plan in which the buffer 42 is arranged close to the external terminal 41 of the hard macro 40. Create a hard macro timing library.

  For example, a hard macro timing library is created assuming the arrangement state of FIG. As described above, in the LSI chip design, when the hard macro 40 and the buffer 42 are arranged as shown in FIG. 8, the timing standard described in the field 1A of the timing table 50 in FIG. 9 is referred to.

  Therefore, the support design apparatus creates a hard macro timing library by focusing on the timing standard referred to in the design of the LSI chip. Specifically, the support design apparatus creates a hard macro timing library by describing in the timing table 50 only the timing standards referred to in the LSI chip design. Thereby, the man-hours for creating and verifying the hard macro library can be reduced.

  By narrowing down the timing standards, the data amount of the timing standards described in the timing table 50 is reduced, and the file size (data amount) of the hard macro timing library can be reduced.

  Further, even in the arrangement state of FIG. 8, the external capacitance may be different for each external terminal 41. In this case, it suffices to increase the reference location of the timing standard in the timing table 50 in accordance with the external capacity that is different for each external terminal 41. Then, by reducing the timing standards that are unlikely to be referenced in the timing table 50 of FIG. 9, the timing table 50 corresponding to the external capacity that differs for each external terminal 41 is created without increasing the data amount of the timing library. can do.

  Next, the net list of the wrapper module 60 created by the net list creation unit 18 will be described. FIG. 10 shows an example of the net list of the wrapper module 60. FIG. 11 shows a conceptual diagram of the wrapper module 60 described in the net list of the wrapper module 60 of FIG. The wrapper module 60 in FIG. 11 includes external terminals 61A, 61B, 61C, and 61D corresponding to the external terminals 41A, 41B, 41C, and 41D of the hard macro 40. The wrapper module 60 includes a buffer module 62 for attracting arrangement that connects the external terminals 41A, 41B, 41C, and 41D and the external terminals 61A, 61B, 61C, and 61D, respectively. In the following, external terminals 41A, 41B, 41C, and 41D are collectively referred to as external terminals 41, and external terminals 61A, 61B, 61C, and 61D are collectively referred to as external terminals 61.

  In line 1 of the netlist of the wrapper module 60 in FIG. 10, “module Wrapper (A, B, C, D)” is described. This indicates that Wrapper is defined as the top module name, and the external terminals 61 of the wrapper module 60 are named A, B, C, and D.

  In the line 3-6 of the netlist of the wrapper module 60 in FIG. 10, “input A;”, “input B;”, “output C;”, “output D;” are described. This is an input / output definition of the external terminal 61 of the wrapper module 60. That is, the netlist of the wrapper module 60 in FIG. 10 defines that input A and input B are input terminals, and output C and output D are output terminals.

  In the line 8 of the netlist of the wrapper module 60 in FIG. 10, “wire In # A, In # B, Out # C, Out # D;” is described. This is connection information inside the wrapper module 60. In this example, four pieces of net connection information “In # A”, “In # B”, “Out # C”, and “Out # D” are defined.

In the line 10 of the netlist of the wrapper module 60 of FIG. 10, "HARDMACRO hardmacro (.A (In # A), .B (In # B), .C (Out # C), .D (Out # D)");"Is described. As a result, the HARDMACRO (hard macro 4
0) will be defined. Then, the module named “HARDMACRO” is named “macromacro” as a unique name, and defines what is connected to the terminal of HARDMACRO. That is, a net called In # A is connected to terminal A of HARDMACRO, a net called In # B is connected to terminal B of HARDMACRO, a net called In # C is connected to terminal C of HARDMACRO, and a terminal of HARDMACRO It is defined that a net called In # D is connected to D. In FIG. 11, the wiring 45A is connected to the external terminal 41A, the wiring 45B is connected to the external terminal 41B, the wiring 45C is connected to the external terminal 41C, and the wiring 45D is connected to the external terminal 41D. Is shown.

In the line 12-14 of the netlist of the wrapper module 60 of FIG. 10, “HIKITSUKE # BUF hikitsuke # buf (.In # Buf # A (A), .Out # Buf # A (In # A), .In # Buf # B (B), .Out # Buf # B (In # B), .In # Buf # C (Out # C), .Out # Buf # C (C). .In # Buf # D (Out # D), .Out # Buf # D (D)) ”. As a result, HIKITSUKE # BUF (buffer module 62) is defined as a submodule existing in the wrapper module 60. Then, the module name macro named HIKITSUKE # BUF is named as hikitsuke # buf as a unique name, and defines what is connected to HIKITSUKE # BUF.

  In the netlist lines 19-20 of the wrapper module 60 of FIG. #C, Out # Buf # C, In # Buf # D, Out # Buf # D); This defines the terminals of HIKITSUKE # BUF and HIKITSUKE # BUF as submodules existing in the wrapper module 60.

In the netlist lines 22-29 of the wrapper module 60 of FIG. 10, “input In # Buf # A;”, “input In # Buf # B;”, “input In # Buf # C;”, “input In” # Buf # D; ”,“ output Out # Buf # A; ”,“ output Out # Buf # B; ”,“ output Out # Buf # C; ”,“ output Out # Buf # D; ” Yes. This is the input / output definition of the HIKITSUKE # BUF terminal. That is, FIG.
In the netlist of the wrapper module 60 of 0, “In # Buf # A”, “In # Buf # B”, “In # Buf # C”, and “In # Buf # D” are input terminals, and “Out # It is defined that “Buf # A”, “Out # Buf # B”, “Out # Buf # C”, and “Out # Buf # D” are output terminals. In FIG. 11, it is shown that the external terminal 63A, the external terminal 63B, the external terminal 63C, and the external terminal 63D are input terminals of the buffer module 62, and the external terminal 64A, the external terminal 64B, the external terminal 64C, and the external terminal 64D are the buffers. The output terminal of the module 62 is shown.

In the line 31 of the netlist of the wrapper module 60 of FIG. 10, “BUFFER buf # A (.A (In # Buf # A), .Y (Out # Buf # A));” is described. This names a unit cell named BUFFER as buf # A with a unique name, and defines what is connected to the BUFFER terminal. That is, “In # Buf # A” is connected to the terminal A of “BUFFER (buf # A)”, and “Out # Buf # A” is connected to the terminal Y of “BUFFER (buf # A)”. It is defined. In FIG.
It is shown that the input terminal 63A is connected to the terminal A of the buffer 42A, and the output terminal 64A is connected to the terminal Y of the buffer 42A. The same applies to the lines 32-34 of the net list of the wrapper module 60 of FIG.

In the line 19-34 of the netlist of the wrapper module 60 of FIG. 10, HIKITSUKE # BUF
Is defined (description). On the other hand, in the line 10 of the netlist of the wrapper module 60 in FIG. 10, HARDMACRO is called, but the internal structure of HARDMACRO is not defined (described). Therefore, when the hard macro library is used when creating the layout data of the hard macro 40 and the buffer 42, the layout data in the black box state is created. On the other hand, when the hard macro layout data is used when creating the layout data of the hard macro 40 and the buffer 42, the layout data in the white box state is created.

  Next, the layout data of the wrapper module 60 created by the layout unit 13 will be described. FIG. 12 is an example of the layout data of the wrapper module 60. In the layout data of the wrapper module 60 shown in FIG. 12, a hard macro 40 and a buffer 42 are arranged. The shape of the hard macro 40 is rectangular, and an external terminal side 44 is provided on one side of the hard macro 40. In this specification, a rectangle means a right-angled quadrilateral including a rectangle and a square.

  In the layout data of the wrapper module 60 shown in FIG. 12, a buffer arrangement area (also referred to as a unit cell arrangement area) 70 for arranging the buffer 42 is provided, and the buffer 42 is arranged in the buffer arrangement area 70. Yes. The layout data of the wrapper module 60 is provided with an area (also referred to as a circuit block arrangement area) where the hard macro 40 is arranged, and the hard macro 40 is provided there. A cell power supply 71 is provided in the buffer arrangement area 70 so as to be adjacent to the buffer 42. As shown in FIG. 12, the buffer arrangement area 70 is provided close to the hard macro 40. Therefore, the buffer 42 is in a state of being disposed close to the external terminal side 44 of the hard macro 40. The external terminal 41 can be provided at an arbitrary position on the external terminal side 44 of the hard macro 40.

  Further, the external terminal 41 and the buffer 42 are connected by a wiring 45. Then, as shown in FIG. 12, the buffer arrangement region 70 is arranged in the extending direction of the wiring 45 connected to the external terminal 41. As described above, the horizontal width of the buffer arrangement region 70 may be provided according to the length of the external terminal side 44 provided in the hard macro 40. Further, the horizontal width of the buffer arrangement region 70 may be made shorter than the length of the external terminal side 44 provided in the hard macro 40. Further, the horizontal width of the buffer arrangement area 70 may be made longer than the length of the external terminal side 44 provided in the hard macro 40.

  Note that the shape of the hard macro 40 may be non-rectangular. When the shape of the hard macro 40 is non-rectangular, the buffer arrangement area 70 may be provided for the external terminal side 44 provided in the hard macro 40 as in the case where the shape of the hard macro 40 is rectangular. That is, the buffer arrangement area 70 may be provided in accordance with the shape of the hard macro 40.

FIG. 13 is an example of the layout data of the wrapper module 60. In the layout data of the wrapper module 60 shown in FIG. 13, a hard macro 40 and a buffer 42 are arranged. The shape of the hard macro 40 is a rectangle, and external terminal sides 44 are provided on four sides of the hard macro 40.

  In the layout data of the wrapper module 60 shown in FIG. 13, buffer arrangement areas 70 are provided for the four sides of the hard macro 40, and the buffer 42 is arranged in the buffer arrangement area 70. That is, the layout data of the wrapper module 60 shown in FIG. 13 is provided with the buffer arrangement area 70 for all the external terminal sides 44 provided on the four sides of the hard macro 40. A cell power supply 71 is provided in the buffer arrangement area 70 so as to be adjacent to the buffer 42. Note that the layout data of the wrapper module 60 is provided with an area in which the hard macro 40 is arranged, as in FIG.

  As shown in FIG. 13, the buffer arrangement area 70 is provided close to the hard macro 40. Therefore, the buffer 42 is in a state of being disposed close to the external terminal side 44 of the hard macro 40. The external terminal 41 can be provided at an arbitrary position on the external terminal side 44 of the hard macro 40. Further, the external terminal 41 and the buffer 42 are connected by a wiring 45.

  Note that the shape of the hard macro 40 may be non-rectangular. When the shape of the hard macro 40 is non-rectangular, the buffer arrangement area 70 may be provided for the external terminal side 44 provided in the hard macro 40 as in the case where the shape of the hard macro 40 is rectangular. That is, the buffer arrangement area 70 may be provided in accordance with the shape of the hard macro 40.

<Description of Pattern Example of Wrapper Module 60>
In designing an LSI chip, an LSI chip designer determines in which location and in which direction the wrapper module 60 is arranged. Therefore, when designing the LSI chip, a plurality of patterns of the wrapper module 60 are prepared in advance so as not to limit the arrangement location and the arrangement direction of the wrapper module 60. FIG. 14 is an explanatory diagram of a pattern example of the wrapper module 60.

  The wrapper modules 60A to 60D illustrated in FIG. 14 include buffers 42A to 42G, respectively. The buffers 42 </ b> A to 42 </ b> G are in a state of being arranged close to the external terminal side 44 of the hard macro 40. The wrapper module 60A and the wrapper module 60B shown in FIG. 14 are targeted with the line A as an axis. The wrapper module 60A and the wrapper module 60C shown in FIG. 14 are targeted with the line B as an axis. The wrapper module 60A and the wrapper module 60D shown in FIG. 14 have a rotational symmetry of 180 degrees.

  Further, the wrapper modules 60E to 60H illustrated in FIG. 15 include buffers 42H to 42N, respectively. The buffers 42 </ b> H to 42 </ b> N are arranged in proximity to the external terminal side 44 of the hard macro 40. The wrapper module 60E and the wrapper module 60F illustrated in FIG. 15 are targeted with the line A as an axis. The wrapper module 60E and the wrapper module 60G illustrated in FIG. 15 are targeted with the line B as an axis. The wrapper module 60E and the wrapper module 60H shown in FIG. 15 have a rotational symmetry of 180 degrees.

<Use of Buffer Arrangement Area 70 in Wrapper Module 60>
The use of the buffer arrangement area 70 in the wrapper module 60 in designing an LSI chip will be described with reference to FIGS. FIGS. 16 and 17 are explanatory diagrams when the wrapper module 60 is arranged on the LSI chip. In the wrapper module 60 shown in FIGS. 16 and 17, the external terminal side 44 is provided on the upper side of the hard macro 40.
A buffer arrangement area 70 surrounded by a thick line is arranged close to the external terminal side 44 of the hard macro 40. In FIGS. 16 and 17, the area surrounded by the dotted line is the LSI chip logic area 80, which is an area where the logic (logic circuit) of the LSI chip can be placed.

  The internal structure of the buffer 42 arranged in the buffer arrangement area 70 in the wrapper module 60 is described in the layout data of the wrapper module 60. Therefore, the buffer arrangement area 70 in the wrapper module 60 can be expanded in a hierarchy on the LSI chip. The buffer arrangement area 70 in FIG. 16 is before hierarchical development, and the buffer arrangement area 70 in FIG. 17 is after hierarchical development. In the buffer arrangement area 70 of FIG. 17, there is a place where the buffer 42 is not arranged, and the LSI chip logic can be arranged in the empty area in the buffer arrangement area 70 where the buffer 42 is not arranged. is there. Accordingly, by expanding the buffer arrangement area 70 of the wrapper module 60 in a hierarchical manner, the free area in the buffer arrangement area 70 can be effectively used.

<Example of Connection Wiring between External Terminal 41 of Hard Macro 40 and Buffer 42>
As described above, the layout data of the wrapper module 60 created by the present design support apparatus is provided with the wiring 45 that connects the external terminal 41 of the hard macro 40 and the buffer 42. Furthermore, the design support apparatus may create layout data of the wrapper module 60 in which the wiring 45 that connects the external terminal 41 of the hard macro 40 and the buffer 42 is not provided. When using the layout data of the wrapper module 60 in which the wiring 45 that connects the external terminal 41 of the hard macro 40 and the buffer 42 is not used, the LSI chip designer can select the shortest path according to the situation on the LSI chip. Wiring 45 can be provided so that

  FIG. 18 is a diagram showing a pattern when the external terminal 41 of the hard macro 40 and the buffer 42 are connected. In the example of FIG. 18, the LSI chip designer uses the layout data of the wrapper module 60 in which the wiring 45 that connects the external terminal 41 of the hard macro 40 and the buffer 42 is not provided.

  In FIG. 18, the buffer 42 is disposed close to the external terminal 41 of the hard macro 40. In the example of FIG. 18, there are two types of wiring route pattern A and wiring route pattern B. When such a wiring route pattern exists, the LSI chip designer can select the wiring route pattern A or the wiring route pattern B in accordance with the design situation of the LSI chip.

  In addition, when using the layout data of the wrapper module 60 provided with the wiring 45 that connects the external terminal 41 of the hard macro 40 and the buffer 42, the LSI chip designer, depending on the situation on the LSI chip, It is also possible to change the wiring route pattern. For example, when the LSI chip is designed using the layout data of the wrapper module 60 provided with the wiring 45 by the wiring path pattern A shown in FIG. Can be changed. This is effective when the LSI chip designer wants to switch to the wiring 45 by the wiring route pattern B for some reason (for example, priority is given to other wiring of the LSI chip).

<Application example of layout data of wrapper module 60>
Normally, when designing the hard macro 40 as a general-purpose macro, the design status of the LSI chip cannot be confirmed, and it is difficult to estimate the influence of a voltage drop that causes an operation failure. In such a case, it is desired to create layout data that suppresses the influence of the voltage drop on the hard macro 40.

  FIG. 19 shows layout data of the wrapper module 60 in which the power supply wiring (also referred to as a reinforced power supply ring) 90 is provided on the outer periphery of the hard macro 40. As shown in FIG. 19, power supply wiring 90 is provided so as to surround the hard macro 40, and the voltage source for the hard macro 40 is strengthened. Further, the hard macro 40 and the buffer 42 shown in FIG. 19 have the same configuration as the hard macro 40 and the buffer 42 described in FIG. As described above, by creating layout data in which the power supply wiring 90 is provided on the outer periphery of the hard macro 40 in advance, it is possible to suppress the influence of the voltage drop on the hard macro 40.

  10 to 19 do not refer to the clock buffer 43, the wrapper module 60 may include the clock buffer 43. That is, the clock buffer 43 may be disposed close to the external terminal 41 of the hard macro 40. In this case, any of the buffers 42 may be replaced with the clock buffer 43.

<Computer-readable recording medium>
A program that causes a computer to realize any of the above functions can be recorded on a computer-readable recording medium. The function can be provided by causing the computer to read and execute the program of the recording medium. Here, the computer-readable recording medium refers to a recording medium that accumulates information such as data and programs by electrical, magnetic, optical, mechanical, or chemical action and can be read from the computer. Examples of such a recording medium that can be removed from the computer include a flexible disk, a magneto-optical disk, a CD-ROM, a CD-R / W, a DVD, a DAT, an 8 mm tape, and a memory card. Moreover, there are a hard disk, a ROM and the like as a recording medium fixed to the computer.

The aspects of the present invention are summarized as additional notes below.
(Appendix 1)
A method of creating design data of a semiconductor integrated circuit used for design by a computer,
Computer
Creating a circuit block library in which circuit block shape information, terminal position information and timing information are described;
Creating a netlist describing connection information of module circuits having unit cells connected to the circuit blocks and the circuit blocks;
Using the unit cell library in which the shape information, terminal position information, and timing information of the unit cell are described, the circuit block library, and the netlist, a circuit block arrangement area in which the circuit block is arranged, and the unit cell Creating module module layout data in which unit cell placement areas to be placed are provided in a predetermined state, and
The circuit block library is a method for creating design data of a semiconductor integrated circuit in which timing information of the circuit block is described when the circuit block arrangement area and the unit cell arrangement area are provided in a predetermined state.
(Appendix 2)
The design of the semiconductor integrated circuit according to appendix 1, wherein the circuit block library describes timing information of the circuit block when the circuit block arrangement area and the unit cell arrangement area are provided close to each other. How to create data.
(Appendix 3)
The method for creating design data of a semiconductor integrated circuit according to appendix 1 or 2, wherein the unit cell arrangement area is provided around the circuit block arrangement area.
(Appendix 4)
4. The method of creating design data for a semiconductor integrated circuit according to any one of appendices 1 to 3, wherein the layout data is further provided with a power supply wiring region for supplying power to the circuit block.
(Appendix 5)
The layout data further includes wiring connecting the circuit block and the unit cell,
5. The method for creating design data of a semiconductor integrated circuit according to any one of appendices 1 to 4, wherein the unit cell arrangement region is provided in an extension direction of the wiring.
(Appendix 6)
6. The method of creating design data of a semiconductor integrated circuit according to any one of appendices 1 to 5, wherein the unit cell arrangement region is expandable.
(Appendix 7)
7. The method for creating design data of a semiconductor integrated circuit according to any one of appendices 1 to 6, wherein the unit cell arrangement area is provided according to a shape and a terminal position of the circuit block.

It is a figure which shows the hardware constitutions of the computer for implement | achieving this design support apparatus. It is a functional block diagram of this design support apparatus. It is a flow which shows the flow of the provision data creation process which this design support apparatus performs. It is a figure which shows the example of arrangement | positioning of a hard macro and a buffer. It is explanatory drawing of the reference location of a timing table in case the timing library of a hard macro is referred. It is a figure which shows the example of arrangement | positioning of a hard macro and a buffer. It is explanatory drawing of the reference location of a timing table in case the timing library of a hard macro is referred. It is a figure which shows the example of arrangement | positioning of a hard macro and a buffer. It is explanatory drawing of the reference location of a timing table in case the timing library of a hard macro is referred. It is a figure which shows the example of the net list of a wrapper module. It is a conceptual diagram of the wrapper module described in the net list of the wrapper module. It is a figure which shows the example of the layout data of a wrapper module. It is a figure which shows the example of the layout data of a wrapper module. It is explanatory drawing about the example of a pattern of a wrapper module. It is explanatory drawing about the example of a pattern of a wrapper module. It is explanatory drawing about arrangement | positioning of the wrapper module on a LSI chip. It is explanatory drawing about arrangement | positioning of the wrapper module on a LSI chip. It is a figure which shows the pattern in the case of connecting the external terminal and buffer of a hard macro. It is a figure which shows the layout data of the wrapper module which provided the power supply wiring in the outer periphery of the hard macro.

Explanation of symbols

1 Computer 2 CPU
3 Memory 4 Interface 5 Hard disk drive 6 Portable medium drive 7 Input device 8 Display device 11 Operation unit 12 Storage unit 13 Layout unit 14 Verification unit 15 Library creation unit 16 Library verification unit 17 External terminal extraction unit 18 Netlist creation unit 19 Timing standard extracting unit 20 Timing standard calculating unit 21 Timing standard comparing unit 30 Netlist database 31 Library database 32 Layout database

Claims (5)

A method of creating design data of a semiconductor integrated circuit used for design by a computer,
Computer
Creating a circuit block library in which circuit block shape information, terminal position information and timing information are described;
Creating a netlist describing connection information of module circuits having unit cells connected to the circuit blocks and the circuit blocks;
Using the unit cell library in which the shape information, terminal position information, and timing information of the unit cell are described, the circuit block library, and the netlist, a circuit block arrangement area in which the circuit block is arranged, and the unit cell Creating module module layout data in which unit cell placement areas to be placed are provided in a predetermined state, and
The circuit block library is a method for creating design data of a semiconductor integrated circuit in which timing information of the circuit block is described when the circuit block arrangement area and the unit cell arrangement area are provided in a predetermined state.   2. The semiconductor integrated circuit according to claim 1, wherein the circuit block library describes timing information of the circuit block in a case where the circuit block arrangement area and the unit cell arrangement area are provided close to each other. How to create design data.   3. The method of creating design data for a semiconductor integrated circuit according to claim 1, wherein the unit cell arrangement area is provided around the circuit block arrangement area.   4. The method for creating design data of a semiconductor integrated circuit according to claim 1, wherein the layout data is further provided with a power supply wiring region for supplying power to the circuit block. 5. The layout data further includes wiring connecting the circuit block and the unit cell,
5. The method for creating design data of a semiconductor integrated circuit according to claim 1, wherein the unit cell arrangement region is provided in an extending direction of the wiring.

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