KR102419645B1 - Computer-implemented method and computing system for designing integrated circuit and method of manufacturing integrated circuit - Google Patents

Abstract

The present disclosure discloses a computer-implemented method and computing system for the design of an integrated circuit. A computer-implemented method for designing an integrated circuit according to the technical concept of the present disclosure detects a connection relationship between polygons from layout data of an integrated circuit based on a rule file including a DRC syntax, and uses the detected connection relationship to provide layout data Extracts a layout netlist from , and performs LVS verification on the integrated circuit to generate LVS result data by comparing the schematic data of the integrated circuit with the layout netlist.

Description

TECHNICAL FIELD Computer-implemented method and computing system for designing integrated circuit and method of manufacturing integrated circuit

The technical idea of the present disclosure relates to an integrated circuit, and more particularly, to a computer-implemented method and computing system for designing an integrated circuit, and a manufacturing method of the integrated circuit.

An integrated circuit may be defined by schematic data including various elements such as transistors, resistors, diodes, and the like. The layout data of the integrated circuit may be generated based on the schematic data and may include a plurality of polygons. Layout-Versus-Schematic (LVS) verification may be performed to verify whether the layout data matches the schematic data. Specifically, the LVS verification may verify whether a net, a device, and a parameter match in the layout data and the schematic data. Four may correspond to one interconnection in the layout of the integrated circuit, and one interconnection may correspond to a wiring structure including metal layers and vias electrically connected to each other.

The technical idea of the present disclosure provides a computer-implemented method and computing system for designing an integrated circuit, and a method of manufacturing the integrated circuit.

A computer implemented method for designing an integrated circuit according to the technical spirit of the present disclosure includes, by a processor, a layout of the integrated circuit based on a rule file including a Design Rule Check (DRC) syntax. detecting connectivity of polygons from data, extracting a layout netlist from the layout data using the detected connectivity, and comparing the layout netlist with the schematic data of the integrated circuit. and performing LVS verification on the integrated circuit to generate Layout-Versus-Schematic (LVS) result data.

In addition, the method of manufacturing an integrated circuit according to the technical spirit of the present disclosure includes the steps of: detecting a connection relationship between polygons from the layout data, and extracting a layout netlist, by performing DRC on the layout data of the integrated circuit; generating LVS result data by performing LVS verification on a layout netlist and schematic data of the integrated circuit, and manufacturing the integrated circuit according to a layout based on the layout data and the LVS result data. .

In addition, the computing system for designing an integrated circuit according to the technical spirit of the present disclosure includes a memory storing an LVS engine for performing LVS verification on the integrated circuit, and being accessible to the memory and executing the LVS engine a processor, wherein the LVS engine detects a connection relationship of polygons from the layout data of the integrated circuit based on a rule file including a DRC syntax, and uses the detected connection relationship to a layout netlist from the layout data , and compares the extracted layout netlist with the schematic data of the integrated circuit.

According to the technical idea of the present disclosure, it is possible to automatically detect a connection relationship between polygons from layout data based on a rule file including a DRC syntax, and perform LVS verification using the detected connection relationship. Accordingly, since only essential connection relationships included in the layout data can be detected, the size of data corresponding to connection relationship information can be reduced. In addition, since the designer can omit the task of describing the direct connection relationship, the LVS coding time may be shortened, and at the same time, the LVS verification execution time may not increase. Furthermore, the DRC syntax can be implemented as a DRC loop syntax using a loop algorithm, and thus, it is possible to prevent omission of connection relationship information even if the number of polygons in the layout increases due to the miniaturization of the semiconductor process.

1 is a flowchart schematically illustrating a method of designing an integrated circuit according to an embodiment of the present disclosure.
2 is a block diagram illustrating a computing system for designing an integrated circuit according to an embodiment of the present disclosure.
3 is a block diagram illustrating an LVS engine according to an embodiment of the present disclosure.
4A shows an integrated circuit layout according to an embodiment of the present disclosure, and FIG. 4B shows an integrated circuit schematic according to an embodiment of the present disclosure.
5 shows a rule file and a connection relationship according to an embodiment of the present disclosure.
6 is a flowchart illustrating an LVS verification method for an integrated circuit according to an embodiment of the present disclosure.
7A illustrates an LVS operation according to an embodiment of the present disclosure, and FIG. 7B illustrates an LVS operation according to a comparative example of the present disclosure.
8 is a flowchart illustrating an LVS coding method according to an embodiment of the present disclosure.
9 is a block diagram illustrating an LVS engine according to an embodiment of the present disclosure.
10 is a block diagram illustrating an LVS engine according to an embodiment of the present disclosure.
11A shows an example of a wiring structure included in a layout of an integrated circuit according to an embodiment of the present disclosure, and FIG. 11B shows a rule file according to an embodiment of the present disclosure.
12A shows another example of a wiring structure included in a layout of an integrated circuit according to an embodiment of the present disclosure, and FIG. 12B shows a rule file according to an embodiment of the present disclosure.
13 shows an example of a rule file according to an embodiment of the present disclosure.
14 shows an example of a DRC operation according to an embodiment of the present disclosure, and FIG. 15 shows another example of a DRC operation according to an embodiment of the present disclosure.
16 to 21 are diagrams in accordance with some embodiments of the present disclosure; Examples of connection relationship detection operations by DRC are shown.
22 is a flowchart schematically illustrating a method of manufacturing an integrated circuit according to an embodiment of the present disclosure.
23 is a flowchart specifically illustrating a method of manufacturing an integrated circuit according to an embodiment of the present disclosure.
24 illustrates a computer-readable storage medium according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a flowchart schematically illustrating a method of designing an integrated circuit according to an embodiment of the present disclosure.

Referring to FIG. 1 , a method of designing an integrated circuit is a step of designing and verifying a layout for the integrated circuit, and may be performed using a tool for designing the integrated circuit. In this case, the tool for designing the integrated circuit may be a program or software module including a plurality of instructions executed by a processor, and may be stored in a computer-readable storage medium. Accordingly, the design method of the integrated circuit may be referred to as a computer implemented method for designing the integrated circuit.

In step S110, a gate-level netlist may be generated by synthesizing input data defined at a Register Transfer Level (RTL) for the integrated circuit using the standard cell library. For example, step S110 may be performed by a processor using a synthesis tool. In step S130, layout data of the integrated circuit is generated by placing and routing standard cells defining the integrated circuit according to the netlist (Placement & Routing, hereinafter referred to as "P&R"). For example, step S130 may be performed by a processor using a P&R tool. For example, the layout data may be data in a graphic design system (GDS) or GDSII format.

In step S150, LVS result data is generated by performing LVS verification on the integrated circuit. For example, step S150 may be performed by the processor using the LVS verification tool. Specifically, by performing a Design Rule Check (DRC) operation on the layout data, it is possible to automatically detect a connection relationship between polygons from the layout data, and perform LVS verification using the detected connection relationship. In this case, the LVS verification may refer to an operation of verifying whether the schematic data of the integrated circuit matches the layout data of the integrated circuit. According to an embodiment, the schematic data and the layout data may be provided as input files to the LVS verification tool, and the LVS result data may be output as an output file from the LVS verification tool.

In step S170, parasitic component data is generated by extracting a parasitic component from the layout data. For example, step S170 may be performed by the processor using a Parasitic Extraction (PEX) tool. For example, the parasitic component data may be generated as a Standard Parasitic Extraction Format (SPEF) file. According to an embodiment, the layout data may be provided as an input file to the PEX tool, and the SPEF file may be output as an output file from the P&R tool.

2 is a block diagram illustrating a computing system 100 for designing an integrated circuit according to an embodiment of the present disclosure.

Referring to FIG. 2 , a computing system for designing an integrated circuit (hereinafter referred to as an 'integrated circuit design system') 100 includes a processor 110 , a memory 130 , an input/output device 150 , and a storage device 170 . and a bus 190 . The integrated circuit design system 100 may perform an integrated circuit design operation including steps S110 to S170 of FIG. 1 . In an embodiment, the integrated circuit design system 100 may be implemented as an integrated device, and thus may be referred to as an integrated circuit design apparatus. The integrated circuit design system 100 may be provided as a dedicated device for designing an integrated circuit of a semiconductor device, or may be a computer for driving various simulation tools or design tools.

The processor 110 may be configured to execute instructions that perform at least one of various operations for designing an integrated circuit. The processor 110 may communicate with the memory 130 , the input/output device 150 , and the storage device 170 through the bus 190 . The processor 110 may execute an integrated circuit design operation by driving the synthesis module 130a, the P&R module 130b, the LVS module 130c, and the PEX module 130d loaded into the memory 130 .

The memory 130 may store the synthesis module 130a, the P&R module 130b, the LVS module 130c, and the PEX module 130d. The synthesis module 130a , the P&R module 130b , the LVS module 130c , and the PEX module 130d may be loaded into the memory 130 from the storage device 170 . The synthesis module 130a may be, for example, a program including a plurality of instructions for performing a logic synthesis operation according to step S110 of FIG. 1 . The P&R module 130b may be, for example, a program including a plurality of instructions for performing the P&R operation according to step S130 of FIG. 1 . The LVS module 130c may be, for example, a program including a plurality of instructions for performing the LVS verification operation according to step S150 of FIG. 1 . The PEX module 130d may be, for example, a program including a plurality of instructions for performing a parasitic extraction operation according to step S170 of FIG. 1 . The memory 130 may be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR flash memory.

The input/output device 150 may control user input and output from user interface devices. For example, the input/output device 150 may include input devices such as a keyboard, a mouse, and a touch pad to receive input data defining an integrated circuit. For example, the input/output device 150 may include an output device such as a display and a speaker, and may display an arrangement result, a routing result, a DRC result, an LVS result, or a PEX result. The storage device 170 may store various data related to the synthesis module 130a, the P&R module 130b, the LVS module 130c, and the PEX module 130d. The storage device 170 may include a memory card (MMC, eMMC, SD, MicroSD, etc.), a solid state drive (SSD), a hard disk drive (HDD), or the like.

3 is a block diagram illustrating an LVS engine 30 according to an embodiment of the present disclosure.

Referring to FIG. 3 , the LVS engine 30 may be a program that performs LVS verification for an integrated circuit, and may correspond to, for example, an example of the LVS module 130c stored in the memory 130 of FIG. 2 . have. The LVS engine 30 may include a plurality of procedures, such as a DRC verifier 31 and an LVS verifier 32 . Here, a procedure may refer to a series of instructions for performing a specific task, and may also be referred to as a function, a routine, a subroutine, a subprogram, and the like. In the present specification, when the processor (eg, 110 in FIG. 2 ) performs an operation by executing a procedure stored in the memory (eg, 130 in FIG. 2 ), the procedure is also referred to as performing such an operation. is expressed

The LVS engine 30 may receive the layout data D10 and the schematic data D20 . The layout data D10 may be topological data related to the layout of the integrated circuit, and may include a plurality of polygons. Through a semiconductor manufacturing process, the integrated circuit may have a structure in which a plurality of layers are stacked, and the layout data D10 of the integrated circuit may include topological information of the plurality of layers. The plurality of layers may include a conductive layer and an insulating layer, and the like, and the device of the integrated circuit may be configured as a pattern formed on one or more layers. In the layout data D10, a plurality of layers and a plurality of patterns may be displayed as polygons. In an embodiment, the layout data D10 may be output data of a P&R tool in which the P&R operation of step S130 of FIG. 1 is performed, but the present invention is not limited thereto.

The schematic data D20 may include devices such as transistors, resistors, and diodes, and may define a connection relationship between the devices. Specifically, in the schematic data D20 , an element of the integrated circuit may be defined as an instance of a corresponding symbol, and each of the instances may be connected through a wire. The symbol defines a device performing the same function, and each of the devices such as an NMOS transistor, a PMOS transistor, a diode, and a resistor may be defined as a unique symbol. For example, the schematic data D20 may include a transistor level netlist, a gate level netlist, a cell level netlist or an IP (Intellectual Property) level netlist, and the like. In an embodiment, the schematic data D20 may be output data of a synthesis tool on which the synthesis operation of step S110 of FIG. 1 is performed, but the present invention is not limited thereto. Hereinafter, the layout data D10 and the schematic data D20 will be described in detail with reference to FIGS. 4A and 4B .

4A shows an integrated circuit layout 41 according to an embodiment of the present disclosure, and FIG. 4B shows an integrated circuit schematic 42 according to an embodiment of the present disclosure.

3, 4A, and 4B together, the integrated circuit layout 41 may be defined by layout data D10. The integrated circuit layout 41 has an active region RX, a gate line GL, a first contact CA_N, a second contact CA_P, a via V0, and a first metal layer M1, each represented by polygons. ) may be included. The integrated circuit schematic 42 may be defined by schematic data D20 . The integrated circuit schematic 42 may include a CMOS transistor including a PMOS transistor TR1 and an NMOS transistor TR2.

The layout data D10 defining the integrated circuit layout 41 may be generated according to the schematic data D20 defining the integrated circuit schematic 42 . The LVS engine 30 verifies whether elements corresponding to instances included in the schematic data D20, for example, the PMOS transistor TR1 and the NMOS transistor TR2 exist in the layout data D10. can do. Also, the LVS engine 30 may verify whether the corresponding instance of the schematic data D20 and the element of the layout data D10 have the same parameter, for example, a length or a width. Hereinafter, a detailed operation of the LVS engine 30 will be described.

The DRC verifier 31 may generate the DRC result data D40 by performing DRC on the layout data D10 based on the rule file D30. Here, the rule file D30 may refer to an LVS rule file (or LVS rule deck) defining devices as a plurality of layers in the layout of the integrated circuit. For example, the rule file D30 may include a series of codes written according to a Standard Verification Rule Format (SVRF) or a TCL Verification Format (TVF).

In one embodiment, the rule file D30 may include a DRC syntax (DS), and the DRC verifier 31 may include layout data (DS) according to the DRC syntax included in the rule file D30. By performing DRC on D10), it is possible to automatically detect the connection relationship between polygons. In this case, the DRC result data D40 may include the detected connection relationship. In FIG. 3 , the DRC verifier 31 is illustrated as being included in the LVS engine 30 , but the present invention is not limited thereto. In some embodiments, the DRC verifier 31 is not included in the LVS engine 30 and may be implemented as a separate DRC engine. Hereinafter, the operation of the DRC verifier 31 will be described in detail with reference to FIG. 5 .

5 shows a rule file 51 and a connection relationship 52 according to an embodiment of the present disclosure.

3 to 5 , the rule file 51 may include first to fifth DRC phrases 511 to 515 . However, the present invention is not limited thereto, and the rule file 51 includes at least one of the first to fifth DRC phrases 511 to 515 or other than the first to fifth DRC phrases 511 to 515 . may further include other DRC constructs of In an embodiment, the first to fifth DRC constructs 511 to 515 may be DRC loop constructs implemented as a loop algorithm, and accordingly, a plurality of layers included in the layout data D10 and each layer. A DRC may be indicated for each of a plurality of polygons included. Hereinafter, first to fifth DRC syntaxes 511 to 515 will be described.

The first DRC syntax 511 may be configured to check whether two polygons are touched in order to detect a lateral connection relationship or a vertical connection relationship between polygons in the layout data D10. For example, the first DRC syntax 511 may be generated as “…{@ A INTERACT B}” or “…{@ A TOUCH B}”. In this case, A may represent a first polygon and B may represent a second polygon. In an embodiment, the layout data D10 may include the active area RX and the first contact CA_N respectively disposed in different layers, and the first DRC syntax 511 may include the active area RX. and a check of whether the first contact CA_N is touched (eg, “…{@ RX INTERACT CA_N}”). In an embodiment, the layout data D10 may include first and second contacts CA_N and CA_P included in the same layer, and the first DRC syntax 511 includes the first contact CA_N and the second contact CA_N. A check of whether the second contact CA_P has been touched may be indicated (eg, “…{@ CA_N INTERACT CA_P}”).

The second DRC syntax 512 may be configured to check whether at least three polygons are touched in order to detect a vertical connection relationship between polygons in the layout data D10 . For example, the second DRC syntax 512 may be generated as “…{@ (A INTERACT B) INTERACT C}” or “…{@ (A TOUCH B) TOUCH C}”. In this case, A, B, and C may represent first to third polygons disposed on different layers, respectively. In an embodiment, the layout data D10 may include a first contact CA_N, a via V0, and a first metal layer M1 disposed on different layers, respectively, and a second DRC syntax 512 . ) may indicate checking whether the first contact CA_N, the via V0, and the first metal layer M1 are touched (eg, “…{@ (M1 INTERACT CA_N) INTERACT V0}”) .

The third DRC syntax 513 may be configured to check whether polygons overlap in the layout data D10 . For example, the third DRC syntax 513 may be generated as “…{@ A AND B}”. In this case, A and B may represent first and second polygons disposed on the same layer, respectively. In an embodiment, the layout data D10 may include a first layer, and the third DRC syntax 513 determines whether the first and second polygons A and B included in the first layer overlap. You can order a check. The third syntax 513 will be described later with reference to FIG. 18 .

The fourth DRC syntax 514 may be configured to check a polygon that is not defined as a derived layer in the layout data D10 , that is, a missing polygon. For example, the fourth DRC syntax 514 may be generated as “…{@ M1 NOT A}”. In this case, M1 may indicate an original layer, and A may indicate a polygon derived from the original layer, that is, a derived layer. In one embodiment, the layout data D10 includes a first layer divided by at least one polygon, and the DRC syntax 514 checks whether there is a polygon that is not defined as at least one polygon on the first layer. can direct The fourth syntax 514 will be described later with reference to FIG. 19 .

The fifth DRC syntax 515 may be configured to check a floating net in the layout data D10 . For example, the fifth syntax 515 may be generated as “…{@ ((PORT1 INTERACT A) INTERACT B) INTERACT C}”. In this case, PORT1 may indicate a polygon corresponding to a specific port, and A to C may indicate first to third polygons disposed on different layers, respectively. The fifth syntax 515 will be described later with reference to FIGS. 20A and 20B .

As described above, a missing connection relationship, overlapping connection relationship, floating connection relationship, etc. may be detected using various DRC syntaxes such as the first to fifth DRC syntaxes 515 . According to an embodiment, various DRC syntaxes such as the first to fifth DRC syntaxes 515 may be implemented through a coding loop method to detect all connections included in layout data during a DRC operation.

The DRC verifier 31 may generate the DRC result data 52 by automatically detecting the first to fifth connection relationships 521 to 525 from the layout data D10 based on the rule file 51 . In one embodiment, the DRC verifier 31 performs the DRC on the layout data D10 according to the first DRS syntax 511 included in the rule file 51 , whereby the first contact CA_N and the second contact A first connection relationship 521 of (CA_P), a second connection relationship 522 between the active area RX and the first contact CA_N, and a third connection between the active area RX and the second contact CA_P A relationship 523 may be detected.

In addition, in one embodiment, the DRC verifier 31 performs DRC on the layout data D10 according to the second DRS syntax 512 included in the rule file 51, whereby the first metal layer M1, A fourth connection relationship 524 between the first contact CA_N and the via V0 and a fifth connection relationship 525 between the first metal layer M1, the second contact CA_P, and the via V0 are detected. can do. As such, the connection relationship information included in the DRC result data 52 may include first to fifth connection relationships 521 to 525, which are essential connection relationships of polygons actually connected in the layout data D10. can

In one embodiment, since the DRC verifier 31 performs DRC on the layout data D10 according to the DRC syntax, if a connection relationship corresponding to the DRC syntax is not detected in the layout data D10, detection is further performed. You can ignore the corresponding DRC statement without For example, in the case of the DRC syntax of “…{@ A AND B}”, the DRC verifier 31 does not proceed with detection if there is no overlapping portion of the polygons A and B in the layout data D10. can Therefore, even if the number of DRC statements is very large, the LVS runtime may not be increased. In addition, in one embodiment, since the DRC verifier 31 performs DRC on the layout data D10 according to the DRC loop syntax, the task of describing and verifying by hand can be omitted, thereby reducing the development period of the integrated circuit. It can be shortened, and it is possible to detect missing polygons that are not defined as a derived layer.

Referring back to FIG. 3 , the LVS verifier 32 performs LVS verification that compares the layout data D10 with the schematic data D20 based on the rule file D30 and the DRC result data D40 to obtain the LVS result. Data D50 may be generated. Specifically, the LVS verifier 32 may extract a layout netlist from the layout data D10 based on the rule file D30 and the DRC result data D40. In addition, the LVS verifier 32 may generate the source netlist by compiling the schematic data D20. The LVS verifier 32 may then generate LVS result data D50 by comparing the layout netlist and the source netlist. The LVS result data D50 may include not only whether the layout data D10 and the schematic data D20 match or not match, but also information about a non-matching part. The designer may modify the layout data D10 or the schematic data D20 by referring to the LVS result data D50.

6 is a flowchart illustrating an LVS verification method for an integrated circuit according to an embodiment of the present disclosure.

Referring to FIG. 6 , the LVS verification method according to the present embodiment may correspond to, for example, an implementation example of step S150 of FIG. 1 . Accordingly, the contents described above with reference to FIGS. 1 to 5 may also be applied to the present embodiment, and a redundant description will be omitted. The LVS verification method may include steps S210, S230, and S250, and steps S210, S230, and S250 may be performed by a processor (eg, 110 of FIG. 2 ), respectively.

In step S210, a connection relationship between polygons is detected from the layout data based on the rule file including the DRC syntax. In an embodiment, the rule file may further include definitions for a plurality of layers included in the layout data and a plurality of polygons included in each of the plurality of layers. In one embodiment, the DRC syntax may be a DRC loop syntax implemented as a loop algorithm. According to the DRC loop syntax, a connection relationship may be detected for each of a plurality of layers included in the layout data and for each of a plurality of polygons included in each layer. For example, the DRC syntax may be implemented using a 'foreach loop'.

In step S230, the layout netlist is extracted from the layout data using the linkage relationship. In step S250, LVS verification is performed on the integrated circuit to generate LVS result data by comparing the layout netlist with the schematic data of the integrated circuit. In one embodiment, the method may further comprise compiling the source netlist from the schematic data, and the LVS verification may be performed by comparing the source netlist and the layout netlist. For example, in the LVS verification step, a connection relationship between polygons, double counting on parasitic components, short/open check, etc. may be performed using a loop algorithm.

7A illustrates an LVS operation according to an embodiment of the present disclosure, and FIG. 7B illustrates an LVS operation according to a comparative example of the present disclosure.

Referring to FIG. 7A , according to an embodiment, the connection relationship 72 of polygons is automatically detected by performing DRC on the layout data 71 based on the rule file, and the detected connection relationship 72 is used. Thus, by performing LVS verification, the layout data 73 for which LVS verification has been completed can be obtained. The layout data 71 includes first to fourth polygons 711 to 714 , and in the layout data 71 , the first and fourth polygons 711 and 714 are perpendicular to the third polygon 713 . , and the first and second polygons 711 and 712 may be vertically connected. Accordingly, the connection relationship 72 may include two connection relationships for polygons actually connected in the layout data 71 .

Referring to FIG. 7B , in the related art, a human, ie, a designer, describes a connection relationship 74 in text before generating layout data. For example, the connection relationship 74 was described using a 'CONNECT' function or a 'push_conn_stack' function. For example, the connection relationship 74 may be described as 'CONNECT A B BY V1', where 'CONNECT' is a function and A, B, and V1 are factors. As the number of factors increases in the integrated circuit due to the miniaturization process of the integrated circuit, the combination of factors increases exponentially, and thus, human error may continuously occur.

A net connection in an integrated circuit is made of wires, which may include metal layers and vias. During LVS verification, if the net connection is not accurately detected, it may be impossible to distinguish between short and open nets in the actual mask. However, in the past, such a decision was made by a human typing. According to the miniaturization of the process, since the physical relationship of the wires has reached a stage where the human eye can no longer identify it, a CAE (Computer Aided Engineering) level solution is required. According to embodiments of the present disclosure, human error is prevented by automatically detecting the connection relationship 72 of polygons from the layout data 71 in the DRC verification step and applying the detected connection relationship 72 to the LVS verification step. can do. Accordingly, it is possible to prevent a mask fail occurring due to an LVS verification error.

8 is a flowchart illustrating an LVS coding method according to an embodiment of the present disclosure.

Referring to FIG. 8 , the LVS coding method according to the present embodiment may correspond to a method of generating a rule file used for LVS verification. For example, the LVS coding method may be included in step S150 of FIG. 1 or may be performed before step S210 of FIG. 6 .

In step S310, an original layer is defined. In step S330, a derived layer is defined. The original layer may be classified into a plurality of derived layers, and the plurality of derived layers may correspond to a plurality of polygons. In an embodiment, the original layer may be divided into a plurality of derived layers based on a process basis including a concentration of an impurity or a thickness of a metal layer. In an embodiment, the original layer may be logically divided into a plurality of derived layers by coding. However, the present invention is not limited thereto, and the original layer may be divided into a plurality of derived layers according to various criteria.

In step S350, elements and parameters are defined. For example, the device may include PMOS, NMOS, and the like. The parameter may be a geometric parameter related to an electrical characteristic of the device, and may include, for example, a width and a length. In an embodiment, the LVS coding method may further include, after step S350, defining a comparison target between the layout data and the schematic data in the LVS verification step. In step S370, an ERC (Electrical Rule Check) is defined.

Conventionally, in the LVS coding process, the step of defining the connection relationship between steps S330 and S350 was performed, and the designer directly described the connection relationship before the layout data of the integrated circuit was generated. However, according to the present embodiment, the step of defining the connection relationship by the designer in the LVS coding process may be omitted, and accordingly, the rule file (eg, 51 in FIG. 5 ) may not include the connection relationship of polygons. can Accordingly, in the rule file according to embodiments of the present disclosure, coding related to a connection relationship may be omitted, and for example, a 'CONNECT' function or a 'push_conn_stack' may not be included.

9 is a block diagram illustrating an LVS engine 90 according to an embodiment of the present disclosure.

Referring to FIG. 9 , the LVS engine 90 may include an extractor 93 and a comparator 95 . The extractor 93 extracts the connection relationship of polygons from the layout data D10 based on the rule file D30, and the layout netlist ( D45) can be extracted. In one embodiment, the extractor 93 may be configured to include a DRC procedure configured to perform DRC on the layout data D10 according to the DRC syntax DS included in the rule file D30.

The comparator 95 may compare the layout netlist D45 with the schematic data D20 and, specifically, may compare parameters such as the connection state of the net, the number of elements, width and length, and the like. As a result of the comparison, if the layout netlist D45 and the schematic data D20 match, the comparator 95 may generate the LVS result data D50 including the path result. Meanwhile, if the layout netlist D45 and the schematic data D20 do not match, the comparator 95 may generate the LVS result data D50 including the fail result. In an embodiment, the LVS engine 90 may further include a compiler for generating a source netlist from the schematic data D20.

10 is a block diagram illustrating an LVS engine 90a according to an embodiment of the present disclosure.

Referring to FIG. 10 , the LVS engine 90a may include a design rule checker 91 , an extractor 93 , and a comparator 95 , and may correspond to a modified embodiment of the LVS engine 90 of FIG. 9 . . The design rule checker 91 automatically extracts the connection relationship of polygons by performing DRC on the layout data D10 according to the DRC syntax DS included in the rule file 30, and includes the extracted connection relationship. DRC result data D40 may be generated. The extractor 93 may extract the layout netlist D45 from the layout data D10 based on the extracted connection relationship and the rule file D30. The comparator 95 may generate the LVS result data D50 by comparing the layout netlist D45 with the schematic data D20.

11A shows an example 111 of a wiring structure included in a layout of an integrated circuit according to an embodiment of the present disclosure, and FIG. 11B shows a rule file 113 according to an embodiment of the present disclosure.

Referring to FIG. 11A , the wiring structure 111 may include a plurality of metal layers M1 to M5 and a plurality of vias V1 to V4 stacked in a vertical direction. Each of the vias V1 to V4 may electrically connect the metal layers M1 to M5 positioned in different layers. For example, the first via V1 is disposed between the first metal layer M1 and the second metal layer M2 to electrically connect the first metal layer M1 and the second metal layer M2. can be connected

Referring to FIG. 11B , the conventional rule file 112 may include four lines of 'CONNECT' phrases corresponding to the connection relationship of the wiring structure 111 described by the designer. Even when such a simple 'CONNECT' syntax is described, typos and omissions may occur during text typing. However, the rule file 113 according to an embodiment of the present disclosure may include DRC statements, and the DRC statements are connected to all layers and all polygons included in the wiring structure 111 using a loop algorithm. You can instruct it to automatically detect the relationship.

FIG. 12A shows another example 121 of a wiring structure included in a layout of an integrated circuit according to an embodiment of the present disclosure, and FIG. 12B shows a rule file 123 according to an embodiment of the present disclosure.

Referring to FIG. 12A , the wiring structure 112 includes a first metal layer M1, a first via layer V1, and a second metal layer M2 stacked in a vertical direction (eg, Z direction). may include The first metal layer M1 , the first via layer V1 , and the second metal layer M2 may each correspond to, for example, original layers defined in operation S310 of FIG. 8 . Each of the first metal layer M1 , the first via layer V1 , and the second metal layer M2 may be divided into a plurality of derivative layers in a horizontal direction (eg, an X direction or a Y direction). .

For example, the first metal layer M1 is divided into 7 derived layers corresponding to 7 polygons M1a to M1g, respectively, and the number of possible side connection relationships in the first metal layer M1 is 21 dog (ie, ₇ C ₂ ). For example, the first via layer V1 is divided into three derived layers respectively corresponding to the three polygons V1a to V1c, and the number of possible side connection relationships in the first via layer V1 is 3 dog (ie, ₃ C ₂ ). For example, the second metal layer M2 is divided into three derived layers corresponding to three polygons M2a to M2c, respectively, and the number of possible side connection relationships in the second metal layer M2 is 3 dog (ie, ₃ C ₂ ). Meanwhile, the number of possible vertical connection relationships in the first metal layer M1 , the first via layer V1 , and the second metal layer M2 may be 63 (ie, 3*3*7). Accordingly, the total number of possible connection relationships in the wiring structure 112 may correspond to 90.

Referring to FIG. 12B , the conventional rule file 122 may include 90 lines of 'CONNECT' phrases corresponding to the connection relationship of the wiring structure 121 described by the designer. Specifically, the rule file 122 has three lines of phrases 122a describing the lateral connectivity of the second metal layer M2, and three lines of phrases describing the lateral connectivity of the first via layer V1. 122b, 21-line phrases 122c describing lateral connection relationships of the first metal layer M1, and the first metal layer M1, the first via layer V1, and the second metal layer 63 lines of phrases 122d describing the vertical connections of (M2).

Meanwhile, the rule file 123 according to an embodiment of the present disclosure may include a first part 123a defining original layers and derived layers and a second part 123b including DRC phrases. The first portion 123a defines the first metal layer M1 , the first via layer V1 , and the second metal layer M2 as original layers, and uses the derivative layers of the first metal layer M1 as M1a . to M1g, derivative layers of the first via layer V1 may be defined as V1a to V1c, and derivative layers of the second metal layer M2 may be defined as M2a to M2c.

In the second part 123b, the DRC constructs may instruct to automatically detect a connection relationship for all layers and all polygons included in the wiring structure 121 using a loop algorithm. For example, the DRC constructs may include foreach Tool Command Language (Tcl), and accordingly, may instruct execution of DRC for derived layers included in each original layer. Accordingly, even if the number of polygons included in the layout data rapidly increases due to the miniaturization of the integrated circuit, all connection relationships between the polygons may be detected.

13 shows an example of a rule file 131 according to an embodiment of the present disclosure.

Referring to FIG. 13 , the rule file 131 may include a first part 131a defining original layers and derived layers, and a second part 131b including DRC phrases. The first part 131a may correspond to an example of the first part 123a of FIG. 12B , and the second part 131b may correspond to an example of the second part 123b of FIG. 12B . The DRC syntax included in the second part 131b may be implemented using a foreach loop, and accordingly, for all layers included in the layout data and all derived layers included in each layer, that is, polygons. Connections can be automatically detected.

14 illustrates an example of a DRC operation according to an embodiment of the present disclosure.

Referring to FIG. 14 , the layout data D10a includes first and second metal layers M1 and M2 and a first via V1 between the first and second metal layers M1 and M2 . can do. The design rule checker 91 may generate the DRC result data D40a by performing DRC on the layout data D10a according to the DRC syntax included in the rule file D30a. The rule file D30a may include, for example, a DRC syntax expressed as “… @ (M1 AND V1) AND M2”, and accordingly, the design rule checker 91 may use the first and A connection relationship between the second metal layers M1 and M2 and the first via V1 may be automatically detected.

The layout data D10a may include first to third nets N1 to N3 . Each of the first to third nets N1 to N3 may correspond to a vertical connection relationship in which the first and second metal layers M1 and M2 and the first via V1 are connected. Accordingly, the DRC result data D40a includes information that the total number of connections between the first and second metal layers M1 and M2 and the first via V1 detected in the layout data D10a is three. can do. The DRC result data D40a may be referred to as a DRC log file.

15 shows another example of a DRC operation according to an embodiment of the present disclosure.

Referring to FIG. 15 , the layout data D10b includes first and second metal layers M1 and M2 , and a first via V1 between the first and second metal layers M1 and M2 . can do. The design rule checker 91 may generate the DRC result data D40b by performing DRC on the layout data D10b according to the DRC syntax included in the rule file D30b. The rule file D30b may include, for example, a DRC syntax indicated by "... {@ (M1 AND V1) AND M2}", and accordingly, the design rule checker 91 receives the second order from the layout data D10b. A connection relationship between the first and second metal layers M1 and M2 may be automatically detected.

The layout data D10b may not include a vertical connection relationship between the first and second metal layers M1 and M2 and the first via V1 at all. Accordingly, the DRC result data D40b may include information that the total number of connection relationships between the detected first and second metal layers M1 and M2 and the first via V1 is zero. .

16 illustrates an example of a connection relationship detection operation by DRC according to an embodiment of the present disclosure.

Referring to FIG. 16 , the original layer is a first metal layer M1, and the first metal layer M1 includes first to third derived layers, that is, first to third polygons A, B, and C. ) can be distinguished. According to the layout data 161, the first and second polygons (A, B) are connected in a first direction (eg, X direction), and the first and third polygons (A, C) are the second It may be connected in two directions (eg, Y direction).

According to an embodiment, the rule file 161 includes a first part 162a defining an original layer, a second part 162b defining derived layers, and a third part 162c including a DRC syntax. can do. The third part 162c implements the DRC syntax as a loop algorithm using a foreach loop. Accordingly, DRC may be performed on each of the derived layers A to C included in the first metal layer M1 according to the DRC syntax included in the rule file 162 . The DRC result data 163 may include only "CONNECT A B" and "CONNECT C A", which are essential connection relationships of polygons actually connected in the layout data 161 .

17 illustrates an example of a connection relationship detection operation by DRC according to an embodiment of the present disclosure.

Referring to FIG. 17 , the original layer is a first metal layer M1, and the first metal layer M1 includes first to third derived layers, that is, first to third polygons A, B, and C. ) can be distinguished. According to the layout data 171 , the first and third polygons A and C may be connected in the second direction (eg, the Y direction).

According to an embodiment, the rule file 172 may be substantially the same as the rule file 162 of FIG. 16 . Accordingly, DRC may be performed on each of the derived layers A to C included in the first metal layer M1 according to the DRC syntax included in the rule file 172 . The DRC result data 173 may include only “CONNECT C A”, which is an essential connection relationship between polygons actually connected in the layout data 171 .

18 illustrates an example of a connection relationship detection operation by DRC according to an embodiment of the present disclosure.

Referring to FIG. 18 , the original layer is a first metal layer M1 , and the first metal layer M1 includes first to third derived layers, that is, first to third polygons A, B, and C. ) can be distinguished. According to the layout data 181 , the first and third polygons A and C may overlap in the second direction (eg, the Y direction). As such, when the first and third polygons A and C overlap, a parasitic component such as a parasitic resistance or a parasitic capacitance in the parasitic component extraction step (eg, step S190 of FIG. 1 ) for the overlap region is It can be duplicated and extracted. Accordingly, an error may occur in the parasitic component data, which may also cause an error in the timing analysis result of the integrated circuit. Therefore, it is necessary to detect the overlap area in the lateral connection relationship. However, according to the prior art, since the connection relationship is described before the creation of the layout, the overlap area cannot be predicted in advance, and thus, it is difficult to detect the overlap area.

According to an embodiment, the rule file 182 includes a first part 182a defining an original layer, a second part 182b defining derived layers, and a third part 182c including a DRC syntax. can do. For example, the third part 182c may include the DRC syntax "... {@ A AND C}", and the third part 182c may include "... {@ A AND B}" and "... {@ B AND C}" may be further included. For example, the DRC syntax in the third part 182c may be implemented as a DRC loop syntax using a loop algorithm. Accordingly, DRC may be performed on each of the derived layers A to C included in the first metal layer M1 according to the DRC syntax included in the rule file 182 . The DRC result data 183 may include only "OVERLAP AC", which is an essential connection relationship between polygons that actually overlap in the layout data 181 .

19 illustrates an example of a connection relationship detection operation by DRC according to an embodiment of the present disclosure.

Referring to FIG. 19 , the original layer is a first metal layer M1, and the first metal layer M1 is formed of first and second derived layers, that is, first and second polygons A and B. can be distinguished. According to the layout data 191 , the first polygon A may be connected to a third polygon C that is not divided into a derived layer. At this time, the third polygon (C) included in the first metal layer (M1) is omitted in the classification process for the first metal layer (M1), for example, it is not defined as a derived layer in step S330 of FIG. can According to the prior art, since the connection relationship is described before the generation of the layout, the connection relationship to the third polygon C that is not defined as the derived layer may not be predicted in advance.

According to an embodiment, the rule file 192 includes a first part 192a defining an original layer, a second part 192b defining derived layers, and a third part 192c including a DRC syntax. can do. For example, the third part 192c may include a DRC phrase of “… {@ M1 NOT A NOT B}”. Accordingly, by performing DRC on the layout data 191 according to the DRC syntax included in the rule file 192, polygons not defined as a derived layer in the first metal layer M1 are detected, and the first and DRC result data 193 including "CONNECT C A", which is a connection relationship between the third polygons, may be generated.

20A and 20B show examples of a connection relationship detection operation by DRC according to an embodiment of the present disclosure.

Referring to FIG. 20A , the layout data 201 may include a wiring structure 201a, in which the first port PORT1, the first contact CA, and the first metal are vertically stacked. It may include a layer M1. For example, when an input pin or an output pin connected to the first port PORT1 is implemented as a second metal layer on the first metal layer M1 , the wiring structure 201a is connected to the first port PORT1 . Since the second metal layer to be connected is not included, the wiring structure 201a may be a floating net.

If the rule file includes only the DRC syntax of “… {@ (PORT1 AND M1) AND CA}”, the floating net cannot be detected as a result of LVS verification for the layout data 201 . However, according to an embodiment, the rule file 202 limits the wiring structure such that two or more metal layers are disposed with respect to a specific port, for example, the first port PORT1 "... {@ ((PORT1). AND M1) AND CA) AND V1) AND M2}". Therefore, by performing DRC on the layout data 201 according to the DRC syntax included in the rule file 202, DRC result data 203 indicating that there are zero four or more metal layers satisfying the DRC syntax. can create

Referring to FIG. 20B , the layout data 204 may include a wiring structure 204a, wherein the wiring structure 204a includes a first port PORT1, a first contact CA, and a first metal stacked vertically. It may include a layer M1 , a via V1 , and a second metal layer M2 . For example, when the second metal layer M2 is implemented as an input pin or an output pin, the wiring structure 204a may be a normal net instead of a floating net. According to an embodiment, by performing DRC on the layout data 204 according to the DRC syntax included in the rule file 202, DRC indicating that there is one four of two or more metal layers satisfying the DRC syntax. Result data 205 may be generated.

21 illustrates an example of a connection relationship detection operation by DRC according to an embodiment of the present disclosure.

Referring to FIG. 21 , the layout data 211 may include a last metal layer LM, and the final metal layer LM may correspond to a pad. In the layout data 211 , when a via and a lower metal layer are not disposed under the final metal layer LM, the final metal layer LM may be a floating net.

Conventionally, the final metal layer LM can be described as a pad in the connection relationship described before the layout is created, and accordingly, the final metal layer LM cannot be detected as a floating net in the LVS verification step. However, according to one embodiment, the rule file contains a DRC syntax (eg, "… {@ (LM AND M1) AND V1") that restricts the wiring structure so that different metal layers are connected to a specific port, such as a pad. may include Accordingly, DRC result data 212 indicating that the final metal layer is a floating net may be generated by performing DRC on the layout data 211 according to the DRC syntax included in the rule file.

As described above with reference to FIGS. 1 to 21 , according to embodiments of the present disclosure, the DRC verification method may be applied to the LVS verification step. Accordingly, it is possible to reduce the possibility of omitting the connection relationship information in the LVS verification step of comparing the layout and the schematic. Specifically, according to embodiments, when patterns are connected during LVS verification but disconnected in a real mask, when patterns are disconnected during LVS verification but connected in a real mask, a conductor is present in LVS verification However, it is possible to detect all errors such as a case in which the conductor is present in the actual mask but not present in the actual mask in the LVS verification. Further, according to embodiments, the integrated circuit may also detect an error comprising a floating net.

22 is a flowchart schematically illustrating a method of manufacturing an integrated circuit according to an embodiment of the present disclosure.

Referring to FIG. 22 , a method of manufacturing an integrated circuit may be divided into an integrated circuit design and an integrated circuit manufacturing process. The design of the integrated circuit may include steps S410 and S430, and the manufacturing process of the integrated circuit may include steps S450 and S470. The integrated circuit manufacturing process is a step of manufacturing a semiconductor device according to the integrated circuit based on layout data, and may be performed in a semiconductor process module. The integrated circuit manufacturing method according to the present embodiment may manufacture the integrated circuit based on layout data generated by performing the integrated circuit design method described above with reference to FIGS. 1 to 21 .

In step S410, LVS verification is performed on the integrated circuit. Specifically, by performing DRC on the layout data based on the rule file including the DRC syntax, the connection relationship of polygons is automatically detected from the layout data, and the layout netlist is extracted from the layout data using the detected connection relationship, and , LVS verification is performed by comparing the layout netlist with the schematic data. Step S410 may correspond to S150 of FIG. 1 or steps S210 to S250 of FIG. 6 , and the embodiments described above with reference to FIGS. 1 to 21 may also be applied to this embodiment. In step S430, a parasitic component extraction operation is performed on the layout data for which the LVS verification is completed. Step S430 may correspond to S170 of FIG. 1 .

In step S450, a mask is produced based on the layout data. In an embodiment, layout data may be modified based on the parasitic component data generated in step S430, and a mask may be generated according to the modified layout data. Specifically, optical proximity correction (OPC) may be first performed based on layout data. OPC refers to a process of changing a layout by reflecting an error caused by an optical proximity effect. Subsequently, a mask may be manufactured according to a layout changed according to the result of performing OPC. In this case, the mask may be manufactured using a layout reflecting OPC, for example, GDSII reflecting OPC.

In step S470, an integrated circuit is manufactured using the mask. Specifically, various semiconductor processes are performed on a semiconductor substrate such as a wafer using a plurality of masks to form a semiconductor device in which an integrated circuit is implemented. For example, a process using a mask may mean a patterning process through a lithography process. A desired pattern may be formed on a semiconductor substrate or a material layer through such a patterning process. Meanwhile, the semiconductor process may include a deposition process, an etching process, an ion process, a cleaning process, and the like. In addition, the semiconductor process may include a packaging process of mounting a semiconductor device on a PCB and sealing the semiconductor device with a sealing material, or may include a test process of testing the semiconductor device or package.

23 is a flowchart specifically illustrating a method of manufacturing an integrated circuit according to an embodiment of the present disclosure.

Referring to FIG. 23 , in step S510, a connection relationship between polygons is detected from the layout data by performing DRC on the layout data of the integrated circuit, and a layout netlist is extracted. In one embodiment, the step of extracting the layout netlist includes detecting a connection relationship by performing DRC on the layout data based on a rule file including the DRC syntax, and layout from the layout data using the detected connection relationship. extracting the netlist. In step S530, LVS result data is generated by performing LVS verification on the layout netlist and schematic data. In step S550, parasitic component data is generated by extracting the parasitic component from the layout data. In some embodiments, step S550 may be omitted.

In step S570, an integrated circuit is manufactured according to the layout based on the layout data. In one embodiment, manufacturing the integrated circuit includes modifying layout data based on the LVS result data, manufacturing a mask according to the modified layout data, and manufacturing the integrated circuit using the mask. may include In one embodiment, manufacturing the integrated circuit includes modifying layout data based on the LVS result data and parasitic component data, fabricating a mask according to the modified layout data, and fabricating the integrated circuit using the mask. It may include a manufacturing step.

24 illustrates a computer-readable storage medium 1000 according to an embodiment of the present disclosure.

Referring to FIG. 24 , the storage medium 1000 includes schematic data 1100 of an integrated circuit, layout data 1200 of an integrated circuit, an LVS rule file 1300 , an LVS engine 1400 , and LVS result data 1500 . ) can be stored. The storage medium 1000 is a computer-readable storage medium and may include any storage medium that can be read by a computer while being used to provide instructions and/or data to a computer. For example, the computer-readable storage medium 1000 may include a magnetic or optical medium such as a disk, tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, RAM, and the like. , ROM, volatile or non-volatile memory such as flash memory, non-volatile memory accessible through a USB interface, microelectromechanical systems (MEMS), and the like. The computer-readable storage medium may be inserted into, integrated into, or coupled to the computer through a communication medium such as a network and/or a wireless link.

The schematic data 1100 of the integrated circuit may be data defining the integrated circuit. For example, the schematic data 1100 of the integrated circuit may be the schematic data illustrated by D20 of FIGS. 3 , 9 , 10 , or 42 of FIG. 4B . The layout data 1200 of the integrated circuit may include topological data for defining a structure of an integrated circuit manufactured through a semiconductor manufacturing process. For example, the layout data 1200 of the integrated circuit may include D10 in FIGS. 3, 9, and 10, 41 in FIG. 4A, 71 in FIG. 7A, 111 in FIG. 11A, 121 in FIG. 12A, D10a in FIG. 14, and D10a in FIG. 15 , 161 of FIG. 16 , 171 of FIG. 17 , 181 of FIG. 18 , 191 of FIG. 19 , 201 of FIG. 20A , 204 of FIG. 20B , or 211 of FIG. 21 may be layout data.

The LVS rule file 1300 is a file referenced by the LVS engine 1400 when performing LVS verification, and may define an element in order to recognize and extract the element from the layout data 1200 of the integrated circuit. In one embodiment, the LVS rule file 1300 may include a DRC syntax, and the DRC syntax may be implemented as a DRC loop syntax using a loop algorithm. For example, the DRC syntax may include foreach Tcl. For example, the LVS rule file 1300 is shown in Figs. 3, 9 and 10 D30, Fig. 5 51 , Fig. 11b 113 , Fig. 12b 123 , Fig. 13 131 , Fig. 14 D30a of Fig. 15 . It may be a rule file exemplified by D30b, 162 of FIG. 16, 172 of FIG. 17, 182 of FIG. 18, 192 of FIG. 19, or 202 of FIGS. 20A and 20B.

The LVS engine 1400 automatically detects the connection relation of polygons from the layout data 1200 of the integrated circuit based on the LVS rule file 1300, and uses the detected connection relation to the layout data 1200 of the integrated circuit. LVS result data 1500 may be generated by extracting the layout netlist and comparing the extracted layout netlist with the schematic data 1100 of the integrated circuit. For example, the LVS engine 1400 may be the LVS engine illustrated by 130c in FIG. 2 , 30 in FIG. 3 , 90 in FIG. 9 , or 90a in FIG. 10 .

The LVS engine 1400 may include a plurality of instructions for performing LVS verification, and the computing system or a processor included in the computing system executes the plurality of instructions included in the LVS engine 1400 to perform LVS verification. can In one embodiment, the LVS engine 1400 may include a design rule checker for performing DRC. In one embodiment, the storage medium 1000 may further store a DRC engine, which automatically detects a connection relationship of polygons from the layout data 1200 of the integrated circuit based on the LVS rule file 1300 to thereby DRC Result data can be generated.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure and not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

D10, D10a, D10b: Layout data, D20: Schematic data
D30, D30a, D30b: Rule file, D40, D40a, D40b: DRC result data
D45: Layout netlist, D50: LVS result data
M1, M2, M3, M4, M5: metal layers, V0, V1, V2, V3. V4: vias

Claims (20)

A computer-implemented method for designing an integrated circuit, comprising:
A rule file containing a DRC syntax including instructions for performing a Design Rule Check (DRC) on layers of layout data of an integrated circuit by executing a Layout-Versus-Schematic (LVS) engine by a processor automatically detecting connectivity of polygons from the layout data of the integrated circuit based on a rule file;
generating, by the processor, the LVS engine, a DRC result including one or more connection relationship information based on the detected connection relationship;
extracting a layout netlist from the layout data using the connection relationship detected based on the connection relationship information of the DRC result by executing the LVS engine by the processor; and
and executing, by the processor, the LVS engine, performing LVS verification on the layout netlist and the schematic data of the integrated circuit to generate LVS result data. According to claim 1,
The rule file, a plurality of layers included in the layout data, and a plurality of polygons included in each of the plurality of layers A computer implemented method, characterized in that it further comprises a definition (definition) for. 3. The method of claim 2,
The DRC syntax is a DRC loop syntax configured to check the connectivity for each of the plurality of layers and for each of the plurality of polygons. According to claim 1,
The layout data includes a first layer and a second layer on the first layer,
The DRC syntax includes a first syntax configured to check whether at least one first polygon included in the first layer and at least one second polygon included in the second layer are touched. How to implement a computer. According to claim 1,
The layout data includes a first layer, a via layer on the first layer, and a second layer on the via layer,
The DRC syntax determines whether at least one first polygon included in the first layer, at least one second polygon included in the second layer, and at least one third polygon included in the via layer is touched. and a second syntax configured to check. According to claim 1,
The layout data includes a first layer,
The DRC syntax includes a first syntax configured to check whether first and second polygons included in the first layer are touched. According to claim 1,
The layout data includes a first layer,
The DRC syntax includes a third syntax configured to check whether first and second polygons included in the first layer overlap. According to claim 1,
The detecting comprises performing DRC verification on the layout data according to the DRC syntax, thereby generating DRC result data including a connection relationship between polygons actually connected in the layout data. According to claim 1,
The layout data includes a first layer divided by at least one polygon,
wherein the DRC syntax includes a fourth syntax configured to check whether a polygon not defined as the at least one polygon exists on the first layer. 10. The method of claim 9,
The detecting comprises generating DRC result data including undefined polygons from the layout data by performing DRC verification on the layout data according to the fourth syntax. According to claim 1,
wherein the DRC syntax includes a fifth syntax configured to check for a floating net in the layout data. 12. The method of claim 11,
The detecting comprises generating DRC result data including the floating net from the layout data by performing DRC verification on the layout data according to the fifth syntax. According to claim 1,
The rule file is a computer implemented method, characterized in that the connection relationship of the polygons is omitted. According to claim 1,
and generating parasitic component data by extracting a parasitic component from the layout data for which the LVS verification has been completed. 15. The method of claim 14,
manufacturing a mask based on the layout data and the parasitic component data; and
and fabricating the integrated circuit using the mask. A method of manufacturing an integrated circuit comprising:
A rule file containing a DRC syntax including instructions for performing a Design Rule Check (DRC) on layers of layout data of an integrated circuit by executing a Layout-Versus-Schematic (LVS) engine by a processor automatically detecting connectivity of polygons from the layout data of the integrated circuit based on a rule file;
generating, by the processor, the LVS engine, a DRC result including one or more connection relationship information based on the detected connection relationship;
extracting a layout netlist from the layout data using the connection relationship detected based on the connection relationship information of the DRC result by executing the LVS engine by the processor;
performing, by the processor, the LVS engine, performing LVS verification on the layout netlist and the schematic data of the integrated circuit to generate LVS result data; and
manufacturing the integrated circuit according to a layout based on the layout data and the LVS result data. 17. The method of claim 16,
Manufacturing the integrated circuit comprises:
modifying, by the processor, the layout data based on the LVS result data;
manufacturing a mask according to the modified layout data; and
and fabricating the integrated circuit using the mask. 17. The method of claim 16,
and generating, by the processor, after generating the LVS result data, parasitic component data by extracting a parasitic component from the layout data. 19. The method of claim 18,
Manufacturing the integrated circuit comprises:
modifying, by the processor, the layout data based on the LVS result data and the parasitic component data;
manufacturing a mask according to the modified layout data; and
and fabricating the integrated circuit using the mask. A computing system for the design of an integrated circuit, comprising:
a memory for storing an LVS engine for performing Layout-Versus-Schematic (LVS) verification for the integrated circuit; and
a processor accessible to the memory and executing the LVS engine;
The LVS engine is
Based on a rule file including a DRC syntax including instructions for performing a Design Rule Check (DRC) on the layers of the layout data of the integrated circuit, the connection relation of polygons is automatically determined from the layout data of the integrated circuit. detect,
Generates a DRC result including one or more connection information based on the detected connection relationship,
extracting a layout netlist based on the connection information of the DRC result,
and comparing the extracted layout netlist with schematic data of the integrated circuit.

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