KR102644204B1 - Design Automation Method and System for CMOS Circuitry - Google Patents

Abstract

A CMOS-based circuit design automation method and system is presented. The CMOS-based circuit design automation method proposed in the present invention is a code-based final drawing using a template of an instance with guaranteed DRC (Design Rule Check) and a grid to be placed through CMOS circuit-based layout automation. It includes a step of generating and measuring specification values for the circuit by conducting post simulation based on the layout information of the generated drawing.

Description

CMOS-based circuit design automation method and system {Design Automation Method and System for CMOS Circuitry}

The present invention relates to a CMOS-based circuit design automation method and system.

The semiconductor circuit design process is largely divided into two categories: front-end (Logical Design) and back-end (Physical Design). Among the two categories, physical design is carried out in the back-end process. A verification process is underway for the completed design, and the time required for this process has increased significantly. The reason is that the design rules are very strict and unintuitive. Therefore, in order to create a drawing that satisfies this rule, the designer must go through a process of designing complex layout and wiring and ultimately design it to satisfy the design rule. This circuit design process takes a lot of time, which reduces the designer's ability to research new system architectures. In other words, the increase in design time in the back-end process is a very critical problem in the current semiconductor design process. To improve this, a layout design automation system using Python is needed to design a layout that guarantees design rules.

[1] Jaeduk Han "Laygo: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies", IEEE Transactions on Circuits and Systems-1: Regular Papers, VOL. 68, NO. 3, MARCH 2021 [2] Eric Chang "BAG2: A Process-Portable Framework for Generator-Based AMS Circuit Design"

The technical problem to be achieved by the present invention is a Python code-based layout design automation method and method using a template that guarantees design rules and grid-based arrangement and wiring in an abstract coordinate system. The goal is to provide a system.

In one aspect, the CMOS-based circuit design automation method proposed in the present invention is a code using a template of an instance where DRC (Design Rule Check) is guaranteed through CMOS circuit-based layout automation and a grid to be placed. It includes the step of generating a final drawing and performing post simulation based on the layout information of the generated drawing to measure specification values for the circuit.

The step of creating a code-based final drawing using a template of an instance with guaranteed DRC (Design Rule Check) and a grid to be placed through the CMOS circuit-based layout automation is the layout of the code-based final drawing. To create an abstract coordinate system that represents the values of the physical coordinate system, which is a coordinate system that is not affected by process and device parameters and abstracts and represents specific values rather than actual values, is used.

The step of creating a code-based final drawing using a template of an instance where DRC (Design Rule Check) is guaranteed through the CMOS circuit-based layout automation and a grid to be placed includes loading the template and grid. Create an instance, write an instance creation and placement code, write a function to create a wire and route it to a designated location, create a pin on the corresponding metal, and extract the written code into a layout file.

The step of measuring specification values for the circuit by performing post simulation based on the layout information of the generated drawing is a template and grid-based arrangement with guaranteed DRC for each instance of the layout of the generated final drawing. and wiring process can result in time reduction in the verification process during post-simulation.

In another aspect, the CMOS-based circuit design automation system proposed in the present invention utilizes a template of an instance where DRC (Design Rule Check) is guaranteed and a grid to be placed through CMOS circuit-based layout automation. It includes a circuit design unit that generates a final drawing based on one code, and a simulation performance unit that performs post simulation based on layout information of the generated drawing to measure specification values for the circuit.

According to embodiments of the present invention, code-based design using a template of an abstract instance with guaranteed DRC (Design Rule Check) and a grid to be placed through layout automation of a CMOS circuit-based D flip-flop Final drawing can be designed. Post simulation can be performed based on the layout information of the designed drawing to measure timing specification values. Based on this, the area obtained through the drawing of the directly designed layout or simulation obtained through the layout information Analyze the performance of the automation system by comparing the values.

1 is a diagram for explaining the configuration of a CMOS-based circuit design automation system according to an embodiment of the present invention.
Figure 2 is a flowchart illustrating a method for automating CMOS-based circuit design according to an embodiment of the present invention.
Figure 3 is a diagram showing a transmission gate-based D flip-flop according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating instance arrangement based on relative positions according to an embodiment of the present invention.
Figure 5 is a diagram showing instance P-type and N-type transistors with guaranteed DRC according to an embodiment of the present invention.
Figure 6 is a diagram showing a layout generated from a CMOS-based circuit design automation system according to an embodiment of the present invention.
Figure 7 is a diagram showing the D_FF layout designed according to the prior art.

In most cases, the layout's DRC (Design Rule Check) verification process is a critical factor that increases the design time of circuit designers. To improve these problems, we propose a Python code-based layout design automation system using a template that guarantees design rules and grid-based placement and wiring in an abstract coordinate system. .

Using this method, the layout of the Transmission Gate D flip-flop is created directly by designing a Python-based code in Cadence Virtuoso Tool, and the DRC of the layout designed by the tool is checked. In addition, the performance of the layout created based on the automated system can be checked by comparing the area through code-based layout drawings and directly created layout drawings, or by comparing timing specification values by performing post simulation. do. Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a diagram illustrating the configuration of a CMOS-based circuit design automation system according to an embodiment of the present invention.

The CMOS-based circuit design automation system 100 according to this embodiment may include a processor 110, a bus 120, a network interface 130, a memory 140, and a database 150. The memory 140 may include an operating system 141 and a CMOS-based circuit design automation routine 142. The processor 110 may include a circuit design unit 111 and a simulation performance unit 112. In other embodiments, the CMOS-based circuit design automation system 100 may include more components than those of FIG. 1 . However, there is no need to clearly show most prior art components. For example, the CMOS-based circuit design automation system 100 may include other components such as a display or transceiver.

The memory 140 is a computer-readable recording medium and may include a non-permanent mass storage device such as random access memory (RAM), read only memory (ROM), and a disk drive. Additionally, program codes for an operating system 141 and a CMOS-based circuit design automation routine 142 may be stored in the memory 140. These software components may be loaded from a computer-readable recording medium separate from the memory 140 using a drive mechanism (not shown). Such separate computer-readable recording media may include computer-readable recording media (not shown) such as floppy drives, disks, tapes, DVD/CD-ROM drives, and memory cards. In another embodiment, software components may be loaded into the memory 140 through the network interface 130 rather than a computer-readable recording medium.

Bus 120 may enable communication and data transfer between components of CMOS-based circuit design automation system 100. Bus 120 may be configured using a high-speed serial bus, parallel bus, storage area network (SAN), and/or other suitable communication technology.

The network interface 130 may be a computer hardware component for connecting the CMOS-based circuit design automation system 100 to a computer network. The network interface 130 can connect the CMOS-based circuit design automation system 100 to a computer network through a wireless or wired connection.

The database 150 may serve to store and maintain all information necessary for automation of CMOS-based circuit design. In Figure 1, it is shown that the database 150 is built and included inside the CMOS-based circuit design automation system 100, but it is not limited to this and may be omitted depending on the system implementation method or environment, or may be added in whole or in part. It is also possible for the database to exist as an external database built on another, separate system.

The processor 110 may be configured to process instructions of a computer program by performing basic arithmetic, logic, and input/output operations of the CMOS-based circuit design automation system 100. Commands may be provided to processor 110 by memory 140 or network interface 130 and via bus 120. The processor 110 may be configured to execute program codes for the circuit design unit 111 and the simulation performance unit 112. These program codes may be stored in a recording device such as memory 140.

The circuit design unit 111 and the simulation performance unit 112 may be configured to perform steps 210 to 210 of FIG. 2 .

The CMOS-based circuit design automation system 100 may include a circuit design unit 111 and a simulation performance unit 112.

The circuit design unit 111 generates a code-based final drawing using a template of an instance with guaranteed DRC (Design Rule Check) and a grid to be placed through CMOS circuit-based layout automation.

The circuit design unit 111 uses an abstract coordinate system that represents the values of the physical coordinate system, which is a coordinate system that is not affected by process and device parameters and represents abstract values rather than actual values, in order to create the layout of the code-based final drawing. Use it.

The circuit design unit 111 creates a load of the template and grid, writes an instance creation and placement code, creates a function to create a wire and routes it to a designated location, creates a pin on the corresponding metal, and writes the written code. Extract it as a layout file.

The simulation performance unit 112 can reduce the time in the verification process when performing post-simulation through a template and grid-based arrangement and wiring process with DRC guaranteed for each instance of the layout of the generated final drawing.

Figure 2 is a flowchart illustrating a CMOS-based circuit design automation method according to an embodiment of the present invention.

The proposed CMOS-based circuit design automation method generates a code-based final drawing using a template of an instance with guaranteed DRC (Design Rule Check) and a grid to be placed through CMOS circuit-based layout automation. It may include (210) and a step (220) of measuring specification values for the circuit by performing post simulation based on the layout information of the generated drawing.

In step 210, a code-based final drawing is generated using a template of an instance where DRC (Design Rule Check) is guaranteed and a grid to be placed through CMOS circuit-based layout automation.

According to an embodiment of the present invention, the circuit design unit is a coordinate system that is not affected by process and device parameters to generate the layout of the code-based final drawing, and the value of the physical coordinate system, which is a coordinate system that abstracts and represents specific values rather than actual values. An abstract coordinate system representing is used.

According to an embodiment of the present invention, the circuit design unit creates the template and the load of the grid, writes an instance creation and placement code, creates a function to create a wire and route it to a designated location, and creates a pin on the corresponding metal. And extract the written code into a layout file.

In step 220, post simulation is performed based on the layout information of the generated drawing to measure specification values for the circuit (220).

According to an embodiment of the present invention, the simulation performance unit will achieve the effect of reducing time in the verification process during post-simulation through a template and grid-based arrangement and wiring process with guaranteed DRC for each instance of the layout of the generated final drawing. You can.

Figure 3 is a diagram showing a transmission gate-based D flip-flop according to an embodiment of the present invention.

In the present invention, the layout of a Transmission Gate D flip-flop, a type of popular flip-flop, is designed using Cadence Virtuoso Tool and a 28nm process. First, for design purposes, the schematic of the flip-flop can be shown as shown in Figure 3. The above schematic consists of a total of 3 instances: Inverter, Transmission Gate, and Tri-State Inverter, which each have 1 P-type and 1 N-type transistor. It consists of 1, 1, and 2 pieces. The layout is designed in the back-end process based on the node location and instance configuration type of this circuit.

FIG. 4 is a diagram illustrating instance arrangement based on relative positions according to an embodiment of the present invention.

In order to design the layout, a template must first be created according to the DRC of the 28nm process, and the arrangement and wiring process based on the grid of this process must be set to proceed. Since the design rules required for each process are different, in order to create a template and grid suitable for the 28nm process, a sample that can be applied to any process must first be created and applied.

And since it is code-based layout creation, it becomes easier to apply if you use a method to briefly express the values of the physical coordinate system. This is the use of an abstract coordinate system. An abstract coordinate system is a coordinate system that is not affected by process and device parameters and is a coordinate system that abstracts and represents specific values rather than actual values. It has the advantage of being able to change to an appropriate value when converting the value to the actual coordinate system even without using a unique value, increasing reusability and portability when creating a code-based layout. By applying the abstract coordinate system, you can place templates based on their relative positions. As shown in Figure 4, when placing a template for the first time, if it is placed at the origin based on an abstract coordinate system, the instances used in the layout can be moved in various directions by using position movement functions defined in the Python module for various templates based on the placement. It can be moved. This has the advantage of maximizing the process portability of the code and allowing rapid progress using the code when deploying many instances.

The next grid is a coordinate system formed using an abstract coordinate system, and based on this, wiring work is carried out using various metals. Similarly, if this work is implemented as code using wiring-related functions in Python module functions, process portability increases.

Figure 5 is a diagram showing instance P-type and N-type transistors with guaranteed DRC according to an embodiment of the present invention.

In the present invention, an abstract coordinate system is introduced to use templates and grids in code, and a final template to be used must be created. First, to implement one instance, design a layout of various elements used as basics according to the corresponding DRC and combine them to create a new template. A typically used instance will be a transistor, and since it is a combination of templates with guaranteed DRC, this instance will also have guaranteed DRC, which has a significant impact on reducing the time in the verification process when creating the final layout. Figure 5 shows P-type and N-type transistors with guaranteed DRC.

To create a code-based layout, code must be written and designed using a Python-based grammar.

According to an embodiment of the present invention, first, a template and grid load for the 28nm process are created, and instance creation and placement code are written. Afterwards, write a function to create a wire and route it to a designated location, and extract the pin creation and written code to the corresponding metal as a layout file.

At this time, the code used in Python is used, but in the process of forming the structure, a user-set function used when performing grid-based placement and wiring is also used. The transmission gate D_FF layout writes code based on the information from the previously designed schematic.

Information to consider include the number of instances, the point on the node to route to, and the I/0 and pin names that match the schematic.

Figure 6 is a diagram showing a layout generated from a CMOS-based circuit design automation system according to an embodiment of the present invention.

In the code, functions are used to create and place pre-created instances, and in the code, metals are used to route each node that matches the schematic. The final designed layout can be output as shown in Figure 6 by having Virtuoso output the code in an appropriate format and executing the final Python file.

Looking at the final layout according to an embodiment of the present invention, it can be seen that each instance is a template with guaranteed DRC, and the grid-based placement and wiring process is also designed in consideration of the 28nm process rule. Through this, many factors to be considered during the verification process are eliminated, resulting in a significant reduction in time.

Figure 7 is a diagram showing the D_FF layout designed according to the prior art.

As shown in Figure 6, the layout was created based on the code, and it has an area of 4.87㎛ * 2.815㎛ = 13.71㎡. Post simulation was performed using Hspice based on the information of this layout. There are three measured values: Setup time, Hold time, and Clk-to-Q delay time, and the values are measured after simulation using appropriate instance and node values. did. The post-simulation values of the code-based layout were confirmed to be 16.58ps, 10.53ps, and 25.94ps, respectively.

In order to compare with the layout designed by the automated system, the optimized layout through manual design was designed and measured as shown in Figure 7. The measurement results are as follows. Table 1 summarizes the layout area and simulation values of FIGS. 6 and 7.

<Table 1>

In the present invention, Python was used to set up a module that creates templates and grids to be used in layout, and based on the module, an instance that passed DRC, a physical constraint, was created as a dictionary. After that, the instance was placed and the placement and wiring process was performed using various functions and metals in the module, ultimately creating a code-based layout, which was designed to ensure DRC on the Cadence Virtuoso Tool. However, it can be seen from the table that the layout designed to be guaranteed by DRC has a much larger area than the layout designed directly. This is due to code-based layout limitations where instance placement is based on relative position, so the diffusion area cannot be shared and must be placed only as a single unit. Therefore, the automated design system has the advantage of quickly omitting the verification process when laying out many circuits and increasing reusability and portability, but the disadvantage of being weak for use in layout fields that require the use of a minimized area can be measured through tables. It was confirmed by the results. The process of correcting minor DRC errors in the many instances and routing processes in the physical design process takes a lot of time to form the final drawing. Therefore, this layout automation method using Python programming saves a lot of time during the design process with DRC guaranteed during the verification process, and fatigue of circuit designers is also reduced compared to before, enabling the development of more ingenious system architecture.

The device described above may be implemented with hardware components, software components, and/or a combination of hardware components and software components. For example, devices and components described in embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), etc. , may be implemented using one or more general-purpose or special-purpose computers, such as a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. A processing device may execute an operating system (OS) and one or more software applications that run on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a single processing device may be described as being used; however, those skilled in the art will understand that a processing device includes multiple processing elements and/or multiple types of processing elements. It can be seen that it may include. For example, a processing device may include a plurality of processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing unit to operate as desired, or may be processed independently or collectively. You can command the device. Software and/or data may be used on any type of machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. It can be embodied in . Software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., singly or in combination. Program instructions recorded on the medium may be specially designed and configured for the embodiment or may be known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. -Includes optical media (magneto-optical media) and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, etc. Examples of program instructions include machine language code, such as that produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (8)

A step where the circuit design department generates a code-based final drawing using a template of an instance with guaranteed DRC (Design Rule Check) and a grid to be placed through CMOS circuit-based layout automation; and
A step in which the simulation performance unit performs post simulation based on the layout information of the generated drawing to measure specification values for the circuit.
Including,
The step of the circuit design department generating a code-based final drawing using a template of an instance where DRC (Design Rule Check) is guaranteed through CMOS circuit-based layout automation and a grid to be placed is,
To create the layout of the code-based final drawing, an abstract coordinate system is used that represents the values of the physical coordinate system, which is a coordinate system that is not affected by process and device parameters and represents abstracted specific values rather than actual values.
When converting a value to a real coordinate system using an abstract coordinate system instead of using the value of a unique physical coordinate system, it is changed to a value according to the process and device parameters, increasing reusability and portability when creating a code-based layout.
The grid is a coordinate system formed by using an abstract coordinate system, and when placing a template by applying the abstract coordinate system, arrangement is performed based on the relative position.
A method for automating CMOS-based circuit design. delete According to paragraph 1,
The step of the circuit design department generating a code-based final drawing using a template of an instance where DRC (Design Rule Check) is guaranteed through CMOS circuit-based layout automation and a grid to be placed is,
Create a load of the above template and grid, write an instance creation and placement code, write a function to create a wire and route it to a designated location, create a pin in the corresponding metal, and extract the written code into a layout file.
A method for automating CMOS-based circuit design. According to paragraph 1,
The step of the simulation performing unit performing post simulation based on the layout information of the generated drawing to measure specification values for the circuit,
The DRC-guaranteed template and grid-based arrangement and wiring process for each instance of the final drawing layout created above results in time reduction in the verification process during post-simulation.
A method for automating CMOS-based circuit design. A circuit design department that creates code-based final drawings using templates of instances with guaranteed DRC (Design Rule Check) and a grid to be placed through CMOS circuit-based layout automation; and
A simulation performance unit that performs post simulation based on the layout information of the generated drawing and measures specification values for the circuit.
Including,
The circuit design department,
To create the layout of the code-based final drawing, an abstract coordinate system is used that represents the values of the physical coordinate system, which is a coordinate system that is not affected by process and device parameters and represents abstracted specific values rather than actual values.
When converting a value to a real coordinate system using an abstract coordinate system instead of using the value of a unique physical coordinate system, it is changed to a value according to the process and device parameters, increasing reusability and portability when creating a code-based layout.
The grid is a coordinate system formed by using an abstract coordinate system, and by applying the abstract coordinate system, placement is performed based on the relative position when placing the template.
CMOS-based circuit design automation system. delete According to clause 5,
The circuit design department,
Create a load of the above template and grid, write an instance creation and placement code, write a function to create a wire and route it to a designated location, create a pin in the corresponding metal, and extract the written code into a layout file.
CMOS-based circuit design automation system. According to clause 5,
The simulation performance unit,
The DRC-guaranteed template and grid-based arrangement and wiring process for each instance of the final drawing layout created above results in time reduction in the verification process during post-simulation.
CMOS-based circuit design automation system.