JP2011170771A - Semiconductor integrated circuit and timing adjusting method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that it takes much man-hours to adjust timing in a semiconductor integrated circuit of a conventional technology. <P>SOLUTION: The semiconductor integrated circuit includes: logic cell groups 11 to 15 in which circuit blocks which are individually arranged correspondingly to a plurality of signal lines connected to an external memory to determine the timing of the corresponding signal lines are magnified; and IO buffers 21 to 26 which are provided correspondingly to the logic cell groups 11 to 15. Pieces of wiring connecting the logic cell groups 11 to 15 to the corresponding IO buffers 21 to 26 has the approximately same lengths. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a timing adjustment method thereof.

  In a semiconductor memory including a DRAM (Synchronous Dynamic Random Access Memory), there is a demand for an increase in data capacity and an improvement in data transfer speed. As one of DRAMs whose data transfer speed has been increased, DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory) can be cited. In the DDR-SDRAM, data transfer is possible in synchronization with both rising and falling of the clock, so that it is possible to realize a data throughput more than twice that of the conventional SDRAM.

  The operation of an interface circuit that interfaces with a DDR-SDRAM is disclosed in Patent Document 1. A DDR-SDRAM interface circuit (hereinafter simply referred to as an interface circuit) disclosed in Patent Document 1 includes a clock generation circuit, an output buffer, an input buffer, a DLL (Delay Locked Loop) circuit, and a first delay circuit. And a timing control circuit. The first delay circuit includes a first delay buffer and a second delay buffer. The timing adjustment circuit has two FFs (Flip Flops).

  The clock generation circuit generates an internal clock signal and outputs it to the first delay circuit. At the same time, the clock generation circuit generates a memory clock signal and outputs it to the DDR-SDRAM via the output buffer. The DDR-SDRAM generates a data strobe signal and a data signal based on the memory clock signal generated by the interface circuit, and outputs it to the interface circuit.

  In the interface circuit, the data strobe signal is input to the DLL circuit via the input buffer. Then, the DLL circuit generates a delayed data strobe signal obtained by delaying the phase of the data strobe signal by 90 °. In the interface circuit, the data signal is input to one FF via another input buffer. One FF takes in the data signal in synchronization with the delayed data strobe signal and outputs it to the other FF. That is, one FF samples the data signal with the delayed data strobe signal.

  The first delay circuit gives a delay time to the internal clock signal and outputs a delayed internal clock signal. The other FF takes in the data signal sampled by one FF in synchronization with the delayed internal clock signal and outputs it to the internal circuit at the subsequent stage. In this way, the interface circuit changes the clock of the data signal generated by the DDR-SDRAM.

  Here, the first and second delay buffers provided in the first delay circuit have the same configuration as the output buffer and the input buffer used for amplification of the data strobe signal. Therefore, the interface circuit can suppress a variation in delay time between the delayed data strobe signal and the delayed internal clock signal, and can stably capture data.

JP 2008-210307 A

  In communication between an interface circuit (semiconductor device) that requires high-speed processing and a memory, in order to adjust the AC timing, a logic cell used in the interface circuit is associated with a corresponding IO buffer (input buffer and It is necessary to take measures such as suppressing wiring delay errors by arranging them in the vicinity of the output buffer. However, the interface circuit is generally designed through RTL design, logic synthesis, layout design, and STA (Static Timing Analysis) processes. Therefore, when the AC timing is adjusted in the prior art, there is a problem that it takes man-hours such as selecting a target logic cell from a net list generated after logic synthesis and arranging it in the vicinity of the corresponding IO buffer. It was.

  The semiconductor integrated circuit according to the present invention includes a hard macro in which a circuit block that is individually provided corresponding to a plurality of signal lines connected to an external memory and determines the timing of the corresponding signal line is made into a macro, and the hard macro Each of the wirings that connect the hard macro and the corresponding IO buffer have substantially the same length.

  Another aspect of the semiconductor integrated circuit according to the present invention is arranged in the vicinity of the first IO buffer, coupled to the first IO buffer via a first wiring, and based on the first clock signal. A first hard macro that outputs the generated reference clock via the first IO buffer and a second hard buffer arranged near the second IO buffer and coupled to the second IO buffer via a second wiring A second hard macro that outputs the input control signal via the second IO buffer in synchronization with the first clock signal; and a second hard macro that is disposed in the vicinity of the third IO buffer and the second IO macro. A third hard macro coupled to the third IO buffer via the third wiring and adding a predetermined delay to the strobe signal input via the third IO buffer; And a fourth hard macro that is coupled to the fourth IO buffer via a fourth wiring and transmits / receives a data signal via the fourth IO buffer. The first to fourth wirings have substantially the same length.

  A method of adjusting a timing of a semiconductor integrated circuit according to the present invention is coupled to a first IO buffer via a first wiring, and generates a reference clock generated based on a first clock signal via the first IO buffer. The first hard macro to be output and the second IO buffer are coupled to the second IO buffer via the second wiring, and the input control signal is synchronized with the first clock signal via the second IO buffer. And a second hard macro that outputs the third strobe signal coupled to the third IO buffer via a third wiring, and adds a predetermined delay to the strobe signal input via the third IO buffer. A semiconductor integrated circuit comprising: a hard macro; and a fourth hard macro coupled to the fourth IO buffer via a fourth wiring and transmitting / receiving a data signal via the fourth IO buffer. A timing adjustment method, characterized in that the length of the first to fourth wiring disposing the first through fourth hard macro to be the same.

  With the circuit configuration and timing adjustment method as described above, timing adjustment can be easily performed even when high-speed processing is required.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of easily adjusting timing even when high-speed processing is required, and a timing adjusting method thereof.

1 is a diagram showing a semiconductor integrated circuit according to a first exemplary embodiment of the present invention. It is a figure which shows IO buffer concerning Embodiment 1 of this invention. 1 is a diagram showing a logic cell group 11 according to a first exemplary embodiment of the present invention. It is a figure which shows the logic cell group 12 concerning Embodiment 1 of this invention. It is a figure which shows the logic cell group 13 concerning Embodiment 1 of this invention. It is a figure which shows the logic cell group 14 concerning Embodiment 1 of this invention. 3 is a diagram showing a logic cell group 15 according to the first exemplary embodiment of the present invention. FIG. 3 is a timing chart showing an operation of the semiconductor integrated circuit according to the first exemplary embodiment of the present invention. 3 is a timing chart showing an operation of the semiconductor integrated circuit according to the first exemplary embodiment of the present invention. 1 is a diagram showing a layout configuration of a semiconductor integrated circuit according to a first exemplary embodiment of the present invention; 7 is a timing chart showing an operation of the semiconductor integrated circuit according to the second exemplary embodiment of the present invention. 7 is a timing chart showing an operation of the semiconductor integrated circuit according to the second exemplary embodiment of the present invention. It is a figure which shows the relationship between the total value of internal delay time and external delay time, the frequency of the clock signal CK1, and CLK mode. It is a figure which shows the relationship between the total value of internal delay time and external delay time, the frequency of the clock signal CK1, and CLK mode.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. For clarity of explanation, duplicate explanation is omitted as necessary.

Embodiment 1
FIG. 1 shows a semiconductor device (semiconductor integrated circuit) 100 according to an embodiment of the present invention. The semiconductor device 100 transmits / receives data to / from the memory 200. In the present embodiment, a case where the memory 200 is a DDR-SDRAM will be described as an example.

  The semiconductor device 100 includes an arithmetic processing circuit 1, a memory controller 2, a PLL (Phase Locked Loop) 3, a frequency dividing circuit 4, a logic cell group (second hard macro) 11, and a logic cell group (first Hard macro) 12, logic cell group (fourth hard macro) 13, logic cell group (third hard macro) 14, logic cell group 15, delay adjustment circuit 16, and IO buffer (second buffer). , An IO buffer (first IO buffer) 22, 23, an IO buffer (fourth IO buffer) 24, an IO buffer (third IO buffer) 25, an IO buffer 26, Is provided. Further, the memory controller 2 has a timing adjustment circuit 5.

  FIG. 2 shows a circuit configuration of the IO buffer 21. The IO buffers 21 to 26 have the same circuit configuration. 3 to 7 show circuit configurations of the logic cell groups 11 to 15, respectively. The logic cell group 11 includes FFs (Flip Flops) 101 and 102. The logic cell group 12 includes a delay adjustment circuit 201 and an inverter 202. The logic cell group 13 includes FFs 301 to 309, selectors 310 to 312, and an AND logic gate (hereinafter simply referred to as AND) 313. The logic cell group 14 includes FFs 401 to 404, an AND 405, a delay adjustment circuit 406, and a delay adjustment circuit 407. The logic cell group 15 includes FFs 501 to 503 and a selector 504.

  In this embodiment, the semiconductor device 100 includes a 1-bit clock signal CK and CKB, a 17-bit control signal CM, a 32-bit write data DQ1, and a 4-bit write strobe. A case where the signal DQS1 and the 4-bit width permission signal DQM are output to the memory 200 will be described as an example. In the present embodiment, a case where the memory 200 outputs the read data DQ2 having a 32-bit width and the read strobe signal DQS2 having a 4-bit width to the semiconductor device 100 will be described as an example. In this embodiment, a case where the burst length of data is 8 bursts will be described as an example.

  First, the circuit configuration of the semiconductor device 100 will be described. The arithmetic processing circuit 1 and the memory controller 2 are connected to each other via a transmission / reception line. The output terminal of the PLL 3 is connected to the input terminal of the frequency dividing circuit 4. One output terminal of the frequency dividing circuit 4 is connected to the clock input terminal of the memory controller 2 and the logic cell groups 11 to 14. The other output terminal of the frequency dividing circuit 4 is connected to the logic cell groups 13 and 15 via the delay adjusting circuit 16.

  A control signal output terminal of the memory controller 2 is connected to the logic cell group 11. A data output terminal and a data input terminal of the memory controller 2 are connected to the logic cell group 13. The valid signal output terminal of the memory controller 2 is connected to the logic cell group 13. The mask signal output terminal of the memory controller 2 is connected to the logic cell group 14. The permission signal output terminal of the memory controller 2 is connected to the logic cell group 15.

  The logic cell group 11 is further connected to the I / O buffer 21. The logic cell group 12 is further connected to the I / O buffers 22 and 23. Logic cell group 13 is further connected to IO buffer 24. Logic cell group 14 is further connected to IO buffer 25. Logic cell group 15 is further connected to IO buffer 26.

  The IO buffers 21 to 26 are used as any of an input buffer, an output buffer, and an input / output buffer, respectively. As illustrated in FIG. 2, the IO buffers 21 to 26 include a three-state buffer 701 for an output buffer and a buffer 702 for an input buffer. In the IO buffers 21 to 26, the output terminal of the three-state buffer 701 is connected to the external connection terminal and to the input terminal of the buffer 702. When the IO buffers 21 to 26 are used as output buffers, the three-state buffer 701 is controlled to output the input signal as it is.

  The circuit configuration of the logic cell groups 11 to 16 will be described. FIG. 3 shows a block diagram of the logic cell group 11. The logic cell group 11 is a circuit block that detects the reference control signal PCM output from the memory controller 2 in synchronization with the clock signal CK1 and outputs it as a control signal CM. In the logic cell group 11, the data input terminal of the FF 101 is connected to the control signal output terminal of the memory controller 2. The clock input terminal of the FF 101 is connected to one output terminal of the frequency dividing circuit 4. The data output terminal of the FF 101 is connected to the data input terminal of the FF 102. The clock input terminal of the FF 102 is connected to one output terminal of the frequency dividing circuit 4. A data output terminal of the FF 102 is connected to an input terminal of a three-state buffer 701 provided in the IO buffer 21. Thus, the FFs 101 and 102 constitute a shift register.

  FIG. 4 shows a block diagram of the logic cell group 12. The logic cell group 12 is a circuit block that generates a two-phase differential clock (clock signals CK and CKB) based on the clock signal CK1. Although not shown in FIG. 1, the semiconductor device 100 is provided with a number of logic cell groups 11 and IO buffers 21 corresponding to the bit width of the control signal CM. In this embodiment, since the bit width of the control signal CM is 17 bits, 17 logic cell groups 11 and 17 IO buffers 21 are provided.

  In the logic cell group 12, the input terminal of the delay adjustment circuit 201 is connected to one output terminal of the frequency divider circuit 4. The output terminal of the delay adjustment circuit 201 is connected to the input terminal of a three-state buffer 701 provided in the IO buffer 22. Further, the output terminal of the delay adjustment circuit 201 is connected to the input terminal of a three-state buffer 701 provided in the IO buffer 23 via the inverter 202.

  FIG. 5 shows a block diagram of the logic cell group 13. The logic cell group 13 is a circuit block that is coupled to a data bus such as the memory 200 via the IO buffer 24 and transmits / receives data (write data DQ1, read data DQ2). In the logic cell group 13, the data input terminal of the FF 301 is connected to the data output terminal on the upper bit side of the memory controller 2. The clock input terminal of the FF 301 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. The data output terminal of the FF 301 is connected to the data input terminal of the FF 302. The clock input terminal of the FF 302 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. The data output terminal of the FF 302 is connected to one input terminal of the selector 310. In this way, the FFs 301 and 302 constitute a shift register.

  In the logic cell group 13, the data input terminal of the FF 303 is connected to the data output terminal on the lower bit side of the memory controller 2. The clock input terminal of the FF 303 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. The data output terminal of the FF 303 is connected to the other input terminal of the selector 310. The control terminal of the selector 310 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. The output terminal of the selector 310 is connected to the input terminal of a three-state buffer 701 provided in the IO buffer 23.

  In the logic cell group 13, one input terminal of the AND 313 is connected to the valid signal output terminal of the memory controller 2. The other input terminal of the AND 313 is connected to the data output terminal of the FF 309. The output terminal of the AND 313 is connected to the data input terminal of the FF 309. The clock input terminal of the FF 309 is connected to one output terminal of the frequency dividing circuit 4. The output terminal of the FF 309 is further connected to the control terminal of the selector 311 and the control terminal of the selector 312.

  In the logic cell group 13, the data input terminal of the FF 305 is connected to the output terminal of the buffer 702 provided in the IO buffer 24. The clock input terminal of the FF 305 is connected to the node N14. The data output terminal of the FF 305 is connected to the data input terminal of the FF 304 and the data input terminal of the FF 306. The clock input terminal of the FF 304 is connected to the node N15. The data output terminal of the FF 304 is connected to one input terminal of the selector 311. The clock input terminal of the FF 306 is connected to the node N15. The data output terminal of the FF 306 is connected to the other input terminal of the selector 311. The output terminal of the selector 311 is connected to the data input terminal on the lower bit side of the memory controller 2.

  In the logic cell group 13, the data input terminal of the FF 307 is connected to the output terminal of the buffer 702 provided in the IO buffer 24. The clock input terminal of the FF 307 is connected to the node N15. The data output terminal of the FF 307 is connected to one input terminal of the selector 312. A data input terminal of the FF 308 is connected to an output terminal of a buffer 702 provided in the IO buffer 24. The clock input terminal of the FF 308 is connected to the node N15. The data output terminal of the FF 308 is connected to the other input terminal of the selector 312. The output terminal of the selector 312 is connected to the data input terminal on the upper bit side of the memory controller 2.

  Although not shown in FIG. 1, the semiconductor device 100 is provided with a number of logic cell groups 13 and IO buffers 24 corresponding to the bit width of the write data DQ1 or the read data DQ2. In the present embodiment, since the bit width of the write data DQ1 is 32 bits, 32 logic cell groups 13 and 32 IO buffers 24 are provided.

  FIG. 6 shows a block diagram of the logic cell group 14. The logic cell group 14 is a circuit block in which a delay adjustment circuit 407 adds a predetermined delay to the read strobe signal DQS2 input via the IO buffer 25. Further, the logic cell group 14 is a circuit block that outputs the write strobe signal DQS 1 to which a predetermined delay is added by the delay adjustment circuit 406 via the IO buffer 25. In the logic cell group 14, the data input terminal of the FF 401 is connected to the mask signal output terminal of the memory controller 2. The clock input terminal of the FF 401 is connected to one output terminal of the frequency dividing circuit 4. The data output terminal of the FF 401 is connected to the data input terminal of the FF 402. The clock input terminal of the FF 402 is connected to one output terminal of the frequency dividing circuit 4. The data output terminal of the FF 402 is connected to one input terminal of the AND 405. The other input terminal of the AND 405 is connected to one output terminal of the frequency dividing circuit 4. The output terminal of the AND 405 is connected to the input terminal of the delay adjustment circuit 406. An output terminal of the delay adjustment circuit 406 is connected to an input terminal of a three-state buffer 701 provided in the IO buffer 25.

  In the logic cell group 14, the input terminal of the delay adjustment circuit 407 is connected to the output terminal of the buffer 702 provided in the IO buffer 25. The output terminal of the delay adjustment circuit 407 is connected to the clock input terminal of the FF 404, the clock input terminal of the FF 403, and the node N14. The data input terminal of the FF 404 is connected to the node N15 and the data output terminal of the FF 403. The data output terminal of the FF 404 is connected to the data input terminal of the FF 403.

  Although not shown in FIG. 1, the semiconductor device 100 is provided with a number of logic cell groups 14 and IO buffers 25 corresponding to the bit width of the write strobe signal DQS1 or the read strobe signal DQS2. In this embodiment, since the write strobe signal DQS1 and the read strobe signal DQS2 each have a bit width of four bits, four logic cell groups 14 and four IO buffers 25 are provided.

  In the present embodiment, of the four logic cell groups 14, one logic cell group 14 corresponding to the 0th bit read strobe signal DQS2 [0] and the 0th to 7th bit read data. Eight logic cell groups 13 corresponding to DQ2 [7: 0] are connected. Also, one logic cell group 14 corresponding to the first bit read strobe signal DQS2 [1] and eight logic cell groups 13 corresponding to the 8th to 15th bit read data DQ2 [15: 8]. And are connected. In addition, one logic cell group 14 corresponding to the second bit read strobe signal DQS2 [2] and eight logic cell groups 13 corresponding to the 16th to 23th bit read data DQ2 [23:16]. And are connected. One logic cell group 14 corresponding to the third bit read strobe signal DQS2 [3], eight logic cell groups 13 corresponding to the 24th to 31st bit read data DQ2 [31:24], Is connected.

  FIG. 7 shows a block diagram of the logic cell group 15. The logic cell group 15 is a circuit block that detects the reference permission signal PDQM in synchronization with the clock signal DCK2 and outputs it as the permission signal DQM. The permission signal DQM is a signal for permitting the memory 200 to write the write data DQ1. In the logic cell group 15, the data input terminal of the FF 501 is connected to the permission signal output terminal on the upper bit side of the memory controller 2. The clock input terminal of the FF 501 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. The data output terminal of the FF 501 is connected to the data input terminal of the FF 502. The clock input terminal of the FF 502 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. The data output terminal of the FF 502 is connected to one input terminal of the selector 504. Thus, the FFs 501 and 502 constitute a shift register.

  In the logic cell group 15, the data input terminal of the FF 503 is connected to the permission signal output terminal on the lower bit side of the memory controller 2. The clock input terminal of the FF 503 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. The data output terminal of the FF 503 is connected to the other input terminal of the selector 504. The control terminal of the selector 504 is connected to the other output terminal of the frequency divider circuit 4 through the delay adjustment circuit 16. An output terminal of the selector 504 is connected to an input terminal of a three-state buffer 701 provided in the IO buffer 26.

  Next, the operation of the semiconductor device 100 will be described.

  The arithmetic processing circuit 1 has a function of giving a command to the memory controller 2 and adjusting the delay amount of each delay adjustment circuit. The memory controller 2 generates data to be written into the memory 200, receives data read from the memory 200, generates related control signals, and the like based on the command given from the arithmetic processing circuit 1.

  The PLL 3 generates an internal clock and outputs it to the frequency dividing circuit 4. The frequency dividing circuit 4 generates a clock signal (first clock signal) CK1 obtained by dividing the internal clock by four, and outputs it from one output terminal. Further, the frequency dividing circuit 4 divides the internal clock by four, generates a clock signal CK2 that is 270 ° out of phase with the clock signal CK1, and outputs it from the other output terminal. The logic cell group 12 generates clock signals (reference clocks) CK and CKB obtained by adding a delay to the clock signal CK 1, and outputs them to the memory 200 via the IO buffer 22. The clock signal CKB is an inverted signal of the clock signal CK. The delay adjustment circuit 16 generates a clock signal DCK2 obtained by adding a delay to the clock signal CK2.

  The memory controller 2 outputs the reference control signal PCM from the control signal output terminal. The logic cell group 11 generates a control signal CM based on the reference control signal PCM, and outputs the control signal CM to the memory 200 via the IO buffer 21. More specifically, in the logic cell group 11, the FF 101 detects the reference control signal PCM in synchronization with the clock signal CK1, and outputs it to the FF 102. The FF 102 detects the reference control signal PCM detected by the FF 101 in synchronization with the falling edge of the clock signal CK1, and outputs it to the memory 200 via the IO buffer 21 as the control signal CM.

  The control signal CM includes, for example, an address signal ADD, a chip select signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WE, and a clock enable signal CKE. The memory 200 performs mode switching of data writing (write mode) or reading (read mode), designation of data writing or reading target addresses, and the like in synchronization with the clock signals CK and CKB.

  Further, the memory controller 2 outputs the reference write data PDQ1 from the data output terminal. The logic cell group 13 generates write data DQ1 to be written based on the reference write data PDQ1 and outputs the write data DQ1 to the memory 200 via the IO buffer 24. The reference write data PDQ1 has a 64-bit width.

  More specifically, in the logic cell group 13, the FF 301 detects the upper bit side (for example, the 31st bit) reference write data PDQ1 in synchronization with the rising edge of the clock signal DCK, and outputs it to the FF 302. . The FF 302 detects the reference write data PDQ1 detected by the FF 301 in synchronization with the falling edge of the clock signal DCK, and outputs it to the selector 310. On the other hand, the FF 303 detects the reference write data PDQ1 on the lower bit side (for example, the 0th bit) in synchronization with the rising edge of the clock signal DCK, and outputs it to the selector 310. The selector 310 alternately selects and outputs the upper-bit-side reference write data PDQ1 and the lower-bit-side reference write data PDQ1 according to the clock signal DCK. In this way, each of the 32 logic cell groups 13 outputs the corresponding bit write data DQ1 based on the corresponding upper bit side and lower bit side reference write data PDQ1. That is, the 32 logic cell groups 13 alternately output the reference write data PDQ1 on the upper 32 bits side and the lower 32 bits side as the write data DQ1 in synchronization with both edges of the clock signal DCK.

  The memory controller 2 outputs a mask signal MS from the mask signal output terminal. The logic cell group 14 masks the clock signal CK1 and outputs the write strobe signal DQS1 to the memory 200 via the IO buffer 25 while the mask signal MS is on (for example, high level).

  More specifically, in the logic cell group 14, the FF 401 detects the mask signal MS in synchronization with the rising edge of the clock signal CK1, and outputs it to the FF 402. The FF 402 detects the mask signal MS detected by the FF 401 in synchronization with the falling edge of the clock signal CK1, and outputs it to one input terminal of the AND 405. The AND 405 outputs the clock signal CK1 as it is while the mask signal MS detected by the FF 402 is on. The delay adjustment circuit 406 adds a delay to the masked clock signal CK1 and outputs it as a write strobe signal DQS1. Each of the four logic cell groups 14 controls eight different logic cell groups 13. Then, the memory 200 writes the write data DQ1 in synchronization with the write strobe signal DQS1.

  The read strobe signal DQS 2 output from the memory 200 is input to the logic cell group 14 via the IO buffer 24. The logic cell group 14 generates a delay strobe signal DQS2A obtained by adding a delay to the read strobe signal DQS2, and outputs the delayed strobe signal DQS2A to the logic cell group 13.

  More specifically, in the logic cell group 14, the delay adjustment circuit 407 adds a delay to the read strobe signal DQS2 and outputs the delayed strobe signal DQS2A to the FFs 403 and 404. The FF 404 detects the output value of the FF 403 in synchronization with the rising edge of the delay strobe signal DQS2A and outputs it to the FF 403. The FF 403 detects the output value of the FF 404 in synchronization with the falling edge of the delay strobe signal DQS2A, and outputs it to the node N15. That is, the FFs 403 and 404 divide the delayed strobe signal DQS2A by two and output the resultant signal to the node N15 as the delayed strobe signal DQS2B. Further, the delayed strobe signal DQS2A is supplied to the node N14.

  The timing adjustment circuit 5 provided in the memory controller 2 outputs the valid signal EN from the valid signal output terminal. The logic cell group 13 can detect the read data DQ2 during the period when the valid signal EN is on (for example, high level). That is, the logic cell group 13 detects the read data DQ2 while the valid signal EN is on in synchronization with both edges of the delayed strobe signal DQS2A. The logic cell group 13 further detects the read data DQ2 detected in synchronization with both edges of the delayed strobe signal DQS2A in synchronization with the clock signal CK1, and outputs it to the memory controller 2 as reference read data PDQ2. To do. That is, the clock is changed.

  The logic cell group 13 will be further described. Read data DQ <b> 2 read from the memory 200 is input to the logic cell group 13 via the IO buffer 24. The logic cell group 13 generates reference read data PDQ2 based on the read data DQ2, and outputs it to the memory controller 2. The reference read data PDQ2 has a 64-bit width.

  More specifically, the FF 305 detects the read data DQ2 in synchronization with the rising edge of the delay strobe signal DQS2A, and outputs it to the FFs 304 and 306. The FF 304 detects the read data DQ2 detected by the FF 305 in synchronization with the rising edge of the delay strobe signal DQS2B, and outputs it to the selector 311. The FF 306 detects the read data DQ2 detected by the FF 305 in synchronization with the falling edge of the delay strobe signal DQS2B, and outputs it to the selector 311. The FF 307 detects the read data DQ2 in synchronization with the rising edge of the delay strobe signal DQS2B and outputs it to the selector 312. The FF 308 detects the read data DQ2 in synchronization with the falling edge of the delay strobe signal DQS2B and outputs it to the selector 312. When the valid signal EN is off, the FF 309 continues to output a low level signal. When the valid signal EN is on, the FF 309 divides the clock signal CK1 by 2 and outputs it to the selectors 311 and 312.

  Therefore, when the valid signal EN is on, the selector 311 alternately selects and outputs the output of the FF 304 and the output of the FF 306 in synchronization with the rising edge of the clock signal CK1. Similarly, when the valid signal EN is on, the selector 312 alternately selects and outputs the output of the FF 307 and the output of the FF 308 in synchronization with the rising edge of the clock signal CK1. In this way, each of the 32 logic cell groups 13 outputs a corresponding set of reference read data PDQ2 on the upper bit side and lower bit side based on the read data DQ2 of the corresponding bit. In other words, the 32 logic cell groups 13 divide the 8-burst read data DQ2 into the upper 32 bits and the lower 32 bits and output them alternately as the reference read data PDQ2 in synchronization with the rising edge of the clock signal CK1. .

  The memory controller 2 outputs the reference permission signal PDQM from the permission signal output terminal. The logic cell group 15 generates a permission signal DQM based on the reference permission signal PDQM and outputs the permission signal DQM to the memory 200 via the IO buffer 26. Reference permission signal PDQM has an 8-bit width.

  More specifically, in the logic cell group 15, the FF 501 detects the upper-bit side (for example, the fourth bit) reference permission signal PDQM in synchronization with the rising edge of the clock signal DCK, and outputs the detected signal to the FF 502. . The FF 502 detects the reference permission signal PDQM detected by the FF 501 in synchronization with the falling edge of the clock signal DCK and outputs it to the selector 504. On the other hand, the FF 503 detects the reference permission signal PDQM on the lower bit side (for example, the 0th bit) in synchronization with the rising edge of the clock signal DCK and outputs it to the selector 504. The selector 504 alternately selects the upper-bit-side reference permission signal PDQM and the lower-bit-side reference permission signal PDQM by the clock signal DCK, and outputs it as the permission signal DQM.

  Thus, each of the four logic cell groups 15 outputs the corresponding bit permission signal DQM based on the corresponding one set of upper bit side and lower bit side reference permission signals PDQM. That is, the four logic cell groups 15 alternately select the upper 4 bit side and lower 4 bit side reference permission signals PDQM in synchronization with both edges of the clock signal DCK and output them as the permission signals DQM. Note that the memory 200 can write the write data DQ1 while the permission signal DQM is on.

  Next, operation of the semiconductor device 100 illustrated in FIG. 1 will be described with reference to timing charts of FIGS. FIG. 8 is a timing chart showing the operation of the semiconductor device 100 in the read mode. FIG. 9 is a timing chart showing the operation of the semiconductor device 100 in the write mode. The numbers in parentheses attached to the waveforms shown in FIGS. 8 and 9 correspond to the numbers in parentheses attached to the circuits shown in FIGS.

  First, the operation of the semiconductor device 100 in the write mode will be described with reference to FIG. First, the memory controller 2 generates a reference control signal PCM for the write mode (S3). Next, the memory controller 2 generates reference write data PDQ1 having a 64-bit width (S4). In the example of FIG. 8, the memory controller 2 sequentially outputs data D0, D2, D4, and D6 from the upper 32 bits of the reference write data PDQ1 in synchronization with the rising edge of the clock signal CK1. Similarly, the memory controller 2 sequentially outputs data D1, D3, D5, and D7 from the lower 32 bits of the reference write data PDQ1 in synchronization with the rising edge of the clock signal CK1. The memory controller 2 controls the reference permission signal PDQM to be on during the period of outputting the data D0 to D7 (S5). Further, the memory controller 2 turns on the mask signal MS to mask the clock signal CK1 and generate the write strobe signal DQS1 (S6).

  The logic cell group 11 outputs the write mode control signal CM based on the write mode reference control signal PCM (S10). The logic cell group 12 outputs clock signals CK and CKB based on the clock signal CK1 (S1) (S8 and S9). The logic cell group 13 alternately selects the reference write data PDQ1 on the upper 32 bits side and the lower 32 bits side in synchronization with both edges of the clock signal DCK and outputs it as the write data DQ1 (S11). That is, the logic cell group 13 sequentially outputs data D0 to D7 in synchronization with both edges of the clock signal DCK.

  The logic cell group 15 controls the permission signal DQM to be on based on the reference permission signal PDQM during the period of outputting the data D0 to D7 (S13). Further, the logic cell group 14 outputs the masked clock signal CK1 as the write strobe signal DQS1 during the period of outputting the data D0 to D7 (S12). Thus, the write data DQ1 and the write strobe signal DQS1 are generated in synchronization with the clock signal CK1 and the clock signal DCK having different phases, respectively. The memory 200 writes the write data DQ1 in the storage area of the designated address in synchronization with the write strobe signal DQS1.

  Next, the operation of the semiconductor device 100 in the read mode will be described with reference to FIG. First, the memory controller 2 generates a read mode reference control signal PCM. The logic cell group 11 outputs a read mode control signal CM based on the read mode reference control signal PCM (S10). Thereafter, after a period of three clocks of latency and an external delay (tAC), the memory 200 starts to output the read data DQ2 in synchronization with the clock signals CK and CKB (S11). In the example of FIG. 9, the read data DQ2 is composed of 8-burst data D0 to D7. Further, the memory 200 outputs the read strobe signal DQS2 during the period of outputting the data D0 to D7 (S12).

  In the logic cell group 14, the delay adjustment circuit 407 adds a delay to the read strobe signal DQS2 and outputs the delayed strobe signal DQS2A (S14). The logic cell group 14 further divides the delayed strobe signal DQS2A by two and outputs it as a delayed strobe signal DQS2B (S15).

  In the logic cell group 13, the FF 305 detects the read data DQ2 in synchronization with the rising edge of the delay strobe signal DQS2A and outputs it to the FFs 304 and 306. In the example of FIG. 9, the FF 305 sequentially outputs data D0, D2, D4, and D6 in synchronization with the rising edge of the delay strobe signal DQS2A (S16).

  The FF 304 detects the read data DQ2 detected by the FF 305 in synchronization with the rising edge of the delay strobe signal DQS2B, and outputs it to the selector 311. In the example of FIG. 9, the FF 304 sequentially outputs the data D0 and D4 in synchronization with the rising edge of the delay strobe signal DQS2B (S17). The FF 306 detects the read data DQ2 detected by the FF 305 in synchronization with the falling edge of the delay strobe signal DQS2B, and outputs it to the selector 311. In the example of FIG. 9, the FF 306 sequentially outputs data D2 and D6 in synchronization with the falling edge of the delay strobe signal DQS2B. (S18).

  The FF 307 detects the read data DQ2 (S11) in synchronization with the rising edge of the delay strobe signal DQS2B and outputs it to the selector 312. In the example of FIG. 9, the FF 307 sequentially outputs data D1 and D5 in synchronization with the rising edge of the delayed strobe signal DQS2B (S19).

  The FF 308 detects the read data DQ2 (S11) in synchronization with the falling edge of the delay strobe signal DQS2B and outputs it to the selector 312. In the example of FIG. 9, the FF 308 sequentially outputs data D3 and D7 in synchronization with the falling edge of the delayed strobe signal DQS2B (S20).

  The timing adjustment circuit 5 provided in the memory controller 2 controls the effective signal EN to be on (S21). While the valid signal EN is on, the selector 311 alternately selects and outputs the output of the FF 304 and the output of the FF 306 in synchronization with the rising edge of the clock signal CK1 (S1). In the example of FIG. 9, the selector 311 sequentially outputs data D0, D2, D4, and D6 in synchronization with the rising edge of the clock signal CK1 (upper stage of S22). Similarly, during the period when the valid signal EN is on, the selector 312 alternately selects and outputs the output of the FF 307 and the output of the FF 308 in synchronization with the rising edge of the clock signal CK1. In the example of FIG. 9, the selector 312 sequentially outputs data D1, D3, D5, and D7 in synchronization with the rising edge of the clock signal CK1 (lower stage of S22). Thus, the 32 logic cell groups 13 divide the 8-burst read data DQ2 into the upper 32 bits and the lower 32 bits alternately as the reference read data PDQ2 in synchronization with the rising edge of the clock signal CK1. Output.

  As described above, the semiconductor device 100 and the memory 200 transmit and receive data at high speed via the plurality of signal lines. In the semiconductor device 100, a plurality of logic cells are provided between the memory controller 2 and the IO buffers 21 to 26, respectively. In such a case, in order to adjust the AC timing between the semiconductor device 100 and the memory 200, the logic cells provided in the semiconductor device 100 are arranged in the vicinity of the corresponding IO buffers 21 to 26. Therefore, it is necessary to take measures such as suppressing wiring delay errors. However, the semiconductor device 100 is generally designed through RTL design, logic synthesis, and layout design processes. Therefore, when the AC timing is adjusted in the prior art, there is a problem that it takes man-hours such as selecting a target logic cell from a net list generated after logic synthesis and arranging it in the vicinity of the corresponding IO buffer. It was.

  Therefore, in the present embodiment, each of the logic cell groups 11 to 15 provided between the memory controller 2 and each of the IO buffers 21 to 26 is converted into a hard macro and registered in the library in the same manner as other logic cells. Keep it. Here, the hard macro refers to a circuit block for a specific application in which the arrangement and wiring of transistors are determined in advance. In the hard macro, timing is adjusted in advance. Then, in the layout design, the logic cell groups 11 to 15 that are made into a hard macro are arranged in the vicinity of the corresponding IO buffers 21 to 26. At this time, the signal line connecting any one of the IO buffers 21 to 26 and the corresponding hard macro has a delay amount of the signal line connecting the other IO buffer and the corresponding hard macro. It has a corresponding delay amount. In addition, the signal line connecting any one of the IO buffers 21 to 26 and the corresponding hard macro depends on the wiring length of the signal line connecting the other IO buffer and the corresponding hard macro. Have a long wiring length.

  Preferably, they are arranged so that the delay amount of each signal line connecting the logic cell groups 11 to 15 and the corresponding IO buffers 21 to 26 made into a hard macro becomes substantially the same. Further, the wiring lengths of the signal lines connecting the logic cell groups 11 to 15 and the corresponding IO buffers 21 to 26 made into a hard macro are arranged to be substantially the same.

  Note that it is not necessary that the delay amounts of the signal lines connecting the hard macro logic cell groups 11 to 15 and the corresponding IO buffers 21 to 26 are completely the same. It suffices if the delay amount is within a range in which the AC timing can be easily adjusted. Further, it is not necessary that the wiring lengths of the signal lines that connect the hard macro logic cell groups 11 to 15 and the corresponding IO buffers 21 to 26 are completely the same. It suffices if the wiring length is within a range in which the AC timing can be easily adjusted.

  FIG. 10 shows a simplified diagram of the layout of the semiconductor device 100. As shown in FIG. 10, the memory controller 2 is arranged on the right side from the center of the drawing. A plurality of IO buffers are arranged along the outer frame of the semiconductor device 100. Specifically, the IO buffers 22 and 23 for the clock signals CK and CKB and the IO buffer 21 for 17 bits for the control signal CM are sequentially arranged along the outer frame (vertical direction of the paper surface) of the semiconductor device 100. Has been placed. The 4-bit IO buffer 26 for the enable signal DQM, the 4-bit IO buffer 25 for the strobe signals DQS1 and DQS2, and the 32-bit IO buffer 24 for the data DQ1 and DQ2 are provided in the semiconductor device. They are arranged in order along 100 outer frames (lateral direction of the paper). Here, as shown in FIG. 10, the hard-macro logic cell groups 11 to 15 are arranged in the vicinity of the corresponding IO buffers 21 to 26.

  In the subsequent process, the timing of the clock line is adjusted. At this time, the delay variation (skew) from the PLL 3 to the clock input terminals provided in the respective hard macros (logic cell groups 11 to 15) is adjusted. Thereafter, the STA (Static Timing Analysis) measures the absolute delay from the PLL 3 to the clock input terminals of the flip-flops provided in the hard macros (logic cell groups 11 to 15), and fine adjustment of the variation is performed. . Here, the timing of each hard macro is adjusted in advance. That is, in the design of the semiconductor device 100, it is not necessary to adjust the timing inside each hard macro, so that the overall timing adjustment is facilitated. In the present embodiment, the AC timing can be easily adjusted by arranging each hard macro in the vicinity of the corresponding IO buffer. That is, in the present embodiment, unlike the prior art, it is not necessary to select a target logic cell from among a large number of existing logic cells and place it in the vicinity of the corresponding IO buffer at the time of layout design. Therefore, in the present embodiment, the number of man-hours for designing can be reduced.

Embodiment 2
As shown in the first embodiment, the semiconductor device 100 is generally designed through RTL design, logic synthesis, layout design, and STA (Static Timing Analysis) processes. In layout design or the like, timing adjustment of the clock line is performed. At this time, the delay variation (skew) from the PLL 3 to the clock input terminals provided in the respective hard macros (logic cell groups 11 to 15) is adjusted. However, even after the timing is adjusted once, the delay amount of the IO buffers 21 to 26 may change due to the influence of an external load such as the memory 200. In order to eliminate the influence of such an external load, the semiconductor device 100 according to the present embodiment includes a delay adjustment circuit 16, a delay adjustment circuit 201 (see FIG. 4), and a delay adjustment circuit 406 (see FIG. 6). Is used to adjust the amount of delay added to the corresponding signal. The delay adjustment circuits 16, 201, and 406 are composed of, for example, a plurality of delay buffers and a selector. Each delay buffer is provided in parallel, and outputs a different delay amount to the input signal. The selector selects and outputs one of the output signals from the plurality of delay buffers based on the control signal from the CPU 1. As described above, in this embodiment, by using the delay adjustment circuits 16, 201, and 406, data can be transmitted and received without being affected by the external load.

  Further, the semiconductor device 100 according to the present embodiment can perform timing adjustment even after the LSI design is completed. That is, the semiconductor device 100 adjusts the timing so that data can be read and written accurately when the memory 200 such as a DDR-SDRAM actually used is connected, for example, at the time of LSI evaluation.

  More specifically, first, the CPU 1 sets the delay amount of the delay adjustment circuit 407 provided in the logic cell group 14 to the minimum value. For example, when the set value is 0 to 16, the delay adjustment circuit 407 adds a delay amount corresponding to the set value 0 to the read strobe signal DQS2, and outputs the delay strobe signal DQS2A. Under these conditions, first, the semiconductor device 100 writes test data into the memory 200. Next, the semiconductor device 100 reads the test data written in the memory 200 and detects it in synchronization with both edges of the delay strobe signal DQS2A. The CPU 1 compares the test data (expected value) used for writing with the read test data and stores the comparison result. For example, the CPU 1 stores “1” if the expected value matches the read test data, and stores “0” if they do not match.

  Next, the CPU 1 switches the setting value from 0 to 1. That is, the delay adjustment circuit 407 adds a delay amount corresponding to the setting value 1 to the read strobe signal DQS2, and outputs the delay strobe signal DQS2A. Thereafter, through the same operation as in the case of the set value 0, the CPU 1 compares the expected value with the read test data and stores the comparison result. As described above, the CPU 1 compares the expected value with the read test data in each of the setting values 0 to 16, and stores the comparison result. Thereby, 16 comparison results are obtained.

  Then, the CPU 1 finally sets a setting value indicating that the comparison result is “1” in the delay adjustment circuit 407. Here, when there are consecutive set values with the same comparison result, an intermediate value between them is selected. For example, when the comparison results of the setting values 0 to 16 are “000011111110000” in order, since the comparison results are the same between the setting values 4 to 10, the setting value 7 that is an intermediate value is selected. That is, the set value 7 is set for the delay adjustment circuit 407. Thereby, even when a delay error occurs, data can be transmitted and received with high accuracy. Such a delay amount setting is performed for each of the four logic cell groups 14.

  Thus, in the present embodiment, timing adjustment can be performed even after the LSI design is completed. Thereby, in this embodiment, data can be transmitted and received with high accuracy.

  In the case of the interface circuit (semiconductor device) disclosed in Patent Document 1, it is necessary to include a DLL circuit in order to capture data read from the DDR-SDRAM. However, since the DLL circuit has a large mounting area, there is a problem that the circuit scale of the entire interface circuit increases. Along with this, there is a problem that power consumption increases. On the other hand, in this embodiment, unlike the case of the prior art, instead of providing a large-scale circuit such as a DLL circuit, a delay adjustment circuit having a simple logical configuration is provided, and the delay adjustment is performed by an arithmetic processing circuit such as a CPU. Do. Therefore, in this embodiment, an increase in circuit scale and an increase in power consumption can be suppressed.

  Next, the timing adjustment circuit 5 will be described. The timing adjustment circuit 5 includes an internal delay time in the semiconductor device 100, an external delay time from when the control signal CM is output to the memory 200 until the corresponding read data DQ2 is received, and the frequency of the clock signal CK1. Based on the above, the ON period of the valid signal EN is controlled. Here, the internal delay time indicates, for example, the time from when the frequency dividing circuit 4 generates the clock signal CK1 to when it reaches the IO buffer 22 as the clock signal CK.

  11 and 12 are timing charts showing the operation of the semiconductor device 100. FIG. FIG. 11 shows an example in which the frequency of the clock signal CK is 30 MHz and the total time of the internal delay time and the external delay time (tAC) is 15 ns. On the other hand, FIG. 12 shows an example in which the frequency of the clock signal CK is 125 MHz and the total time of the internal delay time and the external delay time (tAC) is 15 ns.

  As shown in FIGS. 11 and 12, even when the total time of the internal delay time and the external delay time is both equal to 15 ns, the degree of influence on data transmission / reception differs depending on the frequency of the clock signal CK1.

  In the case of the timing chart shown in FIG. 11, the total value of the internal delay time and the external delay time is relatively small compared to the cycle of the clock signal CK1. Therefore, the number of clock cycles of the clock signal CK1 required from when the memory controller 2 outputs the read mode reference control signal PCM (time X) until the corresponding read data DQ2 reaches the logic cell group 13 (time Y). Is less. In the example of FIG. 11, the number of clock cycles is “3”.

  Here, the rising edge of the clock signal CK1 after two clock cycles after the memory controller 2 outputs the read mode control signal PCM (time X) is referred to as a reference edge (time Z). In the example of FIG. 11, the corresponding read data DQ2 reaches the logic cell group 13 one clock cycle after the reference edge. At this time, the timing adjustment circuit 5 turns on the valid signal EN after 1 clock cycle from the reference edge (1 CLK mode). Thereby, the memory controller 2 can correctly receive the read data DQ2.

  On the other hand, in the timing chart shown in FIG. 12, the total value of the internal delay time and the external delay time is relatively large compared to the cycle of the clock signal CK1. Therefore, after the memory controller 2 outputs the read mode control signal PCM (time X), the number of clock cycles of the clock signal CK1 required until the corresponding read data DQ2 reaches the logic cell group 13 (time Y) is Become more. In the example of FIG. 12, the number of clock cycles is “4”.

  Here, in the example of FIG. 12, the corresponding read data DQ2 reaches the logic cell group 13 two clock cycles after the reference edge (time Z). At this time, the timing adjustment circuit 5 turns on the valid signal EN after 2 clock cycles have elapsed from the reference edge (2CLK mode). Thereby, the memory controller 2 can correctly receive the read data DQ2.

  Thus, the timing adjustment circuit 5 switches the CLK mode based on the total value of the internal delay time and the external delay time and the frequency of the clock signal CK1. Thereby, the memory controller 2 can correctly receive the read data DQ2.

  13 and 14 are diagrams showing the relationship between the total value of the internal delay time and the external delay time (total delay time T), the frequency of the clock signal CK1, and the CLK mode. For example, when the frequency of the clock signal CK1 is 30 MHz and the total value of the internal delay time and the external delay time is 40 ns, the timing adjustment circuit 5 is set to the 2CLK mode. More specifically, when the total value of the internal delay time and the external delay time is smaller than one clock cycle of the clock signal CK1, the timing adjustment circuit 5 is set to the 1CLK mode. When the total value of the internal delay time and the external delay time is not less than one clock cycle and less than two clock cycles of the clock signal CK1, the timing adjustment circuit 5 is set to the 2CLK mode. When the total value of the internal delay time and the external delay time is 2 clock cycles or more and less than 3 clock cycles of the clock signal CK1, the timing adjustment circuit 5 is set to the 3CLK mode.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. In the above embodiment, the case where the frequency dividing circuit 4 outputs the clock signal CK1 and the clock signal CK2 whose phase is 270 ° different from that of the clock signal CK1 has been described as an example. The phase difference between the clock signal CK1 and the clock signal CK2 can be arbitrarily set.

  In this embodiment, the case where the CPU 1 and the memory controller 2 are provided inside the semiconductor device 100 has been described as an example, but the present invention is not limited thereto. The CPU 1 and the memory controller 2 can be appropriately changed to a circuit configuration provided outside the semiconductor device 100.

11-15 logic cell group 1 CPU
2 Memory controller 3 PLL
4 Dividing Circuit 5 Timing Adjustment Circuit 16, 201, 406, 407 Delay Adjustment Circuit 21-26 IO Buffer 100 Semiconductor Device 200 Memory 101, 102, 301-309, 401-404, 501-503 FF
202 Inverter 310-312,504 Selector 313,405 AND
701 Three-state buffer 702 Buffer

Claims (7)

A hard macro that is a circuit block that is individually provided corresponding to a plurality of signal lines connected to an external memory and that determines the timing of the corresponding signal lines, and
An IO buffer provided corresponding to each of the hard macros,
2. A semiconductor integrated circuit according to claim 1, wherein each of the wirings connecting the hard macro and the corresponding IO buffer has substantially the same length.   2. The semiconductor integrated circuit according to claim 1, wherein each of the hard macros is disposed in the vicinity of the corresponding IO buffer. A reference clock which is arranged in the vicinity of the first IO buffer and is coupled to the first IO buffer via a first wiring and generated based on the first clock signal is passed through the first IO buffer. A first hard macro that outputs
The second IO buffer is disposed in the vicinity of the second IO buffer and coupled to the second IO buffer via a second wiring, and the input control signal is synchronized with the first clock signal to the second IO buffer. A second hard macro that outputs through a buffer;
Arranged in the vicinity of the third IO buffer and coupled to the third IO buffer via a third wiring to add a predetermined delay to the strobe signal input via the third IO buffer A third hard macro,
A fourth hard macro which is arranged in the vicinity of the fourth IO buffer and coupled to the fourth IO buffer via a fourth wiring and transmits / receives a data signal via the fourth IO buffer; Have
The semiconductor integrated circuit, wherein the first to fourth wirings have substantially the same length. A control circuit for controlling access to an external memory connected to the first to fourth IO buffers;
The control circuit changes a value of the predetermined delay of the third hard macro, obtains a plurality of comparison results comparing the value of the read data of the external memory with the expected value, 4. The semiconductor integrated circuit according to claim 3, wherein the predetermined delay value is determined based on a comparison result. The fourth hard macro is
5. The semiconductor integrated circuit according to claim 3, wherein the data signal is detected in synchronization with the first clock signal after being detected in synchronization with the strobe signal to which a delay is added. . A first hard macro coupled to a first IO buffer via a first wiring and outputting a reference clock generated based on a first clock signal via the first IO buffer;
A second hard macro coupled to the second IO buffer via a second wiring and outputting the input control signal via the second IO buffer in synchronization with the first clock signal;
A third hard macro coupled to the third IO buffer via a third wiring and adding a predetermined delay to the strobe signal input via the third IO buffer;
And a fourth hard macro coupled to a fourth IO buffer via a fourth wiring and transmitting / receiving a data signal via the fourth IO buffer. And
A timing adjustment method for a semiconductor integrated circuit, wherein the first to fourth hard macros are arranged so that the lengths of the first to fourth wirings are the same.   7. The timing adjustment method for a semiconductor integrated circuit according to claim 6, wherein the first to fourth hard macros are arranged so that the delay amounts of the first to fourth wirings are the same.

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