JP2009164263A - Wiring module and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring module which dispenses with redoing timing verification again, when relative arrangements are changed among hard macros and peripheral buffer circuits arranged at peripheral portions. <P>SOLUTION: Th e present invention relates to a wiring module 10 of an axial symmetry and is equipped with a first terminal 11a, a second terminal 11b and a third terminal 11c; a first wiring 12a which connects the first terminal 11a and the second terminal 11b; and a second wiring 12b which connects an intermediate point of the first wiring 12a and the third terminal 11c, wherein the first terminal 11a and the second terminal 11b are mutually provided symmetrically, concerning a symmetry axis. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring module and a semiconductor integrated circuit device.

  In the USB (Universal Serial Bus) standard, referring to FIG. 10, serial data transfer is performed by a data transmission / reception signal line Z7 for D + data and a data transmission / reception signal line Z8 for D-data. . D + and D− in FIG. 10 are data transmission / reception signal terminals for D + data and D− data, respectively. When developing a product equipped with USB, the data transmission / reception signal lines Z7 and Z8 connecting the USB connector Z4 connected to the USB cable side connector Z3 and the transceiver IO cell Z5 of the semiconductor chip are not affected by noise. In addition, it is prohibited to cross each other on the printed circuit board Z1.

  Patent Document 1 discloses a layout method of a semiconductor integrated circuit device. Referring to FIG. 9, the semiconductor integrated circuit device includes an input / output pad 2 and a peripheral buffer between the input / output pad 2 disposed in the peripheral portion of the semiconductor chip 1 and a portion where the peripheral buffer circuit 4 is formed. Tracks T1 to T4 that can be wired are provided in a wiring region 5 for connecting the circuit 4.

  By changing the wiring using the wiring region 5, the peripheral buffer circuit 4 can be arranged without considering the correspondence with the input / output pads 2 arranged in the peripheral part of the semiconductor chip 1. Automatic placement and routing of the peripheral buffer circuit 4 by a computer becomes possible.

JP 60-113943 A

  The following analysis was made by the present inventors. Referring to FIG. 10, the arrangement of the transceiver IO cell Z5 of the semiconductor chip is determined by the arrangement of the USB connector Z4 on the printed board Z1. Further, the arrangement of the host controller macro Z6 of the semiconductor chip is also determined in accordance with the arrangement of the transceiver IO cell Z5. Therefore, after the design of the semiconductor chip Z2, if the position of the USB connector Z4 on the printed circuit board Z1 is changed and the terminal position is switched between the data transmission / reception signal terminals D + and D−, the transceiver IO of the semiconductor chip Z2 It is necessary to redesign the cell Z5 and the host controller macro Z6, and again perform placement and routing, timing verification after placement and routing, and timing adjustment.

  On the other hand, in the layout method disclosed in Patent Document 1, referring to FIG. 9, when an input / output pad 2 is changed after the placement and routing of the semiconductor chip 1, the input / output pad 2 and the peripheral buffer circuit are changed. 4 can be realized by changing the wiring in the wiring region 5. However, the wiring connecting the input / output pad 2 and the peripheral buffer circuit 4 is changed by replacing the wiring in the wiring region 5. Therefore, it is necessary to recalculate the delay time due to the wiring change, crosstalk and bulk capacitance to other signal wiring adjacent to the replaced wiring, and crosstalk and bulk capacitance from other signals. Further, depending on the result of timing verification after placement and routing, timing adjustment adjustment is required. The prior art relates to the wiring between the input / output pad 2 and the peripheral buffer circuit 4 of the semiconductor integrated circuit device, but also in the wiring between the hard macro mounted on the semiconductor chip and the peripheral buffer circuit. The situation is the same.

  Therefore, it is an object to provide a wiring module and a semiconductor integrated circuit device that do not need to perform timing verification again when the relative arrangement is changed between the hard macro and the peripheral buffer circuit arranged in the peripheral portion. It becomes.

The wiring module according to the present invention is
A line-symmetric wiring module,
First, second and third terminals;
A first wiring connecting the first and second terminals;
A second wiring connecting the midpoint of the first wiring and the third terminal;
The first and second terminals are provided symmetrically with respect to an axis of symmetry.

  According to the present invention, there is provided a wiring module and a semiconductor integrated circuit device that do not need to perform timing verification again even when the relative arrangement between the hard macro and the peripheral buffer circuit arranged in the peripheral portion is changed. Provided.

  The reason is as follows. That is, the second wiring connects the first terminal to the third terminal in order to connect the midpoint of the first wiring that connects the first terminal and the second terminal to the third terminal. The wiring length is the same as the wiring length from the second terminal to the third terminal. Therefore, when the first terminal is replaced with the second terminal, the wiring length from both terminals to the third terminal is kept constant.

(First embodiment)
A wiring module according to a first embodiment of the present invention will be described with reference to the drawings.

  Referring to FIG. 11, the wiring module according to the first aspect of the present invention is a line symmetric wiring module 10, which includes first, second and third terminals (11 a to 11 c) and a first terminal. 11a and a second terminal 11b, a first wiring 12a for connecting the middle point of the first wiring 12a and a second wiring 12b for connecting the third terminal 11c, the first terminal 11a and The second terminals 11b are provided symmetrically with respect to the symmetry axis.

  The wiring module 10 in the first development form may be rectangular.

  In the wiring module 10 in the second development form, the first and second terminals (11a, 11b) may be provided on one side of the rectangular wiring module 10.

  The wiring module 10 of the third development form may be provided with the third terminal 11c on the opposite side of the one side.

  The wiring module 10 in the fourth development form may be a convex wiring module.

  In the wiring module 10 of the fifth development form, the first terminal 11a is provided on one of the two sides that are parallel to the axis of symmetry, and the second terminal 11b is provided on the other side. May be provided.

  In the wiring module 10 of the sixth development form, the third terminal 11c may be provided on the side facing the protruding portion.

  In the wiring module of the seventh development form, the first wiring 12a may be line symmetric about the axis of symmetry.

  The wiring module according to the eighth development form may have a plurality of sets including the first, second, and third terminals (11a to 11c) and the first and second wirings (12a, 12b). Good.

  A semiconductor integrated circuit device according to a ninth development form preferably includes the above wiring module.

(Second Embodiment)
A connection adapter macro (wiring module) according to a second embodiment of the present invention will be described.

  When connecting hard macros mounted on a semiconductor chip or between a hard macro and a peripheral buffer circuit, the wiring length and wiring path are the same, and crosstalk, bulk capacitance, and other signals to other adjacent signal wirings A connection adapter macro (wiring module) having the same crosstalk and bulk capacitance is sandwiched. Thus, when the terminal arrangement is changed after the layout design, only one of the hard macro and the connection adapter macro is rotated (mirrored) and arranged and wired. At this time, layout design can be performed without performing timing verification and timing adjustment after placement and routing.

  The adapter macro according to the present embodiment has a first function terminal and a second function terminal as function terminals on one side of a rectangle, and these function terminals have a Y-axis (center point with respect to the center point of the macro). The first branch point is provided at the intermediate point (midpoint) of the wiring connecting the functional terminals to each other and connected to the first branch point. A configuration in which the second branch point is connected in cascade, the third function terminal is arranged on the side (the opposite side) that is paired with the one side, and the second branch point and the third function terminal that are connected in series are connected. Preferably there is.

  In addition, the connection adapter macro includes the first functional terminal and the wiring up to the first branch point, the second functional terminal and the wiring up to the first branch point, right and left, the same wiring length, and the same It is preferable to arrange and wire the wiring paths so that the crosstalk and bulk capacitance to other adjacent signal wires and the crosstalk and bulk capacitance from other signals are the same.

  Further, the connection adapter macro may have a plurality of sets of the above-described functional terminals.

  Further, the connection adapter macro may have a configuration in which a plurality of terminal groups are arranged on both sides of the convex upper portion.

  The adapter macro for connection is provided with an intermediate point (midpoint) of wiring connecting two function terminals as a branch point on the Y coordinate, and when the function terminal is an output terminal, a buffer is input and the function terminal is input. In the case of a terminal, it is preferable to have a connection adapter macro having a configuration in which the OR circuit OR is arranged in the vicinity of the branch point on the wiring connecting the functional terminal and the branch point.

  In the connection adapter macro, the buffer is changed to the AND circuit AND, the OR circuit OR is changed to the AND circuit ANDOR, and a terminal for controlling one input of the AND circuit AND and the AND circuit ANDOR is changed. The structure arrange | positioned on the same edge | side as the said functional terminal group may be sufficient.

  Further, it may be a semiconductor integrated circuit device having the connection adapter macro.

  A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a connection adapter macro (wiring module) according to the present embodiment. A connection adapter macro B is arranged between the hard macro A and the peripheral buffer circuit C. An example in which the three functional terminals D1 to D3 of the hard macro A are connected to the three functional terminals H1 to H3 of the peripheral buffer circuit C is shown.

  The connection adapter macro B has function terminals E1 to E3 and F1 to F3 on one side facing the hard macro A, and the function terminals E1 and F1, E2 and F2, and E3 and F3 are connected adapter macros, respectively. It is arranged at a position symmetric with respect to the Y axis (that is, the symmetry axis perpendicular to the one side) from the center point of B.

  A branch point J1 is provided as an intermediate point of the wiring connecting the functional terminals E1 and F1. Branch points J2 and J3 are provided in the direction opposite to the function terminals E1 and F1 on the same X coordinate as the branch point J1 (X axis is selected in a direction perpendicular to the Y axis). After connecting from the branch point J1 to the branch point J2, two wires are formed symmetrically from the branch point J2 to the branch point J3, and connected from the branch point J3 to the function terminal G1. Further, a branch point K1 is provided as an intermediate point of the wiring connecting the functional terminals E2 and F2. Branch points K2 and K3 are provided in the direction opposite to the positions of the function terminals E2 and F2 on the same X coordinate as the branch point K1. After connecting from the branch point K1 to the branch point K2, two wires are formed symmetrically from the branch point K2 to the branch point K3, and connected from the branch point K3 to the function terminal G2. Furthermore, the middle point of the wiring connecting the functional terminals E3 and F3 is set as a branch point L1, and the branch point L1 is connected to the functional terminal G3.

  The wiring connecting the functional terminal E1 and the branch point J1 and the wiring connecting the functional terminal F1 and the branch point J1 are wiring delay time, crosstalk and bulk capacitance to other signal wiring, and crosstalk from other signals. The bulk capacitance is formed to be equal. In addition, the wiring connecting the functional terminal E2 and the branch point K1, and the wiring connecting the functional terminal F2 and the branch point K1, are wiring delay time, crosstalk and bulk capacitance to other signal wirings, and crossing from other signals. It is formed so that the talk and bulk capacitance are equal. Further, the wiring connecting the functional terminal E3 and the branch point L1 and the wiring connecting the functional terminal F3 and the branch point L1 are also connected to the wiring delay time, crosstalk and bulk capacitance to other signal wirings, and crossing from other signals. It is formed so that the talk and bulk capacitance are equal.

  The X coordinates of the function terminals D1 to D3 of the hard macro A are arranged according to the coordinates of the function terminals E1 to E3 or the function terminals F1 to F3 of the connection adapter macro B. The X coordinates of the function terminals H1 to H3 of the peripheral buffer circuit C are arranged in accordance with the coordinates of the function terminals G1 to G3 of the connection adapter macro B.

  In FIG. 1, a hard macro A and a connection adapter macro B are connected via respective functional terminals D1 and F1, D2 and F2, and D3 and F3. On the other hand, the connection adapter macro B and the peripheral buffer circuit C are connected via respective functional terminals G1 and H1, G2 and H2, and G3 and H3.

  FIG. 2 is a diagram in which the hard macro A of FIG. 1 is mirror-rotated (mirrored). The mirrored hard macro A and connection adapter macro B are connected to each other via their respective function terminals D1 and E1, D2 and E2, and D3 and E3. In the connection adapter macro B, E1 and F1, E2 and F2, and E3 and F3 are functional terminals having the same function. Therefore, the wiring from the hard macro A to the peripheral buffer circuit C is the same between FIG. 1 and FIG. To be kept.

  By using the adapter macro B for connection, even when only the hard macro A is rotated from the center point of the macro with respect to the Y axis (hereinafter referred to as mirror rotation arrangement), the hard macro A is not arranged in mirror rotation. Even when the connection adapter macro B and the peripheral buffer circuit C are arranged in a mirror rotation, the wiring delay time in connection from the hard macro A to the peripheral buffer circuit C, crosstalk and bulk capacitance to other signal wirings, The timing of wiring due to crosstalk and bulk capacitance from other signals remains unchanged.

  In FIG. 1, the function terminals E1 and F1, E2 and F2, and E3 and F3 of the connection adapter macro B are respectively connected to the connection terminals G1, G2, and G3 to the peripheral buffer circuit C, the wiring length, the wiring path, and the other adjacent Since the wiring is formed so that the crosstalk and bulk capacitance to the other signal wiring and the crosstalk and bulk capacitance from other signals are equal, they have exactly the same delay time. Therefore, even when the board terminal position is changed to the mirror rotation position after the chip design, the connection adapter macro B and the peripheral buffer circuit C are arranged in the mirror rotation, so that the arrangement wiring and the arrangement wiring are performed. There is no need to perform timing adjustment based on the subsequent timing verification result.

  A second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a configuration diagram of an adapter macro (wiring module) B according to the second embodiment. Referring to FIG. 3, a connection adapter macro B is arranged between the hard macro A and the peripheral buffer circuit C. The three function terminals D1 to D3 of the hard macro A are connected to the function terminals H1 to H3 of the peripheral buffer circuit C. Consider a case where the function terminals D1 and D2 of the hard macro A are input terminals and the function terminal D3 of the hard macro A is an output terminal.

  The connection adapter macro B includes output function terminals E1 and F1, E2 and F2, and input function terminals E3 and F3 on the same side in contact with the hard macro A. E1 and F1, E2 and F2, and E3 and F3 are arranged at positions symmetrical to the Y axis from the center point of the connection adapter macro B, respectively.

  A branch point J1 is provided as an intermediate point of the wiring connecting the output function terminals E1 and F1, a buffer BUF1 is disposed between the branch point J1 and the output function terminal E1, and a buffer is provided between the branch point J1 and the output function terminal F1. BUF2 is arranged, and the buffer BUF1 and the buffer BUF2 are arranged in the vicinity of the branch point J1 at a position symmetrical to the Y axis. The inputs of the buffer BUF1 and the buffer BUF2 are connected to the branch point J1, the output of the buffer BUF1 is connected to the output function terminal E1, and the output of the buffer BUF2 is connected to the output function terminal F1. Provided as branch points J2 and J3 on the same X coordinate as branch point J1 in the opposite direction to the positions of function terminals E1 and F1, and connected from branch point J1 to branch point J2, and then symmetrical from branch point J2 to branch point J3 Two wirings are formed and connected from the branch point J3 to the function terminal G1.

  A branch point K1 is provided as an intermediate point of the wiring connecting the output function terminals E2 and F2. A buffer BUF3 is disposed between the branch point K1 and the output function terminal E2, and a buffer BUF4 is disposed between the branch point K1 and the output function terminal F2. The buffer BUF3 and the buffer BUF4 are arranged in the vicinity of the branch point K1 and at a position symmetrical to the Y axis. The inputs of the buffer BUF3 and the buffer BUF4 are connected to the branch point K1. The output of the buffer BUF3 is connected to the output function terminal E2, and the output of the buffer BUF4 is connected to the output function terminal F2. After connecting from the branch point K1 to the branch point K2, two wires are formed symmetrically from the branch point K2 to the branch point K3, and connected from the branch point K3 to the function terminal G2.

  An OR circuit OR1 is arranged at an intermediate point where connection wiring lengths from the input function terminals E3 and F3 are equal. The input function terminals E3 and F3 are connected to the input of the OR circuit OR1, and the output of the OR circuit OR1 is connected to the function terminal G3.

  The wiring connecting the output functional terminal E1 and the branch point J1 and the wiring connecting the output functional terminal F1 and the branch point J1 are based on the wiring delay time, crosstalk and bulk capacitance to other signal wirings, and other signals. The crosstalk and the bulk capacitance are formed to be equal. Further, the wiring connecting the output functional terminal E2 and the branch point K1, and the wiring connecting the output functional terminal F2 and the branch point K1, the wiring delay time, crosstalk and bulk capacitance to other signal wiring, and other It is formed so that the crosstalk from the signal and the bulk capacitance are equal. Further, the wiring connecting the input functional terminal E3 and the OR circuit OR1, and the wiring connecting the input functional terminal F3 and the OR circuit OR1, the wiring delay time, crosstalk and bulk capacitance to other signal wirings, and It is formed so that the crosstalk and bulk capacitance from other signals are equal.

  The hard macro A includes input function terminals D1 and D2 and output function terminals D3 and M1. The coordinates of the input function terminals D1 and D2 and the output function terminals D3 and M1 are arranged in accordance with the coordinates of the output function terminals F1 and F2 and the input function terminal F3 of the connection adapter macro B. The output function terminal M1 is arranged at a symmetrical position with respect to the Y axis passing through the center point of the output function terminal D3 and the hard macro A.

  In FIG. 3, the hard macro A and the connection adapter macro B are connected via respective function terminals D1 and F1, D2 and F2, and D3 and F3. Further, the unused input function terminal E3 of the connection adapter macro B is connected to the low-level output function terminal M1 of the hard macro A. Further, the connection adapter macro B and the peripheral buffer circuit C are connected to each other via respective function terminals G1 and H1, G2 and H2, and G3 and H3.

  FIG. 4 is a diagram in which the hard macro A of FIG. The hard macro A and the connection adapter macro B arranged in a mirror rotation are connected to each other via respective function terminals D1 and E1, D2 and E2, and D3 and E3. The unused input function terminal of the connection adapter macro B changes from E3 to F3. However, the hard macro A is connected to the function terminal M1 of the low level output of the hard macro A as before the mirror rotation arrangement, and the function terminals E1 and F1, E2 and F2, and E3 and F3 in the connection adapter macro B are Equivalent functional terminal. Therefore, the wiring from the hard macro A to the peripheral buffer circuit C is kept equal between FIG. 3 and FIG.

  By using the connection adapter macro B, even when only the hard macro A is arranged in the mirror rotation, even when only the connection adapter macro B and the peripheral buffer circuit C are arranged in the mirror rotation without arranging the hard macro A in the mirror rotation The wiring delay time in connection from the hard macro A to the peripheral buffer circuit C, crosstalk and bulk capacitance to other signal wiring, and wiring timing due to crosstalk and bulk capacitance from other signals are not changed. In addition, by arranging a buffer near the branch point of the connection adapter macro B, the wiring load capacity from each branch point of the signal line path to the unused output terminal is separated, the operation speed is improved, and the unused The influence of external noise on the input function terminals can be reduced.

That is, by arranging the buffers BUF1 to BUF4 and the OR circuit OR1,
(1) The wiring load capacity from the branch point to the functional terminal not connected to the hard macro A can be separated, and the operation speed of the signal line path can be improved.
(2) The influence of external noise picked up by wiring from the branch point to the functional terminal not connected to the hard macro A can be reduced.

  A third embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a configuration diagram of a connection adapter macro (wiring module) according to the present embodiment. A connection adapter macro B is arranged between the hard macro A and the peripheral buffer circuit C. The three functional terminals D1 to D3 of the hard macro A are connected to the functional terminals H1 to H3 of the peripheral buffer circuit C. In this embodiment, the function terminals D1 and D2 of the hard macro A are input terminals, and the function terminal D3 is an output terminal.

  The connection adapter macro B includes output function terminals E1, E2, F1, and F2 and input function terminals E3, F3, and P1 on the same side in contact with the hard macro A. The positional relationships between the function terminals E1 and F1, E2 and F2, and E3 and F3 are symmetrical with respect to the Y axis from the center point of the connection adapter macro B.

  A branch point J1 is provided as an intermediate point of the wiring connecting the output function terminals E1 and F1. An AND circuit AND1 is arranged between the branch point J1 and the output function terminal E1, and an AND circuit ANDB1 is arranged between the branch point J1 and the output function terminal F1. The output of the AND circuit AND1 is connected to the output function terminal E1, and the output of the AND circuit ANDB1 is connected to the output function terminal F1.

  The AND circuits AND1 and ANDB1 are arranged in the vicinity of the branch point J1 at positions symmetrical with respect to the Y axis, and one input of each is connected to the branch point J1. Further, after connecting the branch point J1 and the branch point J2, two wires are formed symmetrically from the branch point J2 to the branch point J3, and connected from the branch point J3 to the function terminal G1.

  A branch point K1 is provided as an intermediate point of the wiring connecting the output function terminals E2 and F2. An AND circuit AND2 is arranged between the branch point K1 and the output function terminal E2, and an AND circuit ANDB2 is arranged between the branch point K1 and the output terminal F2. The output of the AND circuit AND2 is connected to the output function terminal E2, and the output of the AND circuit ANDB2 is connected to the output function terminal F2.

  The AND circuits AND2 and ANDB2 are arranged in the vicinity of the branch point K2 at positions symmetrical with respect to the Y axis, and one input of each is connected to the branch point K1. After connecting the branch point K1 and the branch point K2, two wires are formed symmetrically from the branch point K2 to the branch point K3, and connected from the branch point K3 to the function terminal G2.

  An OR circuit OR1 is arranged at a location where the connection wiring lengths from the input function terminals E3 and F3 are equal. An AND circuit AND3 is arranged between one input terminal of the OR circuit OR1 and the input function terminal E3, and an AND circuit ANDB3 is arranged between the other input terminal of the OR circuit OR1 and the input function terminal F3. To do. The logical product circuits AND3 and ANDB3 are arranged in the vicinity of the logical sum circuit OR1 at a position symmetrical to the Y axis with respect to the logical sum circuit OR1. The output of the OR circuit OR1 is connected to the function terminal G3, and the input function terminal P1 of the connection adapter macro B is connected to the other input of the AND circuits AND1, ANDB1, AND2, ANDB2, AND3, and ANDB3. The input terminal P1 of the connection adapter macro B is arranged on the same side as the function terminal D1 of the input of the hard macro A.

  The wiring connecting the output functional terminal E1 and the branch point J1, and the wiring connecting the output functional terminal F1 and the branch point J1, are connected to the wiring delay time, crosstalk and bulk capacitance to other signal wirings, and other signals. Are formed so that the crosstalk and the bulk capacitance are equal. Further, the wiring connecting the output functional terminal E2 and the branch point K1, and the wiring connecting the output functional terminal F2 and the branch point K1, the wiring delay time, crosstalk and bulk capacitance to other signal wiring, and other The crosstalk from the signal and the bulk capacitance are formed to be equal. Further, the wiring connecting the input functional terminal E3 and the OR circuit OR1, and the wiring connecting the input functional terminal F3 and the OR circuit OR1, the wiring delay time, crosstalk and bulk capacitance to other signal wirings, and Crosstalk and bulk capacitance from other signals are formed to be equal.

  The hard macro A has input function terminals D1 and D2 and output function terminals D3, M1, and M2, and the terminals D1, D2, and D3 are arranged in accordance with the function terminals F1, F2, and F3 of the connection adapter macro B.

  The output function terminal M1 is arranged in accordance with P1 of the connection adapter macro B, and the output function terminal M1 and the output function terminal M2 are arranged symmetrically with respect to the center point of the hard macro A in the Y axis.

  In FIG. 5, the hard macro A and the connection adapter macro B are connected to their respective function terminals D1 and F1, D2 and F2, D3 and F3, M1 and P1, and the connection adapter macro B and the peripheral buffer circuit C are connected to each other. Functional terminals G1 and H1, G2 and H2, and GD3 and H3 are connected.

  Since the function terminal M1 of the hard macro A is a low level output terminal, the outputs of the AND circuits AND1 and AND2 connected to the function terminals E1 and E2 of the output of the connection adapter macro B are fixed at the low level. Therefore, the function terminals E1 and E2 of the connection adapter macro B are fixed to the low level, and the logic of the output of the adapter macro B to the function terminal G3 is irrespective of whether the input function terminal E3 is at the high level or the low level. This pin does not affect

  FIG. 6 is a diagram in which the hard macro A of FIG. The function terminals D1 and E1, D2 and E2, D3 and E3, and M2 and P1 are connected to the hard macro A and the connection adapter macro B that are arranged in a mirror rotation. In the connection adapter macro B, the function terminals E1 and F1, E2 and F2, and E3 and F3 are equivalent function terminals. Therefore, the wiring from the hard macro A to the peripheral buffer circuit C is kept equal between FIG. 5 and FIG.

  By using the connection adapter macro B, even if only the hard macro A is mirror-rotated, the hard macro A is not mirror-rotated and only the connection adapter macro B and the peripheral buffer circuit C are mirror-rotated. Even in this case, the wiring delay time in the connection from the hard macro A to the peripheral buffer circuit C, crosstalk and bulk capacitance to other signal wiring, and wiring due to crosstalk and bulk capacitance from other signals The timing does not change. Also, by placing an AND circuit in the vicinity of each branch point of the connection adapter macro B, the wiring load capacity from each branch point to an unused output terminal can be separated, and power consumption and noise can be reduced. The influence of external noise picked up by wiring from unused input terminals to branch points can also be reduced.

That is, by disposing the logical product circuits AND1, ANDB1, AND2, ANDB2, AND3, ANDB3 and the logical sum circuit OR1,
(1) Power consumption and noise can be reduced by not driving the wiring load capacity from the branch point to the functional terminal not connected to the hard macro A,
(2) By separating the wiring load capacity from the branch point to the functional terminal not connected to the hard macro A, the operation speed of the signal line path can be improved.
(3) The influence of external noise picked up by wiring from the branch point to the functional terminal not connected to the hard macro A can be reduced.

  A fourth embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a configuration diagram of a connection adapter macro (wiring module) according to the present embodiment. Referring to FIG. 7, a convex connection adapter macro B is disposed between the concave hard macro A and the peripheral buffer circuit C.

  The convex connection adapter macro B includes functional terminals E1 to E3 and F1 to F3. The function terminals E1 to E3 and F1 to F3 are arranged on the left and right sides of the convex shape at positions symmetrical to the Y axis from the center point of the connection adapter macro B, respectively.

  A branch point J1 is provided as an intermediate point of the wiring connecting the functional terminals E1 and F1. Branch points J2 and J3 are provided in the direction of the peripheral buffer circuit C on the same X coordinate as the branch point J1. After connecting from the branch point J1 to the branch point J2, two wires are formed symmetrically from the branch point J2 to the branch point J3, and connected from the branch point J3 to the function terminal G1. Further, a branch point K1 is provided as an intermediate point of the wiring connecting the function terminals E2 and F2. Branch points K2 and K3 are provided in the direction of the peripheral buffer circuit C on the same X coordinate as the branch point K1. After connecting from the branch point K1 to the branch point K2, two wires are formed symmetrically from the branch point K2 to the branch point K3, and connected from the branch point K3 to the function terminal G2. Further, a branch point L1 is provided at an intermediate point of the wiring connecting the function terminals E3 and F3, and the branch point L1 is connected to the function terminal G3.

  The wiring connecting the functional terminal E1 and the branch point J1 and the wiring connecting the functional terminal F1 and the branch point J1 are wiring delay time, crosstalk and bulk capacitance to other signal wiring, and crosstalk from other signals. The bulk capacitance is formed to be equal. In addition, the wiring connecting the functional terminal E2 and the branch point K1, and the wiring connecting the functional terminal F2 and the branch point K1, are wiring delay time, crosstalk and bulk capacitance to other signal wirings, and crossing from other signals. It is formed so that the talk and bulk capacitance are equal. Furthermore, the wiring connecting the functional terminal E3 and the branch point L1 and the wiring connecting the functional terminal F3 and the branch point L1 are wiring delay time, crosstalk and bulk capacitance to other signal wirings, and crossing from other signals. It is formed so that the talk and bulk capacitance are equal.

  The X coordinates of the function terminals D1 to D3 of the hard macro A are matched with the coordinates of the function terminals E1 to E3 or the function terminals F1 to F3 of the connection adapter macro B. The coordinates of the function terminals H1 to H3 of the peripheral buffer circuit C are matched with the coordinates of the function terminals G1 to G3 of the connection adapter macro B.

  Referring to FIG. 7, the concave hard macro A and the convex connection adapter macro B are connected via respective functional terminals D1 and E2, D2 and F1, and D3 and F3. FIG. 8 is a diagram in which the concave hard macro A of FIG. The concave hard macro A and the convex connection adapter macro B, which are arranged in a mirror rotation manner, are connected via respective functional terminals D1 and F2, D2 and E1, and D3 and E3. In the convex connection adapter macro B, E1 and F1, E2 and F2, and E3 and F3 are equivalent function terminals. Accordingly, the wiring from the concave hard macro A to the peripheral buffer circuit C is kept equal between FIG. 7 and FIG.

  By using the convex connection adapter macro B, even if only the concave hard macro A is arranged in the mirror rotation, the concave hard macro A is not arranged in the mirror rotation and the convex connection adapter. Even when only the macro B and the peripheral buffer circuit C are mirror-rotated, the wiring delay time in the wiring from the concave hard macro A to the peripheral buffer circuit C, crosstalk and bulk capacitance to other signal wirings In addition, the timing of wiring due to crosstalk and bulk capacitance from other signals does not change.

  That is, in the present embodiment, by making the connection adapter macro B convex, the contact portion between the hard macro A and the connection adapter macro B can be increased, and the number of connection terminals of the hard macro and the connection adapter macro can be increased. In many cases, a large number of connection terminals can be arranged without extending the lengths of the hard macro A and the connection adapter macro B in the X direction.

  Although the above description has been made based on examples, the present invention is not limited to the above examples.

It is a block diagram of the connection adapter macro (wiring module) which concerns on Example 1 of this invention. In Example 1 of this invention, it is the block diagram which mirrored the hard macro. It is a block diagram of the connection adapter macro which concerns on Example 2 of this invention. In Example 2 of this invention, it is the block diagram which reflected the hard macro. It is a block diagram of the connection adapter macro which concerns on Example 3 of this invention. In Example 3 of this invention, it is the block diagram which reflected the hard macro. It is a block diagram of the connection adapter macro which concerns on Example 4 of this invention. In Example 4 of this invention, it is the block diagram which reflected the hard macro. It is a figure which shows the conventional layout structure. It is a connection diagram of a USB host controller mounted LSI and a USB connector. It is a block diagram of the wiring module which concerns on embodiment of this invention.

Explanation of symbols

1, Z2 Semiconductor chip 2 Input / output pad 4 Peripheral buffer circuit (input / output buffer circuit)
5 Wiring area 10 Wiring modules 11a-11c Terminals 12a, 12b Wiring A Hard macro AND1-AND3 AND circuit ANDB1-ANDB3 1-inverted AND circuit B Connection adapter macro (wiring module)
BUF1 to BUF4 Buffer C Peripheral buffer circuits D1 to D3, E1 to E3, F1 to F3, G1 to G3 Function terminals D +, D- Data transmission / reception signal terminals J1 to J3, K1 to K3, L1 Branch points M1, M2, P1 Function Terminal OR1 OR circuit T1 to T4 Wiring track Z1 Printed circuit board Z3 USB cable side connector Z4 USB connector Z5 Transceiver IO cell Z6 Host controller macro Z7, Z8 Data transmission / reception signal line

Claims (10)

A line-symmetric wiring module,
First, second and third terminals;
A first wiring connecting the first and second terminals;
A second wiring connecting the midpoint of the first wiring and the third terminal;
A wiring module, wherein the first and second terminals are provided symmetrically with respect to a symmetry axis.   The rectangular wiring module according to claim 1.   The wiring module according to claim 2, wherein the first and second terminals are provided on one side of a rectangular wiring module.   The wiring module according to claim 3, wherein the third terminal is provided on the opposite side of the one side.   The convex wiring module according to claim 1.   The first terminal is provided on one of two sides that are parallel to the axis of symmetry, and the second terminal is provided on the other side of the protruding portion of the convex wiring module. Item 6. The wiring module according to Item 5.   The wiring module according to claim 6, wherein the third terminal is provided on a side facing the protruding portion.   The wiring module according to claim 1, wherein the first wiring is line-symmetric with respect to the symmetry axis.   The wiring module according to claim 1, wherein the wiring module includes a plurality of sets each including the first, second, and third terminals and the first and second wirings.   A semiconductor integrated circuit device comprising the wiring module according to claim 1.

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