CN117494630B

CN117494630B - Register time sequence optimization method and device, electronic equipment and storage medium

Info

Publication number: CN117494630B
Application number: CN202311856978.3A
Authority: CN
Inventors: 张悦; 高帅; 蓝杨; 陈明瑜
Original assignee: Gree Electric Appliances Inc of Zhuhai; Zhuhai Zero Boundary Integrated Circuit Co Ltd
Current assignee: Gree Electric Appliances Inc of Zhuhai; Zhuhai Zero Boundary Integrated Circuit Co Ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-04-26
Anticipated expiration: 2043-12-29
Also published as: CN117494630A

Abstract

The application discloses a register time sequence optimization method, a device, electronic equipment and a storage medium, which comprise the following steps: generating a plurality of initial vector sets based on register information of a first timing circuit in which a first register of the timing violation is located; the initial vector set comprises a plurality of register vectors, and corresponds to the first register, the register vectors comprise the same number of numerical elements, and the numerical values of the numerical elements represent the number of buffers added by the register; adding each register vector contained in the plurality of initial vector sets with the first differential vector respectively to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively; based on a simulated annealing algorithm, calculating the fitness corresponding to each adjacent vector set and screening to obtain a first adjacent vector set corresponding to the maximum value of the fitness; based on the register time sequence corresponding to the first adjacent vector set, the time sequence of the first register is adjusted, so that the optimal time sequence adjustment can be carried out on the register with the violating time sequence, and the performance of the time sequence circuit is improved to a certain extent.

Description

Register time sequence optimization method and device, electronic equipment and storage medium

Technical Field

The application belongs to the technical field of electronic science, and particularly relates to a register time sequence optimization method, a register time sequence optimization device, electronic equipment and a storage medium.

Background

At present, synchronous circuits account for the vast majority of integrated circuit designs with increasingly large scale, clock signal lines are long, loaded registers are more, clock skew (clock skew) is required to be very small, and the time when clock signals reach clock ports of the synchronous registers is basically consistent to ensure normal operation of the circuits, clock skew existing in the design does not necessarily mean time sequence deterioration, and the minimum clock period of normal operation of the circuits is reduced along with the increase of the clock skew, so that positive clock skew has the effect of improving circuit performance. How to effectively use the useful bias to perform timing repair and optimization after clock tree synthesis is a worth of research.

In the related art, a buffer can be inserted in a sequential circuit by means of an EDA tool to balance clock skew in the circuit.

However, this method tends to degrade the overall performance of the circuit, resulting in poor practicality of the circuit.

Disclosure of Invention

An object of an embodiment of the present application is to provide a method, an apparatus, an electronic device, and a readable storage medium for optimizing register timing, which can solve the problem of circuit performance degradation in the related art.

In a first aspect, an embodiment of the present application provides a method for optimizing register timing, where the method includes:

Generating a plurality of initial vector sets based on register information of a first timing circuit in which a first register of the timing violation is located; wherein the initial vector set includes a plurality of register vectors, and corresponds to the first register, the register vectors including the same number of numerical elements, the numerical values of the numerical elements representing the number of buffers added by the register;

Adding each register vector contained in the plurality of initial vector sets with a first differential vector respectively to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively;

based on a simulated annealing algorithm, calculating the fitness corresponding to each adjacent vector set and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness;

And adjusting the time sequence of the first register based on the time sequence of the register corresponding to the first adjacent vector set.

Optionally, generating a plurality of initial vector sets based on the register information of the first timing circuit where the first register of the timing violation is located includes:

determining a register stage number and a first branch number of the first timing circuit from the register information;

Generating the plurality of initial vector sets based on the register stage number and the first branch number; the number of the register vectors contained in the initial vector set is the same as the number of the first branches, the number of the numerical elements contained in the register vectors is the same as the number of the register stages, and the positions of the numerical elements in the register vectors correspond to the positions of each register of the first timing circuit.

Optionally, the method further comprises:

determining a number of numerical elements of a single register vector in the initial vector set;

The first differential vector is generated based on a first location of the first register in the first timing circuit and the number of numerical elements.

Optionally, based on the simulated annealing algorithm, calculating fitness corresponding to each of the adjacent vector sets and screening to obtain a first adjacent vector set corresponding to a maximum fitness in the fitness, including:

taking the building time of the corresponding time sequence of the register as a fitness function;

based on a simulated annealing algorithm and the fitness function, calculating fitness corresponding to each adjacent vector set and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness; wherein the set-up time is positively correlated with the number of buffers.

Optionally, based on the simulated annealing algorithm and the fitness function, calculating fitness corresponding to each of the adjacent vector sets and screening to obtain a first adjacent vector set corresponding to a maximum fitness in the fitness, including:

Calculating fitness of the adjacent vector set based on the simulated annealing algorithm and the fitness function, and determining a second adjacent vector set meeting a first preset condition from the adjacent vector set;

Performing variation of a preset number of rounds on the second adjacent vector set according to a first preset rule to obtain a third adjacent vector set, and calculating the fitness of the third adjacent vector set;

And determining a first adjacent vector set corresponding to the maximum adaptability in all obtained fitness from the second adjacent vector set and the third adjacent vector set.

Optionally, the determining, from the set of adjacent vectors, a second set of adjacent vectors that meets a first preset condition includes:

taking the first establishing time corresponding to the first register as an initial value of an iteration parameter;

determining a neighbor vector set with the change value of the fitness greater than 0 as a fourth neighbor vector set;

determining a fifth set of neighbor vectors from the set of neighbor vectors according to a Metropolis criterion in the case that the change value of the fitness is less than 0;

updating the iteration parameters according to a second preset rule to obtain a first iteration parameter and executing the step of determining a neighbor vector set with the change value of the fitness greater than 0 as a fourth neighbor vector set;

and under the condition that the first iteration parameter meets a second preset condition, determining the fourth adjacent vector set and the fifth adjacent vector set as a second adjacent vector set meeting the first preset condition.

Optionally, the adding each register vector included in the plurality of initial vector sets to the first differential vector to obtain a neighboring vector set corresponding to each of the plurality of initial vector sets includes:

Acquiring a first selection probability corresponding to a first differential vector; the first selection probability is used for determining a first numerical element in the first differential vector;

Based on the first selection probability, each numerical element of the register vectors contained in the plurality of initial vector sets is respectively and correspondingly added with the first numerical element of the first differential vector, and an adjacent vector set respectively corresponding to the plurality of initial vector sets is obtained.

In a second aspect, an embodiment of the present application provides a register timing optimization apparatus, the apparatus comprising:

the first generation module is used for generating a plurality of initial vector sets based on the register information of a first timing circuit where a first register of the timing violations is located; wherein the initial vector set includes a plurality of register vectors, and corresponds to the first register, the register vectors including the same number of numerical elements, the numerical values of the numerical elements representing the number of buffers added by the register;

the first calculation module is used for adding each register vector contained in the plurality of initial vector sets with a first differential vector respectively to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively;

The second calculation module is used for calculating the fitness corresponding to each adjacent vector set based on a simulated annealing algorithm and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness;

And the optimization module is used for adjusting the time sequence of the first register based on the time sequence of the register corresponding to the first adjacent vector set.

Optionally, the first generating module includes:

A first determining submodule for determining a register level number and a first branch number of the first timing circuit from the register information;

A generating sub-module for generating the plurality of initial vector sets based on the register stage number and the first branch number; the number of the register vectors contained in the initial vector set is the same as the number of the first branches, the number of the numerical elements contained in the register vectors is the same as the number of the register stages, and the positions of the numerical elements in the register vectors correspond to the positions of each register of the first timing circuit.

Optionally, the apparatus further comprises:

a determining module for determining a number of numerical elements of a single register vector in the initial vector set;

And a second generation module, configured to generate the first differential vector based on a first position of the first register in the first timing circuit and the number of numerical elements.

Optionally, the second computing module includes:

the second determining submodule is used for taking the building time of the corresponding time sequence of the register as an adaptability function;

The first computing sub-module is used for computing the fitness corresponding to each adjacent vector set based on a simulated annealing algorithm and the fitness function, and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness; wherein the set-up time is positively correlated with the number of buffers.

Optionally, the first computing sub-module includes:

A first calculation unit configured to calculate fitness of the set of neighboring vectors and determine a second set of neighboring vectors that satisfies a first preset condition from the set of neighboring vectors based on the simulated annealing algorithm and the fitness function;

the second calculation unit is used for carrying out variation of a preset number of rounds on the second adjacent vector set according to a first preset rule to obtain a third adjacent vector set and calculating the fitness of the third adjacent vector set;

and the determining unit is used for determining a first adjacent vector set corresponding to the maximum adaptability in all obtained fitness from the second adjacent vector set and the third adjacent vector set.

Optionally, the first computing unit includes:

A first determining subunit, configured to take a first setup time corresponding to the first register as an initial value of an iteration parameter;

A second determining subunit, configured to determine a set of neighboring vectors with a change value of the fitness greater than 0 as a fourth set of neighboring vectors;

a third determining subunit, configured to determine a fifth set of neighbor vectors from the set of neighbor vectors according to a metapolis criterion, in a case where a variation value of the fitness is less than 0;

The iteration subunit is used for updating the iteration parameters according to a second preset rule to obtain a first iteration parameter and executing the step of determining a neighbor vector set with the change value of the fitness greater than 0 as a fourth neighbor vector set;

And the fourth determining subunit is configured to determine, when the first iteration parameter meets a second preset condition, the fourth neighbor vector set and the fifth neighbor vector set as a second neighbor vector set that meets the first preset condition.

Optionally, the first computing module includes:

The acquisition sub-module is used for acquiring a first selection probability corresponding to the first differential vector; the first selection probability is used for determining a first numerical element in the first differential vector;

And the second computing sub-module is used for correspondingly adding each numerical element of the register vectors contained in the plurality of initial vector sets with the first numerical element of the first differential vector respectively based on the first selection probability to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively.

In a third aspect, an embodiment of the present application provides an electronic device, including a register timing optimization device as described above, configured to implement a register timing optimization method as described in any one of the above.

In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement a register timing optimization method as described in any of the above.

In an embodiment of the present application, a method for optimizing register timing is provided, including: generating a plurality of initial vector sets based on register information of a first timing circuit in which a first register of the timing violation is located; the initial vector set comprises a plurality of register vectors, and corresponds to the first register, the register vectors comprise the same number of numerical elements, and the numerical values of the numerical elements represent the number of buffers added by the register; adding each register vector contained in the plurality of initial vector sets with the first differential vector respectively to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively; based on a simulated annealing algorithm, calculating the fitness corresponding to each adjacent vector set and screening to obtain a first adjacent vector set corresponding to the maximum value of the fitness; based on the register time sequence corresponding to the first adjacent vector set, the time sequence of the first register is adjusted, so that the optimal time sequence adjustment can be carried out on the register with the violating time sequence, and the performance of the time sequence circuit is improved to a certain extent.

Drawings

FIG. 1 is a flowchart of a register timing optimization method according to an embodiment of the present application;

FIG. 2 is a flowchart illustrating steps of another register timing optimization method according to an embodiment of the present application;

FIG. 3 is a flow chart of a specific implementation of register timing optimization provided by an embodiment of the present application;

FIG. 4 is a logic block diagram of a register timing optimization apparatus according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

The register timing optimization method provided by the embodiment of the application is described in detail below through specific embodiments and application scenarios thereof with reference to the accompanying drawings.

As shown in fig. 1, fig. 1 is a flowchart illustrating steps of a register timing optimization method according to an embodiment of the present application, where the method may include:

Step 101, generating a plurality of initial vector sets based on register information of a first timing circuit where a first register of a timing violation is located; wherein the initial vector set includes a plurality of register vectors and corresponds to the first register, the register vectors including the same number of numerical elements whose values represent the number of buffers added by the register.

In an embodiment of the present application, the timing circuit is a digital circuit, which is formed by combining a most basic logic gate circuit and a feedback logic loop (output to input) or a device. The sequential circuit has a memory function. There will be different outputs at different times for the same set of inputs. In addition, the sequential circuitry may implement more complex logic functions including data storage, state machines, and the like. A plurality of registers may be included in the sequential circuit, each connected in series or parallel to the circuit. In addition, a buffer can be connected to the input port of the register for delaying the rising edge and the falling edge of the data signal. The time interval corresponding to the active edge of the data signal may be divided into a setup time and a hold time according to a phase difference between the rising edge and the falling edge of the data signal and the clock signal. The set-up time is the shortest time for which data needs to be held before the arrival of the sampling clock edge, and the holding time is the shortest time for which data needs to be held after the arrival of the sampling clock edge and before the arrival of the second data. Thus, if the start of the setup time is after the time of the sampling clock edge or the end of the hold time is before the time of the sampling clock edge, a timing violation occurs, resulting in a data sampling failure. Typically, PRIME TIME tools can be used to analyze the timing of the timing circuit and to be able to obtain the location of the violation registers and the register information of the timing circuit. The register information may include a connection relation of each register in the sequential circuit and a data acquisition time sequence corresponding to each register, for example, a number of stages of each register in the sequential circuit and a number of branches of the sequential circuit corresponding to each register. Therefore, after the first register of the timing violation is acquired, a plurality of initial vector sets may be generated according to the register information of the first timing circuit in which the first register is located. Wherein each initial vector set may comprise a number of register vectors, the number of value elements contained in each register vector may be the same, and the positions of the value elements may correspond to the positions of the registers in the first timing circuit, so that the values of the value elements may represent the number of buffers added by the corresponding registers.

For example, if a branch circuit formed by connecting 5 registers in series can be found in the sequential circuit, the register stage number is 5; if there are 3 branches, the number of the register vectors is 3, and the number of the elements contained in the register vectors is 5; if the first register has 1 register upstream of the branch and 3 registers downstream of the branch, the number of stages of the first register is 2.

And 102, adding each register vector contained in the plurality of initial vector sets with the first differential vector respectively to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively.

In an embodiment of the present application, a first differential vector may be preset to change the numerical value of the numerical value element of each register vector included in the initial vector set. Wherein the number of elements of the first differential vector may be the same as the number of numerical elements of the register vector. When the register vector is added to the first differential vector, the register vector may be added to the element at the same position in the first differential vector. Thus, adjacent vector sets corresponding to the initial vector sets can be obtained. The first differential vector may contain only two elements of "1" and "-1".

With the above example, if the register level is 5, the first differential vector may be { -1, -1, -1}. If one register vector in the initial vector set is {2,3,3,2,4}, then one register vector in the neighbor vector set may be {1,4,4,1,3}.

And 103, calculating the fitness corresponding to each adjacent vector set based on a simulated annealing algorithm, and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness.

In the embodiment of the application, the simulated annealing algorithm is derived from a solid annealing principle, the solid is heated to be sufficiently high, then the solid is slowly cooled, during heating, the internal particles of the solid become disordered along with the temperature rise, the internal energy is increased, during the slowly cooling, the particles gradually become ordered, each temperature reaches an equilibrium state, and finally, the internal energy reaches a ground state at normal temperature, so that the internal energy is minimized. According to the Metropolis criterion, the probability that the particles will tend to equilibrate at temperature T is E (- ΔE/(kT)), where E is the internal energy at temperature T, ΔE is the amount of change it changes, and k is the Boltzmann constant. Simulating the combination optimization problem by using solid annealing, simulating the internal energy E as an objective function value f, and evolving the temperature T into a control parameter T to obtain a simulated annealing algorithm for solving the combination optimization problem: starting from the initial solution i and the initial value t of the control parameter, repeating the iteration of generating a new solution, calculating the objective function difference, accepting or rejecting the objective function difference and gradually attenuating the value t, wherein the current solution when the algorithm is terminated is the obtained approximate optimal solution, which is a heuristic random search process based on the Monte Carlo iteration solution. The annealing process is controlled by a Cooling Schedule comprising initial values t of control parameters and their decay factors Δt, the number of iterations L at each value of t and stop conditions S. The fitness can be used for evaluating the advantages and disadvantages of individuals participating in iteration in the simulated annealing algorithm, and individuals with high fitness are better and individuals with low fitness are worse. That is, the simulated annealing algorithm is a global optimization algorithm. Therefore, the fitness corresponding to each adjacent vector set can be calculated according to the simulated annealing algorithm, and the first adjacent vector set corresponding to the maximum value of the fitness can be obtained through screening. Wherein the sum of the numerical elements of the register vector may be taken as a fitness function.

Step 104, adjusting the time sequence of the first register based on the time sequence of the register corresponding to the first adjacent vector set.

In the embodiment of the present application, in the first adjacent vector set, the value elements included in each register vector may correspond to the registers one by one, so that a corresponding number of buffers may be added at the input ports of each register in the first timing circuit according to the values of the value elements, so that the rising edge of the data will be delayed when the data passes through the buffers, thereby being capable of adjusting the timing of the first register.

For example, a time sequence circuit can be applied in a traffic light control system, and the on-off sequence of traffic lights can be adjusted according to different time periods and traffic flows so as to ensure the smoothness and safety of traffic. In the control process of the traffic light, it is required to ensure that at most one light is simultaneously lighted, and when the timing circuit breaks down, a situation that a plurality of lights are simultaneously lighted may occur. By adopting the scheme, the timing violations in the circuit design process can be optimized, so that the situation that multiple lamps are simultaneously lightened in practical application is avoided.

In an embodiment of the present application, a plurality of initial vector sets are generated by register information of a first timing circuit in which a first register based on a timing violation is located; the initial vector set comprises a plurality of register vectors, and corresponds to the first register, the register vectors comprise the same number of numerical elements, and the numerical values of the numerical elements represent the number of buffers added by the register; adding each register vector contained in the plurality of initial vector sets with the first differential vector respectively to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively; based on a simulated annealing algorithm, calculating the fitness corresponding to each adjacent vector set and screening to obtain a first adjacent vector set corresponding to the maximum value of the fitness; based on the register time sequence corresponding to the first adjacent vector set, the time sequence of the first register is adjusted, so that the optimal time sequence adjustment can be carried out on the register with the violating time sequence, and the performance of the time sequence circuit is improved to a certain extent.

As shown in fig. 2, fig. 2 is a flowchart illustrating steps of another register timing optimization method according to an embodiment of the present application, where the method may include:

Step 201, determining the number of register stages and the number of first branches of the first timing circuit from the register information.

In an embodiment of the present application, the register information of the first timing circuit may include a connection relationship between each register, and the number of register stages and the number of first branches of the first timing circuit may be determined according to the connection relationship.

Step 202, generating the plurality of initial vector sets based on the register stage number and the first branch number; the number of the register vectors contained in the initial vector set is the same as the number of the first branches, the number of the numerical elements contained in the register vectors is the same as the number of the register stages, and the positions of the numerical elements in the register vectors correspond to the positions of each register of the first timing circuit.

In an embodiment of the present application, after determining the register stage number and the first branch number of the first timing circuit, a plurality of initial vector sets may be generated according to the register stage number and the first branch number. The number of register vectors included in each initial vector set may be equal to the number of first branches, and the number of numerical elements included in each register vector may be equal to the number of register stages. The values of the individual value elements may be randomly generated within a preset range. In general, the preset range may be determined by the performance of the buffer, the timing characteristics of the data signal and the sampling signal, and a preset hold time minimum.

In an embodiment of the present application, the number of register stages and the first branch number of the first timing circuit are determined by from the register information; generating a plurality of initial vector sets based on the register stage number and the first branch number; the number of the register vectors contained in the initial vector set is the same as the number of the first branches, the number of the numerical elements contained in the register vectors is the same as the number of the register stages, the positions of the numerical elements in the register vectors correspond to the positions of each register of the first timing circuit, and the corresponding initial vector set can be generated according to the number of the register stages of the first timing circuit and the number of the first branches, so that the usability of the initial vector set is improved.

Step 203 determines the number of numerical elements of a single register vector in the initial vector set.

In an embodiment of the present application, as can be seen from the embodiment content of step 202, the number of numerical elements of each register vector in the initial vector set is the same as the number of register stages in the first timing circuit, and the number of register stages can be determined as the number of numerical elements of a single register vector. The number of numerical elements of the register vector may also be determined by a counting method after the initial vector set is generated.

Step 204, generating the first differential vector based on the first location of the first register in the first timing circuit and the number of numerical elements.

In an embodiment of the application, a first location of a first register in a first timing circuit may be determined first, and then a first differential vector may be generated based on the first location and the number of numerical elements of the register vector. Wherein the number of numerical elements of the first differential vector and the respective register vectors may be the same. Since each numerical element in the register vector corresponds to a register one by one, the numerical element corresponding to the first register in the first differential vector can be determined. According to the timing design rule, in the first differential vector, a value element located before a value element corresponding to the first register may be smaller than 0, and a value element located after the value element corresponding to the first register may be larger than 0. In addition, the first differential vector may include two elements of "1" and "-1" in value.

For example, if the number of register stages of the first timing circuit is 5 and the first register is located at the fourth stage, the first differential vector may be { -1, -1, -1,1} or { -1, -1,1}.

In an embodiment of the present application, by determining the number of numerical elements of a single register vector in an initial vector set; based on the first position of the first register in the first time sequence circuit and the number of the numerical elements, a first differential vector is generated, and a corresponding first differential vector can be generated according to the position of the first register in the time sequence circuit, so that the usability of the first differential vector is improved.

Step 205, adding each register vector included in the plurality of initial vector sets to the first differential vector to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively.

In the embodiment of the present application, the implementation content of this step may refer to the implementation content of step 102, which is not described herein.

Optionally, in step 205, the following sub-steps may be included:

Sub-step 2051, obtaining a first selection probability corresponding to the first differential vector; the first selection probability is used for determining a first numerical element in the first differential vector.

In an embodiment of the present application, the first differential vector may have a first selection probability, and when the first differential vector is used to update a numerical element in the initial vector set, the first selection probability may be used to determine whether the numerical element is updated. The first selection probability can promote the data richness of the adjacent vector set.

Step 2052, based on the first selection probability, adds each numerical element of the register vectors included in the plurality of initial vector sets to the first numerical element of the first differential vector, so as to obtain a neighboring vector set corresponding to each of the plurality of initial vector sets.

In the embodiment of the application, after the first selection probability of the first differential vector is obtained, each register vector contained in each initial vector set and the first differential vector can be added with corresponding position elements according to the first selection probability, so that a neighbor vector set can be obtained. The first selection probability may be used by generating a random number from between (0, 1), if the random number is smaller than the first selection probability, adding and updating the numerical element, otherwise, not updating.

Along the above example, if one register vector in the initial vector set is {5,4,3,3,3}, the first selection probability is 0.3, and if the generated random number is 0.22 when updating the first value element, the register vector is updated to {4,4,3,3,3} and added to the adjacent vector set; if the generated random number is 0.43, the value element of the register vector is kept unchanged and then added to the neighbor vector set.

In the embodiment of the application, a first selection probability corresponding to a first differential vector is obtained; wherein the first selection probability is used for determining a first numerical element in the first differential vector; based on the first selection probability, each numerical element of the register vectors contained in the plurality of initial vector sets is correspondingly added with the first numerical element of the first differential vector to obtain a neighboring vector set corresponding to the plurality of initial vector sets respectively, and the numerical elements in the initial vector sets can be updated according to the first selection probability based on the first differential vector, so that the richness of the neighboring vector sets is improved.

In step 206, the setup time of the register corresponding to the time sequence is used as a fitness function.

In the embodiment of the present application, since the larger the setup time is, the better the data sampling performance of the sequential circuit is, the setup time of the register corresponding to the time sequence can be used as the Fitness Function (Fitness Function), that is, the Fitness is what is the setup time of the register corresponding to the time sequence, so that the Fitness of each register vector can be calculated.

Step 207, calculating fitness corresponding to each adjacent vector set based on a simulated annealing algorithm and the fitness function, and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness; wherein the set-up time is positively correlated with the number of buffers.

In embodiments of the present application, a simulated annealing algorithm may be used to iteratively update the set of neighbor vectors. Wherein the fitness function used for the iteration may be the fitness function described in step 206. After the iteration is completed, the adjacent vector set corresponding to the maximum fitness may be output as the first adjacent vector set.

Optionally, in step 207, the following sub-steps may be included:

Substep 2071, calculating fitness of the set of neighbor vectors and determining a second set of neighbor vectors satisfying a first preset condition from the set of neighbor vectors based on the simulated annealing algorithm and the fitness function.

In the embodiment of the present application, the first preset condition may be an acceptable condition in the simulated annealing algorithm, and the minimum fitness may be set to be used to screen an acceptable set of proximity vectors. If the fitness of the adjacent vector set is less than the minimum fitness, the adjacent vector set is not accepted; if the fitness of the set of neighbor vectors is greater than the minimum fitness, the set of neighbor vectors may be accepted.

Optionally, in the substep 2071, the following substeps may be included:

and a substep A1, wherein a first establishment time corresponding to the first register is used as an initial value of the iteration parameter.

In an embodiment of the present application, the first setup time corresponding to the first register may be used as an initial value of the iteration parameter of the simulated annealing algorithm. The iteration parameter may also be referred to as a temperature parameter, and each time an iteration is performed, the iteration parameter may be updated once.

And a substep A2, determining a neighbor vector set with the change value of the fitness greater than 0 as a fourth neighbor vector set.

In an embodiment of the present application, the first preset condition may include a change value of the fitness being greater than 0. In two adjacent iterations, if the fitness change value of the neighbor vector set is greater than 0, the neighbor vector set may be determined to be a fourth neighbor vector set.

A substep A3 of determining a fifth set of neighbor vectors from the set of neighbor vectors according to the Metropolis criterion in case the change value of the fitness is smaller than 0.

In an embodiment of the present application, the first preset condition may include that, in two adjacent iterations, if the fitness change value of the neighbor vector set is smaller than 0, a fifth neighbor vector set may be determined from the neighbor vector set according to a metapolis criterion. Wherein, the acceptance probability of the Metropolis criterion is shown in formula 1:

(1)

In the formula 1, Δe is a change value of the fitness, and T is an iteration parameter.

A random number may be generated between (0, 1), and if the generated random number is less than Pk, the set of neighbor vectors may be determined to be a fifth set of neighbor vectors.

And a sub-step A4 of updating the iteration parameters according to a second preset rule to obtain a first iteration parameter and executing the step of determining a neighbor vector set with the change value of the fitness greater than 0 as a fourth neighbor vector set.

In an embodiment of the present application, the second preset rule may be to reduce the iteration parameter by a preset proportion. For example, if the preset ratio is 0.7, the iteration parameter may be updated according to the method of T (n+1) =0.7×t (n). Wherein T (n) is an iteration parameter after n iterations. After the iteration is completed, the step of determining the neighbor vector set with the fitness changing value greater than 0 as the fourth neighbor vector set may be performed again, so as to screen out all the fourth neighbor vector set and the fifth neighbor vector set which meet the condition.

And a substep A5, determining the fourth adjacent vector set and the fifth adjacent vector set as a second adjacent vector set meeting the first preset condition under the condition that the first iteration parameter meets the second preset condition.

In an embodiment of the present application, the second preset condition may be that a variation value of the first iteration parameter is smaller than a preset threshold value. In this way, in the case where the variation value of the first iteration parameter is smaller than the preset threshold value, the fourth set of neighbor vectors and the fifth set of neighbor vectors may be determined as the second set of neighbor vectors satisfying the first preset condition.

In the embodiment of the application, the first establishing time corresponding to the first register is used as the initial value of the iteration parameter; determining a neighbor vector set with a change value of the fitness greater than 0 as a fourth neighbor vector set; determining a fifth set of neighbor vectors from the set of neighbor vectors according to a Metropolis criterion in the case that the change value of the fitness is less than 0; updating the iteration parameters according to a second preset rule to obtain a first iteration parameter and executing the step of determining a neighbor vector set with the change value of the fitness greater than 0 as a fourth neighbor vector set; under the condition that the first iteration parameter meets the second preset condition, determining the fourth adjacent vector set and the fifth adjacent vector set as the second adjacent vector set meeting the first preset condition can determine the second adjacent vector set meeting the condition according to the simulated annealing algorithm, so that the availability of the second adjacent vector set is improved.

And step 2072, performing a variation of the preset number of rounds on the second adjacent vector set according to the first preset rule to obtain a third adjacent vector set and calculating the fitness of the third adjacent vector set.

In the embodiment of the present application, the first preset rule may be to update the value of increasing 1 or decreasing 1 for each value element in the second adjacent vector set according to a preset probability. The specific method includes that a random number in a (0, 1) interval is generated, if the value of the random number is smaller than a preset probability, the value update is determined, and then whether the value element is increased by 1 or decreased by 1 is determined with equal probability. And calculating the fitness of the third adjacent vector set once every time the third adjacent vector set is obtained by updating variation in one round. After the calculation is completed, the above steps may be repeated until the number of mutated rounds is the same as the preset number of rounds.

In one possible embodiment, the fitness change value for each round of variation may also be calculated. If the adaptability variation values of the three continuous variations are smaller than the preset threshold value, the variation update can be stopped immediately.

Sub-step 2073, determining a first set of neighbor vectors corresponding to the largest fitness among all the obtained fitness from the second set of neighbor vectors and the third set of neighbor vectors.

In the embodiment of the application, the maximum fitness can be found out from the fitness of the second neighboring vector set and the third neighboring vector set, and the neighboring vector set corresponding to the maximum fitness is determined as the first neighboring vector set.

In the embodiment of the application, the adaptability of the adjacent vector set is calculated based on a simulated annealing algorithm and a fitness function, a second adjacent vector set meeting a first preset condition is determined from the adjacent vector set, the second adjacent vector set is subjected to variation of a preset number of rounds according to a first preset rule to obtain a third adjacent vector set, the adaptability of the third adjacent vector set is calculated, and the first adjacent vector set corresponding to the maximum adaptability in all obtained fitness is determined from the second adjacent vector set and the third adjacent vector set, so that the adjacent vector set can be subjected to variation update, the adaptability of the varied adjacent vector set is calculated, and the reliability of the first adjacent vector set is improved.

In the embodiment of the application, the establishment time of the corresponding time sequence of the register is taken as a fitness function; based on a simulated annealing algorithm and an fitness function, calculating fitness corresponding to each adjacent vector set and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness; the establishing time is positively related to the number of the buffers, and the establishing time of the corresponding time sequence of the register can be directly used as the fitness function, so that the accuracy of the fitness function is improved.

Step 208, adjusting the timing sequence of the first register based on the register timing sequence corresponding to the first neighbor vector set.

In the embodiment of the present application, the implementation content of this step may refer to the implementation content of step 104, which is not described herein.

As shown in fig. 3, fig. 3 is a flowchart of a specific implementation of a register timing optimization method according to an embodiment of the present application. In the figure, the solution is a vector set, and all parameters participating in iteration can be initialized first, the number of register path stages which can be searched by a register with timing violations can be determined, and the register path which can borrow the establishment time can be extracted according to the timing report obtained by the PRIME TIME tool, so that a register vector is formed. According to the number of branches in the sequential circuit, the register vectors can be combined to obtain an initial solution, and finally, a plurality of initial solutions can be generated to form an initial solution set according to the method. And then combining the differential vector to obtain an adjacent solution, judging whether the adjacent solution is acceptable, regenerating the adjacent solution if the adjacent solution is not acceptable, reducing the temperature parameter in the simulated annealing algorithm if the adjacent solution is acceptable, and accumulating the iteration times of the simulated annealing algorithm once. And then judging whether each group of adjacent solutions has completed iteration, if not, returning to regenerate the adjacent solutions, if so, mutating the adjacent solutions according to a preset rule, then recalculating the fitness of each mutated adjacent solution, and accumulating the mutation times once. And if the variation frequency is not maximum, returning to regenerate the adjacent solution, and if the variation frequency is maximum, stopping iteration, and outputting the adjacent solution corresponding to the maximum value of the fitness as an optimal solution.

As shown in fig. 4, fig. 4 is a logic block diagram of a register timing optimization apparatus 400 according to an embodiment of the present application, where the register timing optimization apparatus 400 may include:

a first generating module 401, configured to generate a plurality of initial vector sets based on register information of a first timing circuit in which a first register of a timing violation is located; wherein the initial vector set includes a plurality of register vectors, and corresponds to the first register, the register vectors including the same number of numerical elements, the numerical values of the numerical elements representing the number of buffers added by the register;

A first calculation module 402, configured to add each register vector included in the plurality of initial vector sets to a first differential vector, so as to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively;

The second calculating module 403 is configured to calculate fitness corresponding to each of the adjacent vector sets based on a simulated annealing algorithm, and screen to obtain a first adjacent vector set corresponding to a maximum fitness in the fitness;

and an optimizing module 404, configured to adjust the timing sequence of the first register based on the timing sequence of the register corresponding to the first neighbor vector set.

Optionally, the first generating module 401 includes:

Optionally, the register timing optimization apparatus 400 further includes:

Optionally, the second computing module 403 includes:

Optionally, the first computing sub-module includes:

Optionally, the first computing unit includes:

Optionally, the first computing module 402 includes:

In summary, the register timing optimization device provided by the embodiment of the application includes a first generating module, configured to generate a plurality of initial vector sets based on register information of a first timing circuit where a first register of a timing violation is located; the initial vector set comprises a plurality of register vectors, and corresponds to the first register, the register vectors comprise the same number of numerical elements, and the numerical values of the numerical elements represent the number of buffers added by the register; the first calculation module is used for adding each register vector contained in the plurality of initial vector sets with the first differential vector respectively to obtain adjacent vector sets corresponding to the plurality of initial vector sets respectively; the second calculation module is used for calculating the fitness corresponding to each adjacent vector set based on a simulated annealing algorithm and screening to obtain a first adjacent vector set corresponding to the maximum fitness in the fitness; the optimization module is used for adjusting the time sequence of the first register based on the time sequence of the register corresponding to the first adjacent vector set, so that the optimal time sequence adjustment can be carried out on the register with the violating time sequence, and the performance of the time sequence circuit is improved to a certain extent.

The register timing optimization device in the embodiment of the application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. The electronic device may be a GPU BOX, a Mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile internet appliance (Mobile INTERNET DEVICE, MID), an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, a robot, a wearable device, an ultra-Mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), etc., and may also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a Television (TV), a teller machine, a self-service machine, etc., which are not limited in the embodiments of the present application.

The register timing optimization device in the embodiment of the application can be a device with an operating system. The operating system may be an Android operating system, a Linux, windows operating system or the like, or may be other possible operating systems, and the embodiment of the present application is not limited specifically.

The register timing optimization device provided by the embodiment of the present application can implement each process implemented by the embodiments of the methods of fig. 1 to 3, and in order to avoid repetition, a detailed description is omitted here.

Optionally, as shown in fig. 5, the embodiment of the present application further provides an electronic device M00, which includes a processor M01 and a memory M02, where a program or an instruction that can be executed on the processor M01 is stored in the memory M02, and the program or the instruction implements each step of the embodiment of the register timing optimization method when executed by the processor M01, and can achieve the same technical effect, so that repetition is avoided and no further description is given here.

In an embodiment of the present application, the memory M02 may be used to store software programs as well as various data. The memory M02 may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory M02 may include volatile memory or nonvolatile memory, or the memory M02 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate Synchronous dynamic random access memory (Double DATA RATE SDRAM, DDRSDRAM), enhanced Synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCH LINK DRAM, SLDRAM), and Direct random access memory (DRRAM). Memory M02 in embodiments of the application includes, but is not limited to, these and any other suitable types of memory.

The processor M01 may include one or more processing units; optionally, the processor M01 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor M01.

The embodiment of the application also provides an electronic device, which comprises the register time sequence optimizing device, is used for realizing the processes of the register time sequence optimizing method embodiment, can achieve the same technical effects, and is not repeated here for avoiding repetition.

The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above-mentioned register timing optimization method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here.

Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.

The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the register time sequence optimization method embodiment, and the same technical effects can be achieved, so that repetition is avoided, and the description is omitted here.

It should be understood that the chip according to the embodiments of the present application may also be referred to as a system-on-chip, a chip system, or a system-on-chip.

Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the processes of the embodiments of the register timing optimization method, and achieve the same technical effects, and are not repeated herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the related art in the form of a computer software product stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), including several instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A method of register timing optimization, the method comprising:

adjusting the time sequence of the first register based on the time sequence of the register corresponding to the first adjacent vector set;

the method further comprises the steps of:

generating the first differential vector based on a first location of the first register in the first timing circuit and the number of numerical elements;

The generating a plurality of initial vector sets based on the register information of the first timing circuit where the first register of the timing violation exists includes:

Generating the plurality of initial vector sets based on the register stage number and the first branch number; the number of the register vectors contained in the initial vector set is the same as the number of the first branches, the number of the numerical elements contained in the register vectors is the same as the number of the register stages, and the positions of the numerical elements in the register vectors correspond to the positions of all registers of the first timing circuit;

the step of adding each register vector contained in the plurality of initial vector sets to the first differential vector to obtain adjacent vector sets corresponding to the plurality of initial vector sets, respectively, includes:

2. The method according to claim 1, wherein the calculating the fitness corresponding to each of the neighboring vector sets based on the simulated annealing algorithm and screening to obtain the first neighboring vector set corresponding to the maximum fitness in the fitness includes:

3. The method according to claim 2, wherein calculating fitness corresponding to each of the set of neighboring vectors based on the simulated annealing algorithm and the fitness function and screening to obtain a first set of neighboring vectors corresponding to a maximum fitness of the fitness, comprises:

4. A method according to claim 3, wherein said determining a second set of neighbor vectors from said set of neighbor vectors that meet a first predetermined condition comprises:

5. A register timing optimization apparatus, the apparatus comprising:

The optimization module is used for adjusting the time sequence of the first register based on the time sequence of the register corresponding to the first adjacent vector set;

The apparatus further comprises:

A second generation module configured to generate the first differential vector based on a first position of the first register in the first timing circuit and the number of numerical elements;

The first generation module includes:

A generating sub-module for generating the plurality of initial vector sets based on the register stage number and the first branch number; the number of the register vectors contained in the initial vector set is the same as the number of the first branches, the number of the numerical elements contained in the register vectors is the same as the number of the register stages, and the positions of the numerical elements in the register vectors correspond to the positions of all registers of the first timing circuit;

The first computing module includes:

6. An electronic device comprising the register timing optimization apparatus of claim 5 to implement the register timing optimization method of any one of claims 1 to 4.

7. A storage medium having stored thereon a program or instructions which when executed by a processor implements the register timing optimization method of any one of claims 1 to 4.