CN118261096A - Time sequence repairing method and system for buffer delay data fitting based on full-chip time sequence report - Google Patents
Time sequence repairing method and system for buffer delay data fitting based on full-chip time sequence report Download PDFInfo
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Abstract
The invention relates to the technical field of chip design, and provides a buffer delay data fitting time sequence repairing method based on a full-chip time sequence report. The invention also discloses a system, the method and the system can reduce invalid repeated iterative computation in the chip design process, and can quickly generate the engineering repair script file for maintaining the automatic repair of the time sequence, thereby having high efficiency, being not easy to make mistakes and improving the efficiency of the time sequence repair in the whole chip design process.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a buffer delay data fitting time sequence repairing method and system based on a full-chip time sequence report.
Background
With the development of digital chip design technology, the complexity and integration of chips are continuously improved, the chip design scale is continuously increased, and the frequency is continuously improved. To address these challenges, designers need to divide the chip into more modules in order to better manage complexity and improve performance. The modularized design method enables the design to be more controllable, and enables parallel development and verification to be more convenient. The high-frequency requirements are better met and the reliability and maintainability of the chip are improved by optimizing and analyzing the module.
With more and more modules in a chip, the requirement of high-quality timing verification (timing singff) is more and more severe. In the timing optimization process of the chip, violations (Fanout-AWARE LEAST SLACK) determine the appropriate gate delays by considering the propagation path and driving capability of the signal to maximize the timing margin (slot) and meet the design requirements. The optimization of hold timing requires comprehensive consideration of timing analysis and constraint, logic optimization, hardware partitioning and wiring, and clock optimization.
WO2022109873A1 discloses a timing margin determination method, apparatus, test circuitry and readable storage medium. The method is applied to test circuit system, the test circuit system comprises a first analog circuit and a delay introduction circuit, the first analog circuit is used for simulating a circuit in a first chip to be tested, the delay introduction circuit is used for introducing time sequence delay for the first analog circuit, and the method comprises the following steps: receiving test configuration information; determining a current link to be tested in the first analog circuit according to the test configuration information; adjusting the current link to be tested and/or introducing time sequence delay to the current link to be tested based on the delay introducing circuit so as to cause the first analog circuit to generate time sequence violations; and when the current link to be tested has timing violations, determining a target timing allowance of the current link to be tested.
CN110598235B discloses a method and system for repairing timing violations in chip design, comprising the following steps: step 100, after the chip is laid out and wired, time sequence analysis is carried out based on a time sequence analysis tool to obtain paths of all time sequence violations; step 200, sorting according to the violation values from large to small, and selecting a path corresponding to the maximum violation value as a target repair path; step 300, grabbing all basic units and corresponding delay values on the data path of the target repair path, sorting according to the delay values, and sequentially selecting the basic units as target units according to the sorting; step 400, judging whether the violations of the target repair path are setup time violations or hold time violations and repairing the violations respectively; when repairing, sequentially replacing target units based on rules which do not influence other time sequence paths until the time sequence converges or all target units are completely replaced, and acquiring all repairing operations; step 500, converting the repair operation into an operation command which can be identified by the layout and wiring tool, and executing the operation on the layout and wiring tool based on the layout and wiring data of the edition; step 600, verifying whether the time sequence analysis result after the operation meets the time sequence requirement, returning to the step 200 if the time sequence analysis result does not meet the time sequence requirement, and ending the repair if the time sequence analysis result does not meet the time sequence requirement; in the step 400, the method for replacing the target unit based on the rule that does not affect other timing paths is as follows: under the condition of time violation establishment, judging whether the retention time of all time sequence paths passing through the target unit in the fastest time delay environment has allowance, if so, replacing the target unit, otherwise, not replacing; and under the condition of keeping time violations, judging whether the setup time of all time sequence paths passing through the target unit in the slowest delay environment has a margin, and if so, replacing the target unit, otherwise, not replacing.
CN117494628a discloses a method, device, equipment and storage medium for repairing chip time sequence, which comprises: in the engineering modification stage, acquiring a target chip block and a target system-on-chip; acquiring a target node from the target chip block to serve as an output port, and establishing a two-stage clock tree; and connecting the output port to a clock end of a first trigger in the target system-on-chip through the two-stage clock tree, and repairing the time sequence violation between the target chip block and the interface of the target system-on-chip through the two-stage clock tree.
Because of the optimization of the hold timing, buffers are often inserted in advance at the boundaries of each module, and violations occurring under all working conditions cannot be modified in a targeted manner, so that the redundant design not only reduces the performance of the whole system, but also causes the increase of power consumption.
Disclosure of Invention
Through long-term practice, the optimization of hierarchical module boundary timing sequence is found, in the early stage of chip design, the buffer is inserted into each module boundary in advance in the process, so that a large number of violations can be avoided to a certain extent, and the hold timing (hold timing) of the path under all process-voltage-temperature (Process Voltage Temperature, PVT) conditions is difficult to ensure to meet the design requirement. A sufficient number of redundant designs also results in reduced overall system performance and increased power consumption. If the time sequence report is manually checked, the method of manually inserting a buffer, manually winding and the like on the path to be repaired is found, time and labor are wasted, errors are easy to occur, and all the technical problems of maintaining the time sequence violations and the like cannot be completely repaired.
In view of the above, the present invention provides a method for timing repair based on buffer delay data fitting of full-chip timing report, comprising,
Step S1, reading a top-level time sequence report file comprising time sequence violation data in all paths, wherein the violation data at least comprises path information, and unit names, unit types, unit boundary conditions and delay information of device units on the paths;
Step S2, extracting corresponding unit boundary conditions and delay information in the top-level time sequence report file under different conditions according to the unit type, wherein the unit boundary conditions comprise jump time and output load of an input signal; the delay information is mapped to the corresponding unit boundary condition in the form of a two-dimensional array variable;
S3, calling a linear fitting function, taking the unit boundary condition and the delay information in the step S2 as input data, superposing the linear fitting function, and outputting a binary function parameter set of the linear fitting function;
And S4, extracting the unit boundary conditions and the violation information corresponding to all the target registers, and calculating to obtain buffer types and delay information under different conditions according to the binary function parameter groups of the linear fitting function to generate a script file of engineering repair of each module level.
The transition time (input transition) of an input signal, i.e. the time required from the start point of a signal to the end point of the signal, is usually used to measure the response speed of a circuit.
An output load (output load), i.e. a load connected to the output of the circuit, such as a capacitor or a positive resistor. The magnitude of the output load affects the output voltage and output current of the circuit, and therefore the effect of the output load needs to be considered when designing the circuit.
Engineering repair script files (ENGINEERING CHANGE Order, ECO), also known as ECO script files.
Preferably, in step S4, it is included,
S41, analyzing and sequencing violation values of a target register under different modules, different conditions and different paths;
Step S42, calculating corresponding delay values by adopting linear fitting parameters for all the target registers, and selecting a plurality of buffer types meeting different conditions according to the delay values;
Step S43, selecting a buffer type corresponding to the violation information under the worst condition;
and S44, generating a buffer engineering repair script file of each module level.
Preferably, all path timing violation data includes violation data of device units at each module level in the chip.
Preferably, the device unit includes a buffer, a sequential device including a register, and a nand gate device.
Preferably, the buffer type is different under different conditions, including process, voltage, temperature conditions.
Preferably, the script file of engineering repair is input into a corresponding buffer for time sequence repair.
The invention also discloses a system for executing the time sequence repairing method based on the buffer delay data fitting of the full-chip time sequence report, which comprises,
The acquisition module is used for reading a top-level time sequence report file comprising time sequence violation data in all paths, wherein the violation data at least comprises path information, and unit names, unit types, unit boundary conditions and delay information of device units on the paths;
The preprocessing module is used for extracting corresponding unit boundary conditions and delay information in the top-level time sequence report file under different conditions according to the unit type, wherein the unit boundary conditions comprise jump time and output load of an input signal; the delay information is mapped to the corresponding unit boundary condition in the form of a two-dimensional array variable;
The fitting module is used for calling a linear fitting function, taking the unit boundary condition and the delay information in the step S2 as input data, superposing the linear fitting function, and outputting a binary function parameter set of the linear fitting function;
And the repair module is used for extracting the unit boundary conditions and the violation information corresponding to all the target registers, calculating to obtain buffer types and delay information under different conditions according to the binary function parameter groups of the linear fitting function, and generating engineering repair script files of each module level.
Preferably, the repair module comprises a module for repairing the object,
The analysis submodule is used for analyzing and sequencing the violation values of the target register under different modules, different conditions and different paths;
the calculation sub-module is used for calculating corresponding delay values by adopting linear fitting parameters aiming at all the target registers, and selecting a plurality of buffer types meeting different conditions according to the delay values;
The screening sub-module is used for selecting the buffer type corresponding to the violation information under the worst condition;
and the repair file generation module is used for generating buffer engineering repair script files at each module level.
The invention also provides electronic equipment, at least one processor; and a memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the above-described method of timing repair based on buffer delay data fitting of full-chip timing reports.
The present application also provides a machine-readable storage medium having instructions stored thereon for causing a machine to perform the inventive method of timing repair of buffer delay data fitting based on full chip timing reporting as described above.
Compared with the prior art, the method and the device have the advantages that through the steps S1-S4, the top-level time sequence report file comprising all path time sequence violation data is read, and according to the unit type, corresponding unit boundary conditions in the top-level time sequence report file are extracted under different conditions, wherein the corresponding unit boundary conditions comprise jump time and output load of an input signal; and mapping the delay information to the corresponding unit boundary conditions in a two-dimensional array variable form, and calling a linear fitting function to establish the linear fitting function of the unit boundary conditions and the delay information and output a binary function parameter set in the linear fitting function. And finally, extracting unit boundary conditions and violation information corresponding to all target registers, calculating to obtain buffer types and delay information under different conditions according to binary function parameter groups of the linear fitting function, and generating engineering repair script files of each module level. The invention also discloses a system, the method and the system can calculate the delay information by acquiring the violation data in the global range, aiming at the target register under different process, voltage and temperature conditions and by adopting a data fitting mode, and select a proper buffer type, thereby reducing invalid repeated iterative computation, being capable of quickly generating a script file of engineering repair, being used for maintaining automatic repair of time sequence, having high efficiency, being not easy to make mistakes and improving the efficiency of time sequence repair in the whole chip design process.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, illustrate and explain the invention and are not to be construed as limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a timing repair method for buffer delay data fitting based on full-chip timing reporting according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for timing repair based on buffer delay data fitting for full chip timing reporting according to one embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," "third," and the like in the description and the claims of the present invention and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the prior art, aiming at the optimization of layering module boundary timing sequence, buffers are inserted into respective module boundaries in advance in the process at the early stage of chip design, so that a large number of violations can be avoided to a certain extent, and the hold time of the path under all process-voltage-temperature (Process Voltage Temperature, PVT) conditions is difficult to ensure to meet the design requirement. A sufficient number of redundant designs also results in reduced overall system performance and increased power consumption. If the time sequence report is manually checked, the method of manually inserting a buffer, manually winding and the like on the path to be repaired is found, time and labor are wasted, errors are easy to occur, and all the technical problems of maintaining the time sequence violations and the like cannot be completely repaired. As shown in fig. 1-2, the present invention provides a method for timing repair of buffer delay data fitting based on full-chip timing report, the method for timing repair of buffer delay data fitting based on full-chip timing report comprising,
Step S1, reading a top-level time sequence report file comprising all path time sequence violation data, wherein the violation data at least comprises path information, and unit names, unit types, unit boundary conditions and delay information of device units on a path;
Step S2, extracting corresponding unit boundary conditions and delay information in the top-level time sequence report file under different conditions according to the unit type, wherein the unit boundary conditions comprise jump time and output load of an input signal; the delay information is mapped to the corresponding unit boundary condition in the form of a two-dimensional array variable;
S3, calling a linear fitting function, taking the unit boundary condition and the delay information in the step S2 as input data, superposing the linear fitting function, and outputting a binary function parameter set of the linear fitting function;
And S4, extracting the unit boundary conditions and the violation information corresponding to all the target registers, and calculating to obtain buffer types and delay information under different conditions according to the binary function parameter groups of the linear fitting function to generate a script file of engineering repair of each module level.
According to the invention, through steps S1-S4, through reading a top-level time sequence report file comprising all path time sequence violation data, according to the unit type, corresponding unit boundary conditions in the top-level time sequence report file are extracted under different conditions, wherein the corresponding unit boundary conditions comprise jump time and output load of an input signal; and mapping the delay information to the corresponding unit boundary conditions in a two-dimensional array variable form, and calling a linear fitting function to establish the linear fitting function of the unit boundary conditions and the delay information and output a binary function parameter set in the linear fitting function. And finally, extracting unit boundary conditions and violation information corresponding to all target registers, calculating to obtain buffer types and delay information under different conditions according to binary function parameter groups of the linear fitting function, and generating engineering repair script files of each module level. For identifying the most serious timing violations, predicting circuit delays under different conditions, and selecting appropriate buffers to repair these violations, a repair scheme is ultimately generated to meet timing requirements. According to the method, delay information can be calculated by obtaining violation data in a global range and adopting a data fitting mode aiming at a target register under different process, voltage and temperature conditions, and an appropriate buffer type is selected, so that invalid repeated iterative computation is reduced, an engineering repair script file can be quickly generated, automatic repair of a time sequence is maintained, the efficiency is high, errors are not easy to occur, and the time sequence repair efficiency in the whole chip design process is improved.
In the static timing analysis (STATIC TIMING ANALYSIS, STA) of chip design, the path for holding the violating information of the timing (hold timing) needs to be solved by increasing the delay of the path, by inserting buffers, increasing logic gate delays or adjusting wirings. To better identify and repair these violations, it is ensured that the chip will function properly under various operating conditions. In a preferred aspect of the present invention, step S4 includes,
S41, analyzing and sequencing violation values of a target register under different modules, different conditions and different paths;
Step S42, calculating corresponding delay values by adopting linear fitting parameters for all the target registers, and selecting a plurality of buffer types meeting different conditions according to the delay values;
Step S43, selecting a buffer type corresponding to the violation information under the worst condition;
and S44, generating a buffer engineering repair script file of each module level.
In step S41, timing violations of specific registers under different design modules, operating conditions, and signal transmission paths are identified. The violation value represents the degree to which the timing requirement is not met, typically the difference between the actual delay and the target delay. Ordering these violations helps determine which violations are most severe, with highest priority, should be resolved first.
Linear fits or other mathematical models, such as neural network models, are used to predict signal delays under different operating conditions. Based on these delay values, an appropriate buffer type is selected for each destination register. The buffer can adjust the signal strength to increase or decrease the delay to meet timing requirements. This step involves selecting the appropriate buffer type for the register under different operating conditions (e.g., process, temperature, voltage variations).
Of all operating conditions, particular attention is paid to worst case violation information, which is typically a standard practice in design and verification procedures. Worst case refers generally to the least favorable operating conditions (highest temperature, lowest voltage, etc.), under which the performance of the circuit may be the worst. The choice of the type of buffer that can repair violations under these conditions ensures that the circuit will not violate timing under any conditions.
In the time sequence analysis process, the detailed information of all violations is collected, including the types of violations (such as setup or hold violations), the values of the violations, the paths of the violations, the module information, the conditions for generating the violations and the like. In order to more globally and completely traverse the violation information in the whole chip, the present invention preferably includes the timing violation data in all paths including the violation data of the device units at each module level in the chip. The timing violation data is screened and extracted according to the module to which the timing violation data belongs, the specific conditions generated (such as different processes, voltages, temperature conditions PVT, or different modes or clock domains), and the types of the violating paths. For each offending path, an offending value, i.e., the difference between the actual path delay and the required delay, is calculated. For setup violations, the violation value is the required time minus the actual path delay; for hold violations, the violation value is the actual path delay minus the required time. The collected violations are ordered by their violations, typically starting with the largest violations, as this indicates that the timing violations are most severe.
In order to better address timing repair of different device units in a chip design process, the device units preferably comprise a buffer, a timing device and a NAND gate device, and the timing device comprises a register. Buffers (buffers) are used in digital circuits to enhance the driving capability of signals. Helping the signal to travel over longer lines without attenuation or preventing signal degradation if connected to multiple inputs. In timing analysis, buffers are used to adjust path delays to help meet timing requirements. By selecting different buffer types and sizes, the delay on the signal path is increased or decreased to address timing violations. The timing device (TIMING DEVICES) is a device related to timing control, such as a register. A register is a memory device for storing and transmitting data every clock cycle. They play a key role in determining data flow and processing and are an important component in timing analysis. The sequential devices ensure data synchronization, maintaining stability of the data at the arrival of a particular clock edge, which is critical to avoid timing violations. A nand gate device (NAND GATE DEVICES), which is one of the basic logic gates, is used in digital circuits to implement a logical nand operation. Accepting two or more input signals, outputting a "low" (0) if all inputs are "high" (1); if at least one of the inputs is "low" (0), then a "high" (1) is output. Nand gates are combined into more complex logic functions in digital logic design, such as inverters, and gates, or gates, etc.
During chip design, different process, voltage and temperature conditions have a significant impact on the performance of the circuit. To ensure that the circuit works reliably under all operating conditions, the type of buffer appropriate for these conditions is selected. For example, process variations may result in faster or slower transistors, which affects the delay time of the circuit. It is desirable to select a buffer type that accommodates these process variations to ensure that the circuit meets timing requirements even at the slowest process conditions. The invention preferably has different buffer types under different conditions, including process, voltage and temperature conditions. For example, when the voltage is low, the transistor switching speed becomes slow, resulting in an increase in delay of the circuit; conversely, at higher voltages, the transistor switching speed becomes faster and the delay decreases. The temperature rise may cause a decrease in carrier mobility of the transistor, thereby increasing the delay; while a decrease in temperature may increase carrier mobility, reducing delay.
The type of buffer analyzed and selected generates specific engineering repair schemes for each module, including specifying the insertion or replacement of buffers at specific locations in the circuit, or adjusting parameters of existing buffers. Repair schemes are typically customized for each module because different modules may face different timing requirements and operating conditions. In the preferred case of the invention, the script file of engineering repair is input into the corresponding buffer for time sequence repair.
The invention also discloses a system for executing the time sequence repairing method based on the buffer delay data fitting of the full-chip time sequence report, which comprises,
The acquisition module is used for reading a top-level time sequence report file comprising all path time sequence violation data, wherein the violation data at least comprises path information, and unit names, unit types, unit boundary conditions and delay information of device units on a path;
The preprocessing module is used for extracting corresponding unit boundary conditions and delay information in the top-level time sequence report file under different conditions according to the unit type, wherein the unit boundary conditions comprise jump time and output load of an input signal; the delay information is mapped to the corresponding unit boundary condition in the form of a two-dimensional array variable;
The fitting module is used for calling a linear fitting function, taking the unit boundary condition and the delay information in the step S2 as input data, superposing the linear fitting function, and outputting a binary function parameter set of the linear fitting function;
And the repair module is used for extracting the unit boundary conditions and the violation information corresponding to all the target registers, calculating to obtain buffer types and delay information under different conditions according to the binary function parameter groups of the linear fitting function, and generating engineering repair script files of each module level.
The system reads a top-level timing report file comprising all path timing violation data through an acquisition module. The preprocessing module extracts corresponding unit boundary conditions in the top-layer time sequence report file under different conditions according to the unit type, wherein the corresponding unit boundary conditions comprise jump time and output load of an input signal; the delay information is mapped to the corresponding cell boundary conditions in the form of two-dimensional array variables. The fitting module calls the linear fitting function to establish the linear fitting function of the unit boundary condition and the delay information and output the binary function parameter set in the linear fitting function. The repair module extracts unit boundary conditions and violation information corresponding to all target registers, calculates buffer types and delay information under different conditions according to binary function parameter groups of the linear fitting function, and generates engineering repair script files of each module level. For identifying the most serious timing violations, predicting circuit delays under different conditions, and selecting appropriate buffers to repair these violations, a repair scheme is ultimately generated to meet timing requirements. According to the system, in the chip design process, the delay information can be calculated by acquiring the violation data in the global range and aiming at the target register under different process, voltage and temperature conditions through a data fitting mode, and the proper buffer type is selected, so that invalid repeated iterative computation is reduced, an engineering repair script file can be quickly generated, automatic repair of a time sequence is maintained, the efficiency is high, errors are not easy to occur, and the time sequence repair efficiency in the whole chip design process is improved.
In order to better identify and repair these violations, and thus ensure that the chip can operate properly under various operating conditions, timing violations of specific registers under different design modules, operating conditions, and signal transmission paths are identified. In a preferred aspect of the present invention, the repair module includes,
The analysis submodule is used for analyzing and sequencing the violation values of the target register under different modules, different conditions and different paths;
the calculation sub-module is used for calculating corresponding delay values by adopting linear fitting parameters aiming at all the target registers, and selecting a plurality of buffer types meeting different conditions according to the delay values;
The screening sub-module is used for selecting the buffer type corresponding to the violation information under the worst condition;
and the repair file generation module is used for generating buffer engineering repair script files at each module level.
The invention also provides electronic equipment, at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method described above.
The present application also provides a machine-readable storage medium having stored thereon instructions for causing a machine to perform the method of the present application as described above.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present invention. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, such as the division of the units, merely a logical function division, and there may be additional manners of dividing the actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution contributing to the prior art or in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a mobile terminal, a server or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A time sequence repairing method of buffer delay data fitting based on full-chip time sequence report is characterized in that the time sequence repairing method of buffer delay data fitting based on full-chip time sequence report comprises the following steps,
Step S1, reading a top-level time sequence report file comprising time sequence violation data in all paths, wherein the violation data at least comprises path information, and unit names, unit types, unit boundary conditions and delay information of device units on the paths;
Step S2, extracting corresponding unit boundary conditions and delay information in the top-level time sequence report file under different conditions according to the unit type, wherein the unit boundary conditions comprise jump time and output load of an input signal; the delay information is mapped to the corresponding unit boundary condition in the form of a two-dimensional array variable;
S3, calling a linear fitting function, taking the unit boundary condition and the delay information in the step S2 as input data, superposing the linear fitting function, and outputting a binary function parameter set of the linear fitting function;
And S4, extracting the unit boundary conditions and the violation information corresponding to all the target registers, and calculating to obtain buffer types and delay information under different conditions according to the binary function parameter groups of the linear fitting function to generate a script file of engineering repair of each module level.
2. The method for timing repair based on buffer delay data fitting of full-chip timing report as set forth in claim 1, comprising, in step S4,
S41, analyzing and sequencing violation values of a target register under different modules, different conditions and different paths;
Step S42, calculating corresponding delay values by adopting linear fitting parameters for all the target registers, and selecting a plurality of buffer types meeting different conditions according to the delay values;
Step S43, selecting a buffer type corresponding to the violation information under the worst condition;
and S44, generating a buffer engineering repair script file of each module level.
3. The method of claim 1, wherein the all-path timing violation data comprises violation data of device units at each module level in the chip.
4. The method for timing repair of buffer delay data fitting based on full chip timing reporting of claim 3, wherein said device unit comprises a buffer, a timing device, a nand gate device, said timing device comprising a register.
5. The method for timing repair of buffer delay data fitting based on full-chip timing report as set forth in any of claims 1-4, wherein the buffer type is different under different conditions including process, voltage, temperature conditions.
6. The method for time-series restoration of buffer delay data fitting based on full-chip time-series report according to any one of claims 1 to 4, wherein the script file of engineering restoration is input into the corresponding buffer for time-series restoration.
7. A system for performing the full chip timing report based buffer delay data fitting timing repair method of any of claims 1-6, the system comprising,
The acquisition module is used for reading a top-level time sequence report file comprising time sequence violation data in all paths, wherein the violation data at least comprises path information, and unit names, unit types, unit boundary conditions and delay information of device units on the paths;
The preprocessing module is used for extracting corresponding unit boundary conditions and delay information in the top-level time sequence report file under different conditions according to the unit type, wherein the unit boundary conditions comprise jump time and output load of an input signal; the delay information is mapped to the corresponding unit boundary condition in the form of a two-dimensional array variable;
The fitting module is used for calling a linear fitting function, taking the unit boundary condition and the delay information in the step S2 as input data, superposing the linear fitting function, and outputting a binary function parameter set of the linear fitting function;
And the repair module is used for extracting the unit boundary conditions and the violation information corresponding to all the target registers, calculating to obtain buffer types and delay information under different conditions according to the binary function parameter groups of the linear fitting function, and generating engineering repair script files of each module level.
8. The system of claim 7, wherein the remediation module comprises,
The analysis submodule is used for analyzing and sequencing the violation values of the target register under different modules, different conditions and different paths;
the calculation sub-module is used for calculating corresponding delay values by adopting linear fitting parameters aiming at all the target registers, and selecting a plurality of buffer types meeting different conditions according to the delay values;
The screening sub-module is used for selecting the buffer type corresponding to the violation information under the worst condition;
and the repair file generation module is used for generating buffer engineering repair script files at each module level.
9. An electronic device characterized by at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the full chip timing report based buffer delay data fitting timing repair method of any of claims 1-6.
10. A machine-readable storage medium having stored thereon instructions for causing a machine to perform the method of time series repair of buffer delay data fitting based on full chip time series reports of any of claims 1-6.
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