CN117787173A - Layout method for optimizing retention time - Google Patents
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Abstract
The application discloses a layout method for optimizing retention time, which relates to the technical field of FPGA (field programmable gate array), and the layout method comprises the steps of determining the layout positions of logic units on each retention time critical path in a user input netlist after an FPGA chip is laid out according to the user input netlist to obtain an initial layout state, and then carrying out layout legalization on the initial layout state by taking the movement of the logic units on the same retention time critical path as an optimization target according to a relatively far-away trend. According to the method, in the process of layout legitimization, under the overall layout thought of global layout combined with local optimization to complete legal operation, the same holding time critical path logic unit is enabled to be discrete as far as possible in the process of local optimization so as to increase time delay, and further, holding time violation repair can be completed through layout legitimization, so that a layout result that all paths meet the requirements of establishing time and holding time is obtained, and the layout efficiency is improved.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a layout method for optimizing retention time.
Background
A Field programmable gate array (Field-Programmable Gate Array, FPGA) is a chip that is widely used in household appliances, large machinery, and even aerospace. In the design process of the FPGA, the timing problem is one of the most concerned problems, and in order to ensure the normal and stable operation of the FPGA, it is required to ensure that the timing parameters of the timing devices such as registers in the FPGA meet the requirements, and the Setup time (Setup time) and the Hold time (Hold time) are two important timing parameters. The setup time refers to the time that the data is stable until the rising (or falling) edge of the clock signal of the register arrives, and if the setup time is insufficient, the data cannot be driven into the register on the rising (or falling) edge of the clock signal. The hold time refers to the time after the rising edge (or falling edge) of the clock signal of the register arrives, and if the hold time is insufficient, the data cannot be driven into the register.
For a critical path between two time sequence devices driven by the same clock signal, the establishment time and the holding time need to be met at the same time, the conventional method is to perform layout and wiring design with priority for meeting the establishment time as a target, and the time sequence allowance of the holding time of each path is determined through static time sequence analysis after the design is finished, so that the path with the problem of the holding time can be accurately positioned so as to perform correction and optimization, and the illegal repair of the holding time is realized. However, with the continuous development of the FPGA production process, the FPGA logic unit and the line delay are faster and faster, so that more and more hold time (hold time) problems are exposed.
Disclosure of Invention
The inventor provides a layout method for optimizing the retention time according to the problems and the technical requirements, and the technical scheme of the invention is as follows:
a layout method for optimizing retention time, the layout method comprising:
obtaining a user input netlist corresponding to the FPGA chip, and laying out the FPGA chip according to the user input netlist to obtain an initial layout state, wherein the initial layout state indicates the layout position of each logic unit in the user input netlist;
determining layout positions of logic units on each hold-time critical path in the user input netlist, wherein each hold-time critical path is a path with risk of failing to meet the hold-time requirement;
and taking the logic units on the same holding time critical path as an optimization target according to a relatively far-away trend, carrying out layout legalization on the initial layout state to determine updated layout positions of all the logic units, and completing the layout legalization to obtain a layout result that all paths meet the requirements of the setup time and the holding time.
The further technical scheme is that the layout legalization of the initial layout state comprises the following steps:
for any logic unit on the holding time critical path, setting the selection probability of a layout position which is more distant from other logic units on the same holding time critical path and is more distant from other logic units on the same holding time critical path in the exchange radius of the logic units, and selecting updated layout positions according to the selection probability of each layout position to perform layout position optimization by using a simulated annealing algorithm.
The further technical scheme is that the method for determining each holding time key path in the user input netlist comprises the following steps:
the path that determines the number of stages of logical units passed in the user input netlist to be less than a predetermined threshold is a hold time critical path.
The further technical scheme is that each hold time critical path passes through two stages of logic units.
The further technical scheme is that the layout legalization of the initial layout state comprises the following steps:
when two logic units a and b on the same holding time critical path are also located on the same establishing time critical path at the same time and the front node Pre, the logic unit a, the logic unit b and the rear node Next are sequentially connected along the data transmission direction on the establishing time critical path, according to the reference connection line from the front node Pre to the rear node Next, the two logic units a and b on the same holding time critical path are moved as optimization targets according to relatively far away trends on the basis of optimizing the establishing time of the establishing time critical path to perform layout legalization on the initial layout state; the time critical path is a path which cannot meet the risk of the time requirement.
The further technical scheme is that the layout legalization of the initial layout state according to the reference connection line from the Pre-node to the post-node Next comprises:
and on the basis of keeping the distances between the logic unit a and the logic unit b and the reference connecting line not to exceed a preset threshold value, moving the logic unit a and the logic unit b as optimization targets according to relatively far away trends to legalize the initial layout state.
The further technical scheme is that the layout legalization of the initial layout state according to the reference connection line from the Pre-node to the post-node Next further comprises:
taking the logic unit a along the direction approaching the preamble node Pre as an optimization target on the basis of keeping the distance between the logic unit a and the reference connecting line not to exceed a preset threshold value;
and/or, on the basis of keeping the distance between the logic unit b and the reference connecting line not exceeding a preset threshold value, moving the logic unit b along the direction approaching to the subsequent node Next to serve as an optimization target.
The further technical scheme is that the layout optimization of the layout position of the logic unit a comprises the following steps:
setting the selection probability of the layout positions with smaller distance between the logic unit a and the reference connection line and smaller distance between the logic unit a and the preamble node Pre, selecting the updated layout positions according to the selection probability of each layout position in the logic unit a, and optimizing the layout positions of the logic unit a by using a simulated annealing algorithm.
The further technical scheme is that the layout optimization of the layout position of the logic unit b comprises the following steps:
setting the selection probability of the layout positions with smaller distance between the logic unit b and the reference connecting line and smaller distance between the logic unit b and the Next node Next, and selecting the updated layout positions according to the selection probability of each layout position in the logic unit b, and optimizing the layout positions of the logic unit b by using a simulated annealing algorithm.
The beneficial technical effects of the invention are as follows:
the layout method is characterized in that in the overall layout process of optimizing layout legal operation under the overall layout thought of combining global layout with local optimization to finish legal operation, layout positions of logic units on a critical path of the retention time are screened out before the layout legal process, then when the layout is legal, the logic units on the same critical path of the retention time are moved as an optimization target according to a relatively far trend to optimize, so that the logic units of the same critical path of the retention time are discretized as far as possible to increase time delay, further, maintenance time violation repair can be finished through the layout legal operation, and accordingly, layout results of all paths meeting the requirements of the establishment time and the retention time are obtained, and layout efficiency is improved.
The method locates and maintains the time critical path directly by analyzing the user input netlist according to the stage number of the logic unit through which the path passes, and static time sequence analysis is not needed again, so that the time consumption is further reduced and the layout efficiency is improved.
When the maintenance time violation is repaired in the layout legitimization process, the method does not generate influence on the establishment time of the path beyond the error receiving range, the whole method is still developed on the basis of optimizing the establishment time, and the establishment time and the circuit performance are not sacrificed while the layout efficiency is improved.
Drawings
FIG. 1 is a flow chart of a layout method of one embodiment of the present application.
Fig. 2 is a schematic diagram of the connection of the logic units a and b on a hold time critical path and their preceding node Pre and following node Next of the setup time critical path in an example.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings.
The application discloses a layout method for optimizing retention time, please refer to a flowchart shown in fig. 1, the method comprises the following steps:
step 1, obtaining a user input netlist corresponding to the FPGA chip, and laying out the FPGA chip according to the user input netlist to obtain an initial layout state.
The obtained user input net list aims at the FPGA chip to be laid out, and the total logic resource requirement of the user input net list does not exceed the number of logic resources which can be provided by the FPGA chip to be laid out. The user input netlist is a netlist obtained after completing logic synthesis processing of user design, the logic synthesis processing mainly comprises four processes of reading, translating, optimizing and mapping, the conventional process of developing an FPGA chip by using an EDA tool is adopted, and specific operations of the logic synthesis processing are not expanded. The logic units in the user input netlist are the minimum basic units of the user input netlist, and correspond to a slice level module or a lookup table/register (LUT/REG) level module in the FPGA architecture.
In one embodiment, a Quadratic linear programming layout algorithm (force-directed Quadratic placement, QP) based on a force-directed layout algorithm model (quadric algorithm model) is utilized to perform a global initial layout of the FPGA chip to layout each logic cell in the user input netlist onto the FPGA chip to obtain an initial layout position of each logic cell. The quadratic linear programming layout algorithm is a layout algorithm commonly used at present, and this embodiment will not be described again.
The initial placement state obtained indicates placement locations of the individual logic cells in the user input netlist on the FPGA chip. In the obtained initial layout state, the problem of illegal layout usually exists, for example, the layout positions of the logic units are overlapped, so that after the initial layout is completed, local optimization is performed by combining the layout legal operation.
Step 2, determining the layout positions of the logic units on each hold time critical path in the user input netlist, wherein each hold time critical path is a path with risk of failing to meet the hold time requirements.
Conventional practice uses static timing analysis to learn the hold time of the path, but this is time consuming and the present application directly analyzes the user input netlist to locate the hold time critical path. The larger the time delay of the path is, the more easily the problem of the setup time is, and the less easily the problem of the hold time is; conversely, the smaller the path delay, the less prone the setup time problem, but the more prone the hold time problem.
The time delay of the path comprises the time consumption in the logic units and the time consumption among the logic units, the time consumption in the logic units is fixed, the shorter the time delay is the smaller the number of the stages of the logic units through which the path passes, the shorter the distance between the logic units is, and the problem of the holding time of the path is easily caused in both cases.
Thus, in one embodiment, analyzing the number of stages of logic cells traversed by each path in the user input netlist, determining if a retention time problem exists for each path based on the number of stages of logic cells traversed by the path includes: the path that determines the number of stages of logical units passed through in the user input netlist is less than a predetermined threshold, which is a custom value, is a hold time critical path.
According to practical experience, when other logic units pass between the signal start point and the signal end point of the path, the time consumption of the path is generally larger than the clock offset, so that the path can meet the requirement of the holding time, and the problem of the holding time is easy to occur only when other logic units do not pass between the signal start point and the signal end point. Thus, in one embodiment, the predetermined threshold is 3, and each hold time critical path is determined to pass through two stages of logic units.
After each holding time critical path is screened, the layout position of the logic unit on each holding time critical path in the initial layout state is recorded.
And 3, moving the logic units on the same holding time critical path as an optimization target according to a relatively far trend, carrying out layout legalization on the initial layout state to determine updated layout positions of all the logic units, and completing the layout legalization to obtain a layout result that all paths meet the requirements of establishing time and holding time.
In one embodiment, a simulated annealing algorithm (simulated annealing, SA), which is a currently commonly used local optimization algorithm, is used for local optimization to achieve layout legalization operations, the specific algorithm contents of the simulated annealing algorithm are not described in detail.
As described above, the delay of a path is related to the distance between logic units in addition to the number of stages of the logic units, and the purpose of optimizing the delay of the path can be achieved by optimizing the layout positions of the logic units. In the user design, the paths between the start logic module and the end logic module (usually two registers) driven by the same driving clock must satisfy both the time constraint of setup and hold time: (1) The time sequence constraint of the setup time is used for constraining the time delay of the path to be smaller than the period of the driving clocks of the start logic module and the end logic module, so that in order to enable the path to meet the time sequence constraint of the setup time, the closer the layout positions of the logic modules on the path are, the better the layout positions are, the smaller the time delay generated by connecting lines among the logic modules is, the smaller the time delay of the whole path is, and the requirement of being smaller than the period of the driving clocks can be met. (2) The time sequence constraint of the holding time is used for constraining the time delay of the path to be larger than the clock deviation of the starting logic module and the end logic module, so that in order to enable the path to meet the time sequence constraint of the holding time, the longer the layout position of the logic modules on the path is, the better the layout position is, the time delay generated by connecting lines between the logic modules is as large as possible, the time delay of the whole path is as large as possible, and the requirement of being larger than the clock deviation can be favorably achieved.
From the above theoretical analysis, it can be seen that, in order to achieve both timing constraints of setup time and hold time, the near-far requirements for the layout positions of logic modules on paths are relatively contradictory, which is why it is currently difficult to simultaneously satisfy both timing constraints directly by layout. Because the better the setup time is, the better the circuit performance is, the holding time is ensured to be met without violating the regulations, and the situation that the holding time violations actually occur is less, the current layout thinking is to gather the layout positions of the logic units at first, thereby reducing the line length between the logic units and optimizing the setup time of the paths, so that the time sequence constraint of the setup time is fully met, and then the holding time situation is known by using the time sequence analysis to optimize the whole holding time, which leads to lower layout efficiency.
When the local legalization is carried out by utilizing the traditional simulated annealing algorithm, for any logic unit, randomly selecting a layout position within the exchange radius of the logic unit, and carrying out position exchange by taking the selected layout position as the updated layout position of the logic unit so as to carry out local optimization. The probability of selecting all layout positions in the exchange radius of each logic unit is equal, so that the random selection of the selection in the exchange radius is ensured, and the convergence of the algorithm is ensured by the random selection.
To optimize the above-mentioned switching mechanism of the simulated annealing algorithm with the goal of moving the logic units on the same keep-time critical path in a relatively distant trend, the present application includes:
(1) Traversing a logic unit of layout positions to be optimized according to a preset sequence.
(2) When the traversed logic unit is any logic unit on any holding time critical path, setting that the selection probability of the layout position which is farther from other logic units on the same holding time critical path in the exchange radius of the logic unit is higher, the selection probability of the layout position which is closer to other logic units on the same holding time critical path is lower, and selecting the updated layout position according to the respective selection probability of each layout position to perform layout position optimization by using a simulated annealing algorithm. In this case, the probability of selection of at least two layout positions within the switching radius of each logic cell is not the same to achieve unequal selection.
(3) When the traversed logic unit is not the logic unit on the holding time critical path, selecting updated layout positions in the exchange radius of the logic unit according to equal selection probability according to the conventional practice, and optimizing the layout positions by using a simulated annealing algorithm.
And traversing in turn until the traversing is completed and exiting the local optimization.
Through the optimization, the layout legal process is optimized based on the layout positions of the logic units on each holding time critical path determined in the step 2, so that the logic units on the same holding time critical path are kept away as far as possible to meet the holding time requirement, the holding time problem can be solved simultaneously in the process of layout legal, and the layout efficiency is improved.
When the process of carrying out local optimization by using the simulated annealing algorithm is improved, the traditional simulated annealing algorithm is still required to be kept to optimize the setup time as a main target, so that the layout result meeting the setup time requirement and the hold time requirement can be obtained, and the two conditions are divided into:
1. the two logic units a, b on the same hold time critical path are not located on the setup time critical path, which is a path that has a risk of failing to meet the setup time requirements. At this time, the local optimization of the logic unit on one path keeping time critical according to the method of the application does not affect the setup time, so that the setup time requirement of the path can be met.
2. The two logic units a, b on the same holding time critical path are also located on the same setup time critical path, and the layout optimization of the logic units a, b at this time may affect the setup time of the setup time critical path, so as to meet the basic requirement of the setup time, the embodiment further includes the following contents:
according to practical experience, the established time critical paths are mostly long paths, that is, the number of stages of logic units through which the established time critical paths pass reaches the threshold number of stages, but as analyzed above, there are typically only two logic units on one hold time critical path, so that the duty ratio of two logic units on the hold time critical path in the whole established time critical path is less, and the time sequence of the whole established time critical path is not greatly affected by the two discrete logic units.
For example, referring to fig. 2, two logic units a and b on the same hold time critical path are also simultaneously located on the same setup time critical path, and the preamble node Pre, the logic unit a, the logic unit b, and the subsequent node Next are sequentially connected along the data transmission direction on the setup time critical path. The preamble node Pre sequentially passes through the logic unit a and the logic unit b to reach the Delay (Pre- > a- > b- > Next) of the Next node, the Delay (Pre- > a) +delay (a- > b) +delay (b- > Next), when the logic units a and b on the time critical path are discretely maintained, the Delay (a- > b) between the logic unit a and the logic unit b is increased, but by adjusting the Delay (Pre- > a) between the preamble node Pre and the logic unit a and the Delay (b- > Next) between the logic unit b and the Next node, the overall Delay (Pre- > a- > b- > Next) can still be ensured to meet the requirement of the set-up time. In practical situations, when the time critical path is established to pass through more stages of logic units, the time delay increase caused by the discrete logic unit a and the logic unit b has smaller influence on the whole, so that the method can indicate that the relative discrete of the two logic units on the time critical path is kept as an optimization target and cannot have excessive influence on the establishment time, and after the mechanism is introduced, the method can still be performed on the basis of meeting the requirement of the establishment time of the time critical path.
Further, as described above, the path only requires the hold time not to be violated, but the better the setup time is expected to be, the setup time of the setup time critical path where the logic cell on the hold time critical path is located should be optimized as much as possible when updating the layout position of the logic cell. As shown in fig. 2, the Delay (pre→next) < Delay (pre→a→b→next) of the reference line of the Pre-node to the Next node (as shown by the dotted line of fig. 2), and the closer the logic unit a and the logic unit b are to the reference line of the Pre-node to the Next node, the closer the Delay (pre→a→b→next) is to the Delay (pre→next), so that the Delay of setting up the time critical path can be reduced as much as possible on meeting the requirement of Delay (a→b) to optimize the setup time, and then the circuit performance.
Therefore, based on the analysis, when the layout is legal, according to the reference connection line from the Pre-node to the Next node, the two logic units a and b on the same holding time critical path can be moved as optimization targets according to relatively far away trends on the basis of optimizing the time requirement for establishing the time critical path. Comprising the following steps: and on the basis of keeping the distances between the logic unit a and the logic unit b and the reference connection line not to exceed a preset threshold value, moving the logic unit a and the logic unit b as optimization targets according to relatively far away trends to legalize the initial layout state. Therefore, the logic unit a and the logic unit b can be kept discrete near the reference connecting line, so that the effect of optimizing the set-up time while discrete is achieved. Based on the optimization principle:
taking the logic unit a along the direction approaching the preamble node Pre as an optimization target on the basis of keeping the distance between the logic unit a and the reference connecting line not exceeding a preset threshold value. Also by adjusting the selection probability of the layout position, comprising: setting the higher the selection probability of the layout positions with smaller distance from the reference connecting line and smaller distance from the preamble node Pre in the exchange radius of the logic unit a, selecting the updated layout positions according to the selection probability of each layout position in the exchange radius of the logic unit a, and optimizing the layout positions of the logic unit a by using a simulated annealing algorithm.
And/or the number of the groups of groups,
and on the basis of keeping the distance between the logic unit b and the reference connecting line not exceeding a preset threshold value, moving the logic unit b along the direction approaching to the Next node Next to serve as an optimization target. Also by adjusting the selection probability of the layout position, comprising: setting the higher the selection probability of the layout positions with smaller distance from the reference connecting line and smaller distance from the Next node in the exchange radius of the logic unit b, selecting the updated layout positions according to the selection probability of each layout position in the exchange radius of the logic unit b, and optimizing the layout positions of the logic unit b by using a simulated annealing algorithm.
Claims (9)
1. A layout method for optimizing retention time, the layout method comprising:
obtaining a user input netlist corresponding to an FPGA chip, and laying out the FPGA chip according to the user input netlist to obtain an initial layout state, wherein the initial layout state indicates the layout position of each logic unit in the user input netlist;
determining placement locations of logic cells on each hold-time critical path in the user input netlist, each hold-time critical path being a path at risk of failing to meet hold-time requirements;
and taking the logic units on the same time-keeping critical path as an optimization target according to a relatively far-away trend, carrying out layout legalization on the initial layout state to determine updated layout positions of all the logic units, and completing the layout legalization to obtain a layout result that all paths meet the requirements of the setup time and the retention time.
2. The layout method according to claim 1, wherein layout legalizing the initial layout state includes:
and setting the selection probability of a layout position which is more distant from other logic units on the same holding time critical path and is more distant from other logic units on the same holding time critical path in the exchange radius of any logic unit on the holding time critical path to be lower, and selecting the updated layout position according to the selection probability of each layout position to perform layout position optimization by using a simulated annealing algorithm.
3. The placement method as defined in claim 1, wherein determining each hold time critical path in the user input netlist comprises:
determining that the path of the logic cells passed through in the user input netlist with the number of stages smaller than a predetermined threshold is a hold time critical path.
4. A layout method according to claim 3, wherein each hold time critical path passes through two stages of logic cells.
5. The layout method according to claim 4, wherein layout legalizing the initial layout state includes:
when two logic units a and b on the same holding time critical path are also located on the same establishing time critical path at the same time, and the front node Pre, the logic unit a, the logic unit b and the subsequent node Next are sequentially connected along the data transmission direction on the establishing time critical path, according to the reference connection line from the front node Pre to the subsequent node Next, the two logic units a and b on the same holding time critical path are moved as optimization targets according to relatively far away trends on the basis of optimizing the establishing time of the establishing time critical path to perform layout legalization on the initial layout state; the time critical path is a path which cannot meet the risk of the time requirement.
6. The layout method according to claim 5, wherein layout legalization of the initial layout state according to reference connection of a Pre-node to a post-node Next comprises:
and on the basis of keeping the distances between the logic unit a and the logic unit b and the reference connection line not to exceed a preset threshold value, moving the logic unit a and the logic unit b as optimization targets according to relatively far away trends to legalize the initial layout state.
7. The layout method according to claim 6, wherein layout legalization of the initial layout state according to reference connection of a Pre-node to a post-node Next further comprises:
taking the logic unit a along the direction approaching the preamble node Pre as an optimization target on the basis of keeping the distance between the logic unit a and the reference connecting line not to exceed a preset threshold value;
and/or, on the basis of keeping the distance between the logic unit b and the reference connecting line not exceeding a preset threshold value, moving the logic unit b along the direction approaching to the subsequent node Next to serve as an optimization target.
8. The layout method according to claim 7, wherein performing layout optimization on the layout position of the logic cell a includes:
setting the higher the selection probability of the layout positions with smaller distance from the reference connecting line and smaller distance from the preamble node Pre in the exchange radius of the logic unit a, selecting the updated layout positions according to the selection probability of each layout position in the exchange radius of the logic unit a, and optimizing the layout positions of the logic unit a by using a simulated annealing algorithm.
9. The layout method according to claim 7, wherein performing layout optimization on the layout position of the logic cell b includes:
setting the higher the selection probability of the layout positions with smaller distance from the reference connecting line and smaller distance from the Next node in the exchange radius of the logic unit b, selecting the updated layout positions according to the selection probability of each layout position in the exchange radius of the logic unit b, and optimizing the layout positions of the logic unit b by using a simulated annealing algorithm.
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