JPWO2004046975A1 - Electronic circuit design timing improvement method, program and apparatus - Google Patents

Abstract

Improve the timing of electronic circuit design after logic design, cell placement and wiring processing. First, slack information representing the delay shortage and delay overtime obtained from the timing verification result in the electronic circuit design is input. Next, pay attention to slack information at the cell pins on the path that does not satisfy the timing constraint, and even if the cell is replaced to improve timing, other paths that pass through the replaced cell do not cause timing errors. Search as a candidate. Then, the cell searched as the target candidate is replaced with a cell satisfying the timing constraint, and the timing error is eliminated. Further, a search is made as a candidate for a net narrowed down based on a plurality of specified conditions from a net on the error path, and the timing is improved by making the line thick.

Description

  The present invention relates to an electronic circuit design timing improvement method, program, and apparatus for LSI and VLSI that are automatically designed by computer support, and in particular, checks timing errors for electronic circuit designs that have undergone logic design, cell placement, and wiring processing. The present invention relates to an electronic circuit design timing improvement method, program, and apparatus that are improved.

Conventionally, in LSI and VLSI computer-aided automatic electronic circuit design, after logic design, cell placement, and wiring processing have been completed, timing analysis of the automatically created electronic circuit design is performed and the analysis results are analyzed. ing.
In the analysis of the timing analysis result, if a path that does not satisfy the timing condition, for example, a path causing a racing error or an over delay error, is found, it causes an error in cells existing on the path. Cell needs to be identified and replaced to meet timing requirements.
However, in the conventional analysis of timing analysis results, it is possible to identify cells that exist on a route that does not satisfy the timing conditions, but which cells on that route can be replaced to improve timing. There is a problem of not knowing. For this reason, cells on a route that does not satisfy the timing condition are selected and exchanged at random, but another route that passes through the exchanged cell may cause a timing error, which limits the timing constraints of the entire circuit. It is necessary to repeat the cell exchange and the timing analysis many times before satisfying, and there is a problem that the processing load for timing improvement is large and takes time.

The present invention relates to a timing improvement method, a program, and a program capable of efficiently eliminating a timing error by identifying and changing a cell or net that does not satisfy a timing condition by using cell slack information obtained as a result of timing verification. An object is to provide an apparatus.
(Cell optimization)
The present invention relates to an electronic circuit design timing improvement method in which logic design, cell placement and wiring processing are completed.
An input step for inputting slack information obtained from the timing verification result in the electronic circuit design by the input unit;
Focusing on slack information in cell pins on routes that do not satisfy timing constraints by the cell search unit, even if cells are replaced to improve timing, other routes that pass through the replaced cells do not cause timing errors A cell search step for searching for cells as exchange candidates;
A cell replacement step of replacing a cell searched as an exchange candidate by a cell replacement unit with a cell satisfying a timing constraint;
It is provided with.
As described above, the present invention improves the timing error of the path that does not satisfy the timing constraint first focused by replacing the cell by paying attention to the slack information of the pin of the cell on the path that does not satisfy the timing constraint. In addition, the timing error is not caused in other paths passing through the replaced cell, and the timing error in the final stage of the electronic circuit design can be improved efficiently.
Here, for cell optimization to improve hold time error included in racing error,
In the input step, the slack value that is the margin value for the setup time check obtained from the timing verification result in the electronic circuit design and the slack value that is the margin value for the hold time check are input.
The cell search step searches for a cell having a positive slack value of a setup time check of all pins as a replacement candidate for a path causing a hold time error due to insufficient delay, as a replacement candidate,
In the cell exchange step, a cell searched as an exchange candidate is replaced with a cell having a long delay time.
For cell optimization to improve setup time error included in over delay error,
In the input step, enter the slack value that is the margin value for the setup time check and the slack value that is the margin value for the hold time check,
The cell search step searches for a cell having a positive slack value of a hold time check of all pins as a replacement candidate for a path causing a setup time error due to delay over,
The cell exchange step is characterized in that a cell searched as an exchange candidate is replaced with a cell having a small delay time.
In the net search step, the delay parameter of the cell searched as a replacement candidate is changed to the value of the cell after replacement, and then the net delay is provisionally calculated to determine the timing error. decide.
Thus, by repeating the verification on the cells searched as candidates, it becomes possible to improve only the most necessary circuit. In addition, by preparing a library of cell parameters with the same logic and different delay, cell replacement verification can be performed without actually replacing the cell, and finally, based on the changed macro information that is output at the same time Then, logic change, cell placement and wiring processing are performed.
(Net thick line 1)
The present invention relates to an electronic circuit design timing improvement method in which logic design, cell placement and wiring processing are completed.
An input step for inputting a slack value that is a margin value of a hold time check obtained from a timing verification result in electronic circuit design by an input unit;
A net search step for searching for a net having a pin having a positive slack value and satisfying a predetermined designated condition as a thickening candidate from nets on a path causing a setup time error due to delay delay by a net search unit. When,
A thickening step of replacing the wiring of the net searched as a thickening candidate by a thickening unit with a thick line with a small delay time;
It is provided with.
Here, in the net search step, a net having a net wiring length and a driver driving capability equal to or greater than the specified values is searched as a thickening candidate as a net satisfying the specified condition.
In this way, when the setup time error that is over-delayed is improved by reducing the delay by thickening the net, according to the present invention, the target net is limited by the net wiring length and the driver driving ability, and the entire path is viewed. In many cases, the net is not very effective, and as a result, the shortage of wiring channels is caused, and the increase in wiring capacity due to thick lines leads to an increase in delay as a result of a driver with a small driving capability. Is possible.
In the net search step, the net line capacity and line resistance of the net searched as a thickening candidate are changed to the thickened values, and then the net delay is provisionally calculated to determine the setup time error. To be a candidate. Thus, it is possible to improve only the most necessary net by repeating the verification for the net searched as a candidate. In addition, as a verification of net thickening, changing the wiring resistance and capacitance of the candidate net to values with thickening enables delay calculation without actually thickening the net, and the thick line that is output at the same time Finally, logic change, cell placement, and wiring processing are performed based on the network information.
(Net thick line 2)
The present invention relates to an electronic circuit design timing improvement method in which logic design, cell placement and wiring processing are completed.
An input step for inputting a slack value that is a margin value of a hold time check obtained from a timing verification result in electronic circuit design by an input unit;
A net search step for searching a net satisfying a predetermined specified condition as a thickening candidate from all nets on a path causing a setup time error due to delay delay by a net search unit;
A thickening step of replacing the wiring of the net searched as a thickening candidate by a thickening unit with a thick line with a small delay time;
It is provided with.
Here, the net search step, from the net that has caused the setup time error,
A net having a net wiring length, a driver driving capability, a net delay, a waveform dullness on the receiver side, and a fanout number larger than a specified value is searched as a thickening candidate. For this reason, the most effective improvement is expected in the selected error path among the paths causing the timing error, depending on the specified conditions of the wiring length, driver drive capability, net delay, receiver waveform dullness and fanout number. One possible net can be determined.
In the net search step, a predetermined number of upper worst paths having a large delay time are selected from the nets in which the setup time error has occurred, and the thick line candidate search is repeated. For this reason, the timing error can be improved with the minimum necessary net thickening by thickening the net from a path having a large improvement effect.
(program)
The present invention provides a program for improving the timing of electronic circuit design that has undergone logic design, cell placement, and wiring processing.
First, the program of the present invention for improving timing by cell optimization is stored in a computer.
An input step for inputting slack information obtained from a timing verification result in electronic circuit design;
Pay attention to slack information at the pin of a cell on a route that does not satisfy the timing constraints, and even if a cell is exchanged for timing improvement, a cell that does not cause a timing error in another route that passes through the exchanged cell is used as an exchange candidate. A cell search step to search;
A cell replacement step of replacing a cell searched as an exchange candidate with a cell satisfying a timing constraint;
And execute.
Moreover, the program of the present invention for improving the timing by thickening the net is stored in the computer.
An input step for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in electronic circuit design;
A net search step for searching for a net having a pin whose slack value is positive and satisfying a predetermined designated condition as a thickening candidate from nets on a path causing a setup time error due to delay over;
A thickening step for replacing the wiring of the net searched as a thickening candidate with a thick line with a small delay time;
Is executed.
Moreover, the program of the present invention, which is another form for improving the timing by thickening the net,
An input step for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in electronic circuit design;
A net search step for searching a net satisfying a predetermined designated condition as a thickening candidate from all nets on a path causing a setup time error due to delay over;
A thickening step for replacing the wiring of the net searched as a thickening candidate with a thick line with a small delay time;
Is executed. The details of the program of the present invention are basically the same as the timing improvement method.
(apparatus)
The present invention provides an apparatus for improving the timing of electronic circuit design that has undergone logic design, cell placement and wiring processing.
First of all, the device of the present invention for improving timing by cell optimization includes an input unit for inputting slack information obtained from timing verification results in electronic circuit design, and slack information at a cell pin on a path that does not satisfy timing constraints. Focusing on the cell search unit for searching for a replacement candidate for a cell that does not cause a timing error on another route that passes through the replaced cell even if the cell is replaced for timing improvement, and a cell searched for the replacement candidate And a cell replacement unit that replaces the cell with a timing constraint.
In addition, the device of the present invention that improves the timing by thickening the net has an input unit for inputting a slack value, which is a margin value of a hold time check obtained from a timing verification result in electronic circuit design, and a setup time error due to an over delay. A net search unit that searches for a net having a pin with a positive slack value and satisfying a predetermined specified condition from among nets on a waking path, and wiring of a net searched as a thick line candidate And a thickening section that replaces with a thick line with a small delay time.
In addition, the apparatus of the present invention as another form for improving timing by net thickening includes an input unit for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in electronic circuit design, and a delay overload. Delay time between the net search unit that searches for nets that satisfy the specified conditions as a thickening candidate from all nets on the path that has caused a setup time error due to And a thickening section that replaces the small thick line.
The details of the apparatus of the present invention are basically the same as the timing improvement method.

FIG. 1 is a block diagram of a functional configuration showing an embodiment of the present invention;
FIG. 2 is a flowchart of electronic circuit design to which the present invention is applied;
FIG. 3 is an explanatory diagram of hardware resources of a computer to which the embodiment of FIG. 1 is applied;
4 is a block diagram of the cell size optimization unit of FIG. 2;
Fig. 5 is a circuit diagram of a basic cell net generated by electronic circuit design;
6 is an explanatory diagram of a setup time check in the circuit of FIG.
FIG. 7 is an explanatory diagram of a hold time check in the circuit of FIG.
FIG. 8 is an explanatory diagram of an electronic circuit unit to which the cell size optimization process of FIG. 4 is applied and slack values;
FIG. 9 is an explanatory diagram of a method for calculating the setup slack value in FIG. 8;
FIG. 10 is an explanatory diagram of a method for calculating the hold slack value in FIG.
FIG. 11 is a flowchart of cell size optimization processing according to the present invention;
FIG. 12 is a flowchart of cell size optimization processing following FIG. 11;
FIG. 13 is a block diagram of the net thickening part of FIG. 2;
FIG. 14 is a flowchart of net thickening processing according to the present invention;
FIG. 15 is a flowchart of net thickening processing following FIG. 14;
FIG. 16 is a flowchart of another embodiment of net thickening processing according to the present invention;
FIG. 17 is a flowchart of net thickening processing following FIG. 16;

図７は、図５の回路におけるホールドタイムチェックのための時間を表わしたタイムチャートであり、図７（Ａ）〜（Ｄ）の波形は図６（Ａ）〜（Ｄ）と同じである。この場合、図６（Ｄ）のように、クロックＣＫ２についてＤＦＦ３２のクロック入力端子ＣＫにおけるクロック立ち上がりに対しホールドタイムＴｈｏｌｄが設定される。このホールドタイムＴｈｏｌｄは、クロックエッジに対しデータを保持する時間である。このホールドタイムチェックにあっては、図７（Ｅ）のような条件が成立すれば、図５の回路は正常に動作することができる。また図７（Ｅ）の条件から、ホールドタイムチェックにおけるマージンは次式で与えられる。

図８は本発明のホールドタイムエラーを改善するセル最適化及びセットアップタイムエラーを改善するセル最適化が適用される回路の具体例である。なお、説明を簡単にするため、ネットのディレイは０としている。図８において、回路の始点４８と終点５０の間に８個のセルＡ〜Ｈが配置されている。セルＡ〜Ｈのそれぞれは左下のブロック５２に示したパラメータを表示している。即ち、セルＡ〜Ｈの内部にセル名Ｘとセル自身のディレイｄを示している。またセルＡ〜Ｈの出力ラインの上部にセットアップスラック値ｓｘの値を示し、出力ラインの下側にホールドスラック値ｓｎを示している。更に終点５０には、この回路におけるセットアップ制約値及びホールド制約値を示している。このセットアップ制約値は、図６のタイミングチャートに示したように、ＭＡＸディレイを基に計算される。またホールド制約値は、図７のタイミングチャートに示したように、ＭＩＮディレイを基に計算される。この例ではセットアップ制約値を１２とし、ホールド制約値を８としている。また図８における各数値は時間の単位を持ち、例えばマイクロ秒の単位を持つことになる。図８の回路にあっては、始点４８と終点５０の間に次の３つのパスを持っている。
パス１（Ａ，Ｂ，Ｅ，Ｇ，Ｈ）
パス２（Ａ，Ｃ，Ｆ，Ｇ，Ｈ）
パス３（Ａ，Ｄ，Ｇ，Ｈ）
また、パスのディレイ時間を見ると
パス１＝９
パス２＝１０
パス３＝７
となる。したがって、パスディレイについて、パス２がＭＡＸパスでパスディレイが１０であり、パス３がＭＩＮパスでパスディレイが７となっている。
図９は、図８におけるセットアップスラックｓｘの計算手順の説明図である。このセットアップスラックｓｘは次式で算出される。
ｓｘ＝｛（セットアップ制約値−（終点側積算ディレイ））
−（始点側積算ディレイ） （１）
ここで図９のセルＡ〜Ｈには、左下のボックス５４に示すパラメータを数値で示している。即ち、セルＡ〜Ｈにはセル名Ｘとセルのディレイｄが示され、セルの出力ラインの上側にはセットアップスラックｓｘを示し、出力ラインの下側には始点４８からの積算ディレイを示している。
遅延オーバーによるセットアップエラーを判断するためのセットアップスラックの計算にあっては、パスディレイが最大となる矢印５６で示すパス２が問題になる。そこで、パス２を構成するセルＡ，Ｃ，Ｆ，Ｇ，Ｈについてセットアップスラックの具体的な計算例を見ると次のようになる。セットアップスラックは終点５０側から計算していくほうが分かり易い。いまセルＨに着目すると、
セットアップ制約値＝１２、
終点側積算ディレイ＝０
始点側積算ディレイ＝１０
であることから、スラック値は
ｓｘ＝１２−１０＝２
として算出される。
次のセルＧにあっては、
セットアップ制約値＝１２、
終点側積算ディレイ＝２
始点側積算ディレイ＝８
であることから、セットアップスラック値は
ｓｘ＝（１２−２）−８＝２
となる。
次のセルＦにあっては、
セットアップ制約値＝１２、
終点側積算ディレイ＝２＋１
始点側積算ディレイ＝７
であることから、セットアップスラック値は
ｓｘ＝（１２−２−１）−７＝２
となる。
次のセルＣは
セットアップ制約値＝１２、
終点側積算ディレイ＝２＋１＋２
始点側積算ディレイ＝５
であることから、セットアップスラック値は
ｓｘ＝（１２−２−１−２）−５＝２
となる。更にセルＡにあっては、
セットアップ制約値＝１２、
終点側積算ディレイ＝２＋１＋２＋３
始点側積算ディレイ＝２
であることから、セットアップスラック値は
ｓｘ＝（１２−２−１−２−３）−２＝２
となる。同様にして、残りのセルＢ，Ｅ，Ｄについてもセットアップスラックを計算することができる。
図１０は、図８の回路におけるホールドスラックの計算手順の説明図である。ホールドスラックはホールド制約値より大きい場合に余裕があることになるため、セットアップスラックとは計算が逆になる。即ち、ホールドスラックは次式で計算される。
Ｈｘ＝（始点側積算ディレイ）−｛（ホールド制約値）−（終点側積算ディレイ）｝
（２）
図１０のセルＡ〜Ｈにあっては、左下のボックス５８のように、セル内にセル名Ｘとセルのディレイｄを示し、出力ラインの上側にホールドスラックｈｘを示し、出力ラインの下側に始点４８からの積算ディレイＴｄを示している。またホールドスラックを利用するホールドタイムチェックにおけるホールドタイムエラーは、パスディレイが最小となる矢印６０で示すパス３（Ａ，Ｄ，Ｇ，Ｈ）について問題となる。そこで、パス６０のセルＡ，Ｄ，Ｇ，Ｈについてホールドスラックの具体的な計算例を示すと次のようになる。このホールドスラックの計算は、終点５０側から計算していくと分かり易い。まずセルＨにあっては
ホールド制約値＝８
始点側積算ディレイ＝７
終点側積算ディレイ＝０
であることから、この場合のセットアップスラックは
ｈｘ＝７−８＝−１
となる。
次のセルＧにあっては、
ホールド制約値＝８
始点側積算ディレイ＝５
終点側積算ディレイ＝２
であることから、ホールドスラックは
ｈｘ＝５−（８−２）＝−１
となる。
次のセルＤにあっては、
ホールド制約値＝８
始点側積算ディレイ＝４
終点側積算ディレイ＝２＋１
であることから、ホールドスラックは
ｈｘ＝４−（８−２−１）＝−１
となる。
更にセルＡにあっては
ホールド制約値＝８
始点終点側積算ディレイ＝２
終点側積算ディレイ＝２＋１＋２
であることから、ホールドスラックは
ｈｘ＝（２−８−２−１−２）＝−１
となる。
再び図８を参照するに、このようにしてセットアップタイムチェックにおいてＭＡＸディレイを基に計算されたセットアップスラック情報及びホールドタイムチェックにおいて、ＭＩＮディレイを基に計算されたホールドスラック情報が入力されたならば、ホールドタイムエラーを起こしている経路を対象にセル交換によるタイミング改善を行う。ホールドタイムエラーを起こしている経路については、その経路の遅延時間を大きくすることでタイミングを改善することができる。即ち、ホールドタイムエラーを起こしている経路に存在するセルを遅延時間の大きなセルに置き換えることにより、ホールドタイムエラーを解消することができる。この場合、セルの置き換えを行うと、置き換えを行ったセルを通過する別の経路についても遅延が変化する。したがって、置き換えるセルの選択を誤ると、ホールドタイムエラーを改善しようとした経路のホールドタイムエラーを改善することができても、セルの置き換えによって遅延が変化した別の経路に新たなタイミングエラーを生ずることがある。そこで本発明にあっては、セルのスラック情報を使用して置き換えることで、新たなタイミングエラーを生じさせない最適な置き換えセルを求める。具体的には、ホールドタイムエラーを起こしている経路に存在するセルのピンについて、セットアップタイムチェックで求められたセットアップスラックをチェックし、このセットアップスラックが所定値以上の正の値を持つセルを置き換え対象とする。このようにセットアップタイムスラックの大きなセル、即ち遅延時間の増加に対しディレイオーバーとなるセットアップタイムエラーに余裕のあるセルを置き換え対象とすることによって、遅延不足により生じていたホールドタイムエラーが改善され、一方、セットアップタイムチェックでは遅延時間の増加によりタイミング制約に対し厳しくなるが、セットアップタイムチェックにおいて、もともと余裕のあったセル、即ちセットアップタイムチェックのスラック値が正であったセルを対象としているため、セルの交換により遅延時間が増加しても、遅延オーバーによるセットアップタイムエラーを起こすことはない。
このホールドタイムエラーを改善するセル最適化処理を図８について具体的に説明すると、次のようになる。図８におけるパス１（Ａ，Ｂ，Ｅ，Ｇ，Ｈ）、パス２（Ａ，Ｃ，Ｆ，Ｇ，Ｈ）、及びパス３（Ａ，Ｄ，Ｇ，Ｈ）のうち、パスディレイが最小となるＭＩＮパスはパス３（Ａ，Ｄ，Ｇ，Ｈ）であり、トータルディレイが７となっている。このトータルディレイ＝７はホールド制約値＝８より小さいことから、ホールドエラーを起こしていることが判定される。そこで、ホールドエラーを起こしているパス３（Ａ，Ｄ，Ｇ，Ｈ）において、これを改善するための最適なセルとして、ホールドスラックｓｈが最小でセットアップスラックｓｘが最大となるセルを検索する。この場合、パス３（Ａ，Ｄ，Ｇ，Ｈ）にあっては、セルＡ〜Ｈの出力側のネットに示すホールドスラックｈｘは全て−１である。これに対しセットアップスラックｓｘはセルＤのネットが５と最大であり、最も余裕のあるネットであることが分かる。このため、ホールドエラーを解消するためにセルＤのディレイｄを１つ大きくしてＤ＝２＋１＝３とすると、セットアップスラックｓｘは１つ減って、ｓｘ＝５−１＝４となる。このようなセルＤのディレイｄを１つ増やした場合のパスのトータルディレイは８となり、ホールド制約値を満足することでホールドエラーが解消できる。同時に、トータルディレイ８はセットアップ制約値＝１２を超えないことから、セットアップエラーを生ずることはない。
次に、オーバーディレイによるセットアップタイムエラーを改善する場合について説明する。セットアップタイムエラーを改善するためのセルの交換についても、ホールドタイムエラーの改善とほぼ同様、セットアップスラック及びホールドスラックを計算した後にトータルディレイが最大となるＭＡＸパスについてトータルディレイがセットアップ制約値を超えている場合にセットアップタイムエラーを判定し、このセットアップタイムエラーを発生しているパス上のセルを対象に、セットアップスラックが最小でホールドスラックが最大となるセルを検索する。このようにして検索したセルについて、遅延時間の小さなセルに置き換えることによってトータルディレイを減らすことで、セットアップエラーを解消することができる。同時に、トータルディレイが減ることでホールド制約値に近づくが、ホールドスラック値が最大のネットを持つセルを交換していることから、ホールドタイムエラーを発生することはない。
図１１及び図１２は、図４のセルサイズ最適化部１８によるセルサイズ最適化処理の手順を示したフローチャートであり、このフローチャートが本発明によるセルサイズ最適化処理のためのプログラムを同時に表している。
図１１において、まずステップＳ１で全てのネットのホールドスラック値とセットアップスラック値を計算してファイルに保存する。続いてステップＳ２〜Ｓ７においてホールドタイムエラーを改善するセルサイズ最適化処理を行う。即ちステップＳ２でパスを選択して遅延時間を計算し、ステップＳ３でパス遅延時間とホールド制約値を比較し、ホールドタイムエラーを判定する。パス遅延時間がホールド制約値未満であればホールドタイムエラーとなり、ステップＳ４でホールドスラック値が最小で、セットアップスラック値が最大となるセルを仮候補に決定する。続いてステップＳ５で実際にセル交換を行わずにディレイ仮計算を行う。即ち仮候補となったセルについてそれより大きな遅延時間を持つセルの遅延パラメータをセルパラメータライブラリ２４から取得し、セルのディレイを変えることで、ディレイ仮計算を行い、セル交換後のパスのトータルディレイを求める。続いてディレイ仮計算の結果に基づいてステップＳ６でホールドタイムエラーが解消され、且つセットアップタイムエラーを起こさず、タイミング制約を満足するか否かチェックする。ステップＳ６でタイミング制約を満足すれば、ステップＳ７でステップＳ４で決定した仮候補を遅延時間増加の候補セルに決定する。ステップＳ６でタイミング制約条件を満たさない場合にはステップＳ１３で全パスの終了を判別するまで、ステップＳ２からの処理を繰り返す。尚、ステップＳ６でタイミング制約条件を満たさなかった場合にはステップＳ５において可能範囲で、更に仮候補セルの遅延時間を増加させてディレイ仮計算を行い、これによってタイミング制約を満たした場合にはステップＳ７で遅延時間を増加させるための候補セルに決定する。
一方、ステップＳ３でホールドタイムエラーが判定されなかった場合には図１２のステップＳ８〜Ｓ１２のセットアップタイムエラーを改善するセルサイズ最適化処理を行う。即ち、ステップＳ８でパス遅延時間とセットアップ制約値を比較し、セットアップ制約値を超えた場合にはセットアップタイムエラーと判定し、ステップＳ９に進む。ステップＳ９にあってはセットアップタイムエラーを起こしたパスに存在するセルを対象に、セットアップスラック値が最小で、ホールドスラック値が最大となるセルを仮候補に決定する。続いてステップＳ１０でセルパラメータライブラリ２４の参照で小さな遅延時間を持つ仮候補セルのパラメータを取得し、ディレイ仮計算を行う。このディレイ仮計算によるトータルディレイがセットアップ制約値による両方のタイミング制約を満たすか否かをステップＳ１１で判断し、タイミング制約を満たす場合にはステップＳ１２で遅延時間を減少される候補セルに決定する。またステップＳ１１でタイミング制約を満たさない場合にはステップＳ１３で全パスを終了するまでステップＳ２に戻って次のパスについて同様の処理を繰り返す。またステップＳ１１でタイミング制約を満たさない場合にはステップＳ１０に戻り、仮候補セルのさらに小さな遅延時間のパラメータに変更してディレイ仮計算を行って、タイミング制約を満たすかどうか判定する処理を繰り返しても良い。
図１３は、図１のネット太線化部２０の機能構成のブロック図である。このネット太線化部２０は、入力部４２、ネット検索部４４及び太線化部４６を備えている。入力部４２は電子回路設計におけるタイミング検証結果から得られたホールドタイムのスラック値を入力する。ネット検索部４４は遅延オーバーによりセットアップタイムエラーを起こしているパス上のネットの中からスラック値が正となるピンを持ち、且つ所定の指定条件を満たすネットを太線化候補として検索する。
このネット検索の指定条件としては
（１）ネット配線長
（２）ドライバの駆動能力
の２つを設定している。
太線化部４６はネット検索部４４で太線化候補として検索されたネットの配線を遅延時間を小さくするために太線に置き換える。
このような図１３のネット太線化におけるセットアップタイムエラーの改善はセットアップタイムエラーを生じたパスにおける正のホールドスラックを持つネットを対象に太線化して遅延時間を減少させる改善を図る。しかしながら、ホールドスラックが正となるネットを対象による太線化による遅延時間を増やすタイミング改善を行った場合、パス全体として見た時にあまり効果的でないネットを数多く改善対象としており、結果的に配線チャンネルの不足を招いたり、ディレイ削減を意図して太線行った事で配線容量の増加するため、駆動能力の小さいドライバではタイミング改善が適切に図れなくなる場合がある。
そこで図１３の実施形態にあっては太線化により遅延時間を削減させるネットとしてネットの配線長が所定値以上で、ドライバの駆動能力も所定値以上となるネットに制限することでホールドスラックのみにより改善ネットを検索した場合の問題を解消している。
図１４及び図１５は、図１３のネット太線化部によるネット太線化処理の手順を示したフローチャートであり、このフローチャートが同時にネット太線化処理のプログラムを表している。図１４において、ステップＳ１で全てのネットのホールドスラック値とセットアップスラック値を計算してファイルに保存する。続いてステップＳ２でパスを選択し遅延時間、即ちパスのトータルディレイを計算する。続いてステップＳ３でパス遅延時間をセットアップ制約値と比較し、セットアップ制約値以上であればセットアップタイムエラーと判定し、ステップＳ４でエラーパスとしてファイルに格納する。このようなステップＳ２〜Ｓ４のエラーパスの判定をステップＳ５で全パスが終了するまで繰り返す。次にステップＳ６でファイルに格納されたエラーパスをひとつ選択し、ステップＳ７でエラーパス上のネットをひとつ選択し、ステップＳ８でネットのホールドスラック値が正の値か否かチェックする。正であればステップＳ９でネット配線長が所定値Ｌｎより大きいかチェックし、大きければステップＳ１０でドライバ駆動能力が所定値Ｄｎ以上か否かチェックする。ドライバ駆動能力が所定値Ｄｎ以上であればステップＳ１１ですでに処理済みの同一ネットが存在するか否かの重複チェックを行った後、ステップＳ１２で太線化の仮候補ネットに決定する。
続いて図１５のステップＳ１３に進み、太線ネット情報ファイル２６から仮定した配線の太さによる配線容量Ｃと配線抵抗Ｒの値を取得し、仮候補ネットの太線化した値を変更してディレイ仮計算を行う。このディレイ仮計算により改善ネットが決定した時点で太線化を行うために配線処理まで戻って実際に配線をすることなく、ネット太線化後のタイミング状態を解析できる。続いてステップＳ１４でディレイ仮計算から得られたネット太線化後のパスのトータルディレイについてセットアップタイムチェックを行い、ステップＳ１５でパスのトータルディレイがホールド制約値以下となってセットアップタイムエラーが解消されたか否かチェックする。セットアップタイムエラーが解消されていれば、ステップＳ１６で現在の仮候補を太線化の候補ネットに決定する。セットアップタイムエラーが解消されていなければ仮候補は破棄し、ステップＳ１７でパス上の全ネットの終了の有無をチェックした後、図１４のステップＳ７に戻り、エラーパス上の次のネットについて同様の処理を繰り返す。図１５のステップＳ１７でパス上の全てのネットの処理が終了したならば、ステップＳ１８で全てパスについての処理の終了の有無をチェックし、終了していなければ図１４のステップＳ６に戻り次のエラーパスを選択し同様の処理を繰り返す。ステップＳ１８で全てのエラーパスについて処理が終了すると、ステップＳ１９で決定された候補ネットを対象にネットの太線化処理を行う。このネットの太線化処理は実際には図２のフローチャートに示したようにステップＳ９〜Ｓ１４における論理設計、セル配置、配線、タイミング解析、タイミング解析結果分析の処理を通じて行われる。
図１６及び図１７は、本発明におけるネット太線化処理の他の実施形態を示したフローチャートである。この実施形態にあっても基本的な構成は図１２のネット太線化部２０と同様、入力部４２、ネット検索部４４及び太線化部４６で構成されるが、ネット検索部４４における太線化するネットを絞り込む条件が異なっている。即ち、この実施形態にあってはセットアップタイムエラーが判定されたワーストパスの中から上位所定数のワーストパスを選択して、ネット太線化処理を行い、ワーストパスにおけるネット太線化の対象となるネットの絞込みの条件として
（１）ネット長
（２）ドライバ駆動能力
（３）ネットディレイ
（４）レシーバ側の波形鈍り
（５）ファンアウト数
の５つの条件を満足するネットを太線化候補ネットして太線化を行う。これによってひとつのエラーパスの中から、ひとつのネットのみが太線化候補として選択できる。これに対し図１４，図１５のネット太線化処理にあっては、エラーパス上のホールドタイムスラックの値が正となるネットが選択されることから、ひとつのエラーパスについて複数のネットが太線化される点で相違することになる。
そこで図１６及び図１７のフローチャートについてネット太線化処理を説明すると次のようになる。まずステップＳ１で全てのネットのホールドスラック値とセットアップスラック値を計算してファイルに保存した後、ステップＳ２でパスを選択して遅延時間、即ちパスのトータルディレイを計算した後、ステップＳ３でセットアップタイムエラーをパス遅延時間とセットアップ制約値の比較により判定する。セットアップタイムエラーが判定されると、ステップＳ４でこれをワーストパスとしてファイルに格納する。このステップＳ２〜Ｓ４の処理をステップＳ５で全パスが終了するまで繰り返す。次にステップＳ６でファイルに格納されたワーストパスの中からセットアップ制約値に対するパス遅延時間の差が大きい順にワーストパスをひとつ選択する。次にステップＳ７で選択したワーストパス上のネットをひとつ選択し、ステップＳ８でネット長が所定値Ｌｎより大きければステップＳ９に進む。ここでドライバ駆動能力が所定値Ｄｎより大きければステップＳ１０に進む。ここではネットディレイが所定値Ｔｎより大きければステップＳ１１に進む。ここではレシーバ側波形鈍りが所定値（Ｔｓｉｎ）ｎより大きければステップＳ１２に進む。ここではファンアウト数が所定値Ｆｎ以上であれば太線化をネットとし、ステップＳ１３で同一ネットが対象となっているかの重複チェックを行った後、ステップＳ１４で太線化仮候補ネットとして登録する。次に図１７のステップＳ１５で太線ネット情報２４から仮候補ネットについて仮定した配線の太さによる配線容量Ｃと配線抵抗Ｒを太線ネット情報ファイル２６から取得して、太線化した値に変更した後にディレイ仮計算を行う。次にステップＳ１６でディレイ仮計算の結果を用いたセットアップタイムチェックを行い、ステップＳ１７でセットアップタイムエラーが解消されればステップＳ１８で仮候補を太線化の候補ネットに決定する。続いてステップＳ１９でパス上の全ネットが終了するまで、図１６のステップＳ７に戻って同様の処理を繰り返す。ステップＳ１９でパス上の全ネットが終了すると、ステップＳ２０で所定数の上位ワーストパスが終了したか否かチェックし、終了していない場合には図１６のステップＳ６に戻り次の順位のワーストパスを選択して同様の処理を繰り返す。ステップＳ２０で所定数の上位ワーストパスの終了が判別されると、ステップＳ２１に進み決定された候補ネットを太線化する。このネット太線化は実際には図２のフローチャートに示したようにステップＳ９〜Ｓ１３に示す論理設計、セル配置、配線、タイミング解析及びタイミング解析結果分析を通じて処理されることになる。
尚、上記の実施形態にあっては図２のタイムチャートのようにステップＳ７とステップＳ８でセル最適化処理とネット太線化処理を順次行うようにしているが、セル最適化処理と太線化処理のいずれか一方を行うようにしても良い。また本発明は上記の実施形態に限定されず、その目的と利点を損なうことのない適宜の変形を含む。更に本発明は上記の実施形態に示した数値による限定は受けない。FIG. 1 is a block diagram of a functional configuration of an electronic circuit design system to which the timing improvement method of the present invention is applied. In FIG. 1, the electronic circuit design system includes a logic design unit 10, a cell placement unit 11, a wiring processing unit 12, a timing analysis unit 14, and a timing analysis result analysis unit 16, in addition to the above. Furthermore, a cell size optimizing unit 18 and a net thickening unit 20 are newly provided. A cell parameter library 24 and a cell replacement information file 22 are provided for the cell size optimization unit 18. The net thick line unit 20 is provided with a thick line net information file 26. Further, the logic design unit 10 is provided with an output file 28 for storing the created electronic circuit design data.
FIG. 2 is a schematic flowchart of a processing procedure in the electronic circuit design system of FIG. In FIG. 2, logic design based on the design information input in step S1 is performed, cell placement is performed in step S2, and wiring processing is further performed in step S3. Steps S1 to S3 are basic processes of electronic circuit design that is normally performed. Next, in step S4, the timing analysis is performed on the created electronic circuit design, and then the timing analysis result is analyzed in step S5. If a racing error or an over delay error occurs, the process proceeds to step S6. As part of the process associated with the cell placement adjustment, in the present invention, the slack-based cell optimization process in step S7 and the net thickening process on the worst path in step S8 are performed to improve the timing error. Plan. The slack-based cell optimization processing according to the present invention in step S7 inputs slack information obtained from the timing verification result in the electronic circuit design, and pays attention to the slack information at the cell pin on the path that does not satisfy the timing constraint. If the other path through the exchanged cell does not cause a timing error even if the cell is exchanged for timing improvement, this cell is searched as an exchange candidate, and the cell found as the exchange candidate is assigned a timing constraint. Replace with a cell that satisfies Specifically, cell candidates to be exchanged are searched based on slack information for a route causing a hold time error that causes insufficient delay, and the searched cell is replaced with a cell having a long delay time. Further, a cell as an exchange candidate is searched for a route causing a setup time error due to delay over, and the searched cell is replaced with a cell having a short delay time.
On the other hand, in the thickening process of the net on the worst path in step S8, a slack value which is a margin value of the hold time check obtained from the timing verification result in the electronic circuit design is input, and the setup time error due to the delay overrun The nets to be thickened to reduce the delay time are searched as thickening candidates from the nets on the path where the delay occurs, and the wiring of the searched net is replaced with a thick line with a short delay time. Furthermore, in the cell exchange and the net thickening in steps S7 and S8, the capacity and resistance associated with the cell parameter change and the net thickening without actually replacing the cell or thickening the net. A delay provisional calculation is performed by changing the value, and it is checked whether or not the timing error can be solved by cell exchange and net thickening. If the timing error can be eliminated, it is determined as a candidate for cell exchange or thickening. When cell replacement candidates and net thickening candidates are determined in steps S7 and S8, logical design and cell placement are finally performed in steps S9, S10, and S11 based on the cell change macro information and the thickening net information. After performing the timing analysis in step S12, the timing analysis result is analyzed in step S13. If the delaying error or the over delay error is not improved in step S14, the series of processing is terminated. . If a timing error is determined in step S14, the process returns to the cell arrangement adjustment in step S6 again, and the processing from step S7 is repeated.
The system of the present invention in FIG. 1 is realized by hardware resources of a computer as shown in FIG. 3, for example. In the computer of FIG. 3, the bus 101 of the CPU 100 includes a RAM 102, a hard disk controller (software) 104, a floppy disk driver (software) 110, a CD-ROM driver (software) 114, a mouse controller 118, a keyboard controller 122, and a display controller 126. The communication board 130 is connected. The hard disk controller 104 is connected to the hard disk drive 106 and is loaded with an application program for executing the electronic circuit design of the present invention. A necessary program is called from the hard disk drive 106 when the computer is started up, and is expanded on the RAM 102. To execute. A floppy disk drive (hardware) 112 is connected to the floppy disk driver 110 and can read and write to the floppy disk (R). A CD drive (hardware) 116 is connected to the CD-ROM driver 114, and data and programs stored on the CD can be read. The mouse controller 118 transmits an input operation of the mouse 120 to the CPU 100. The keyboard controller 122 transmits the input operation of the keyboard 124 to the CPU 100. The display controller 126 performs display on the display unit 128. The communication board 130 uses a communication line 132 including radio and communicates with other computers and servers via a network such as the Internet.
FIG. 4 is a block diagram of a functional configuration of the cell size optimization unit 18 of the present invention provided in the electronic circuit design system of FIG. The cell size optimization unit 18 includes an input unit 36, a cell search unit 38, and a cell replacement unit 40. The input unit 36 inputs slack information obtained from the timing verification result in the electronic circuit design. The cell search unit 38 pays attention to slack information in the cell pin on the route that does not satisfy the timing constraint, and even if the cell is exchanged for improving the timing, the other route passing through the exchanged cell does not cause a timing error. The cell is searched as an exchange candidate on the condition. The cell replacement unit 40 replaces the cell searched as an exchange candidate with a cell that satisfies the timing constraint. Further, a cell parameter library 24 and a cell replacement information file 22 are provided for the cell replacement unit 40 in order to perform temporary delay calculation for the cell replacement candidates. In the cell size optimizing unit 18 of the present invention as described above, cell replacement for eliminating a hold time error and cell replacement for eliminating a setup time error are performed using slack information.
The cell optimization process for eliminating the setup time error is performed according to the following procedure.
(1) A slack value that is a margin value for a setup time check obtained from a timing verification result in electronic circuit design and a slack value that is a margin value for a hold time check are input.
(2) For a path that has caused a setup time error due to delay over, a cell having a positive slack value of a hold time check of all pins as a replacement value is searched as an exchange candidate.
(3) Replace the cell searched as an exchange candidate with a cell having a short delay time.
The cell optimization process for eliminating the hold time error is performed according to the following procedure.
(1) Input a slack value that is a margin for a setup time check and a slack value that is a margin for a hold time check.
(2) With respect to a route that has caused a hold time error due to insufficient delay, a cell having a positive slack value of a setup time check for all pins equal to or greater than a predetermined value is searched for as an exchange candidate.
(3) Replace the cell searched as an exchange candidate with a cell having a long delay time.
Therefore, first, a case where the hold time error due to insufficient delay is improved will be described. As shown in the flowchart of FIG. 2, at the stage of performing the cell optimization process in step S7, the current timing verification for the already designed electronic circuit design is performed, and the slack information ( Margin value in timing verification). The slack information here is calculated based on the MAX delay in the setup time check, and is calculated based on the MIN delay in the hold time check. In both cases, the slack value has a positive value when there is a margin. Here, each slack information in the setup time check and the hold time check will be described.
FIG. 5 shows an example of a basic circuit generated by electronic circuit design, in which two stages of DFFs 30 and 32 serving as cells are connected. In FIG. 5, the delay time of the net from the clock terminal CK1 to the clock input terminal CK in the preceding DFF 30 is Tc1, the delay time of the net between the input D of the preceding DFF 30 and the subsequent input D is Td, It is assumed that the delay time from the clock terminal CK2 to the clock input terminal CK in the subsequent DFF 32 is Tc2. The parameters that are the targets of the setup time check in this case are as shown in FIGS. That is, CK1 in FIG. 6B has a delay time Tc1 with respect to the basic clock in FIG. Further, the signal change with respect to the input D of the DFF 32 in the latter stage of FIG. 6C has a delay time Td from the rising edge of the clock CK1. Further, the clock CK2 in FIG. 6D is input to the clock terminal CK of the DFF 32 with a delay time Tc2. Here, the setup time Tsetup of the clock CK2 in FIG. 6D is defined as a time for preparing data with respect to the clock edge. Even if the data arrives at a timing when the setup time Tsetup is shorter than this. , DFF32 will not operate. Here, if the condition as shown in FIG. 6E is satisfied during each time in the setup time check, the circuit of FIG. 5 operates normally without causing a setup error. Further, the margin in the setup time check given by the following equation is obtained from the condition of FIG.

FIG. 7 is a time chart showing the time for holding time check in the circuit of FIG. 5, and the waveforms in FIGS. 7A to 7D are the same as those in FIGS. In this case, as shown in FIG. 6D, the hold time Thold is set for the clock rise at the clock input terminal CK of the DFF 32 for the clock CK2. The hold time Thold is a time for holding data with respect to the clock edge. In the hold time check, if the condition shown in FIG. 7E is satisfied, the circuit shown in FIG. 5 can operate normally. Further, from the condition of FIG. 7E, the margin in the hold time check is given by the following equation.

FIG. 8 shows a specific example of a circuit to which the cell optimization for improving the hold time error and the cell optimization for improving the setup time error of the present invention are applied. For simplicity of explanation, the net delay is set to zero. In FIG. 8, eight cells A to H are arranged between the start point 48 and the end point 50 of the circuit. Each of the cells A to H displays the parameters shown in the lower left block 52. That is, the cell name X and the delay d of the cell itself are shown inside the cells A to H. The setup slack value sx is shown above the output lines of the cells A to H, and the hold slack value sn is shown below the output line. Further, the end point 50 shows a setup constraint value and a hold constraint value in this circuit. The setup constraint value is calculated based on the MAX delay as shown in the timing chart of FIG. The hold constraint value is calculated based on the MIN delay as shown in the timing chart of FIG. In this example, the setup constraint value is 12 and the hold constraint value is 8. Each numerical value in FIG. 8 has a unit of time, for example, a unit of microsecond. In the circuit of FIG. 8, the following three paths are provided between the start point 48 and the end point 50.
Pass 1 (A, B, E, G, H)
Pass 2 (A, C, F, G, H)
Pass 3 (A, D, G, H)
Also, if you look at the delay time of the path
Pass 1 = 9
Pass 2 = 10
Pass 3 = 7
It becomes. Therefore, regarding the path delay, the path 2 is the MAX path and the path delay is 10, and the path 3 is the MIN path and the path delay is 7.
FIG. 9 is an explanatory diagram of a calculation procedure of the setup slack sx in FIG. This setup slack sx is calculated by the following equation.
sx = {(setup constraint value− (end point side integrated delay))
-(Start point side integration delay) (1)
Here, in the cells A to H in FIG. 9, the parameters shown in the lower left box 54 are indicated by numerical values. That is, the cells A to H show the cell name X and the cell delay d, the setup slack sx is shown above the cell output line, and the integrated delay from the starting point 48 is shown below the output line. Yes.
In the calculation of the setup slack for determining the setup error due to the delay over, the path 2 indicated by the arrow 56 that maximizes the path delay becomes a problem. Therefore, a specific calculation example of setup slack for cells A, C, F, G, and H that constitute path 2 is as follows. It is easier to understand the setup slack from the end point 50 side. Now focusing on cell H,
Setup constraint value = 12,
End point side integration delay = 0
Start point side integration delay = 10
Therefore, the slack value is
sx = 12-10 = 2
Is calculated as
In the next cell G,
Setup constraint value = 12,
End point side integration delay = 2
Start point side integration delay = 8
Therefore, the setup slack value is
sx = (12-2) -8 = 2
It becomes.
In the next cell F,
Setup constraint value = 12,
End point side integration delay = 2 + 1
Start point side integration delay = 7
Therefore, the setup slack value is
sx = (12-2-1) -7 = 2
It becomes.
The next cell C is
Setup constraint value = 12,
End point side integration delay = 2 + 1 + 2
Start point side integration delay = 5
Therefore, the setup slack value is
sx = (12-2-1-2) -5 = 2
It becomes. In cell A,
Setup constraint value = 12,
End point side integration delay = 2 + 1 + 2 + 3
Start point side integration delay = 2
Therefore, the setup slack value is
sx = (12-2-1-2-3) -2 = 2
It becomes. Similarly, setup slack can be calculated for the remaining cells B, E, and D.
FIG. 10 is an explanatory diagram of a calculation procedure of hold slack in the circuit of FIG. Since the hold slack has a margin when it is larger than the hold constraint value, the calculation is reverse to the setup slack. That is, hold slack is calculated by the following equation.
Hx = (start point side integration delay) − {(hold constraint value) − (end point side integration delay)}
(2)
In the cells A to H in FIG. 10, as shown in the box 58 at the lower left, the cell name X and the cell delay d are shown in the cell, the hold slack hx is shown above the output line, and the lower side of the output line. Fig. 8 shows the integrated delay Td from the start point 48. Further, the hold time error in the hold time check using hold slack becomes a problem for the path 3 (A, D, G, H) indicated by the arrow 60 that minimizes the path delay. Therefore, a specific calculation example of hold slack for the cells A, D, G, and H of the path 60 is as follows. This hold slack calculation is easy to understand if it is calculated from the end point 50 side. First, in cell H
Hold constraint value = 8
Start point side integration delay = 7
End point side integration delay = 0
Therefore, the setup slack in this case is
hx = 7-8 = -1
It becomes.
In the next cell G,
Hold constraint value = 8
Start point side integration delay = 5
End point side integration delay = 2
So hold slack is
hx = 5- (8-2) =-1
It becomes.
In the next cell D,
Hold constraint value = 8
Start point side integration delay = 4
End point side integration delay = 2 + 1
So hold slack is
hx = 4- (8-2-1) =-1
It becomes.
In cell A,
Hold constraint value = 8
Start point / end side total delay = 2
End point side integration delay = 2 + 1 + 2
So hold slack is
hx = (2-8-2-1-2) =-1
It becomes.
Referring to FIG. 8 again, if the setup slack information calculated based on the MAX delay in the setup time check and the hold slack information calculated based on the MIN delay in the hold time check are input in this way. Then, the timing improvement by the cell exchange is performed for the route causing the hold time error. For a route causing a hold time error, the timing can be improved by increasing the delay time of the route. That is, the hold time error can be eliminated by replacing the cell existing in the path causing the hold time error with a cell having a long delay time. In this case, when a cell is replaced, the delay also changes for another route passing through the replaced cell. Therefore, if the cell to be replaced is selected incorrectly, even if the hold time error of the path for improving the hold time error can be improved, a new timing error is generated in another path whose delay has changed due to the cell replacement. Sometimes. Therefore, in the present invention, an optimum replacement cell that does not cause a new timing error is obtained by replacement using cell slack information. Specifically, the setup slack obtained by the setup time check is checked for the cell pin existing in the path causing the hold time error, and the setup slack replaces a cell having a positive value greater than or equal to a predetermined value. set to target. In this way, by setting a cell having a large setup time slack, that is, a cell having a margin in the setup time error that causes a delay over with respect to an increase in the delay time, the hold time error caused by the insufficient delay is improved. On the other hand, the setup time check becomes stricter with respect to timing constraints due to an increase in the delay time, but in the setup time check, since cells that originally had a margin, that is, cells with a positive slack value of the setup time check are targeted, Even if the delay time increases due to cell replacement, a setup time error due to over-delay will not occur.
The cell optimization process for improving the hold time error will be described in detail with reference to FIG. Among path 1 (A, B, E, G, H), path 2 (A, C, F, G, H), and path 3 (A, D, G, H) in FIG. The MIN path becomes path 3 (A, D, G, H), and the total delay is 7. Since this total delay = 7 is smaller than the hold constraint value = 8, it is determined that a hold error has occurred. Therefore, in the path 3 (A, D, G, H) in which a hold error has occurred, a cell having the smallest hold slack sh and the largest setup slack sx is searched as an optimum cell for improving this. In this case, in the path 3 (A, D, G, H), all the hold slacks hx shown in the nets on the output side of the cells A to H are -1. On the other hand, the setup slack sx has the largest net of the cell D as 5 and it is understood that it is the net with the most margin. Therefore, if the delay d of the cell D is increased by 1 and D = 2 + 1 = 3 in order to eliminate the hold error, the setup slack sx is reduced by 1 and sx = 5-1 = 4. When the delay d of the cell D is increased by one, the total delay of the path is 8, and the hold error can be solved by satisfying the hold constraint value. At the same time, since the total delay 8 does not exceed the setup constraint value = 12, no setup error occurs.
Next, the case where the setup time error due to the over delay is improved will be described. For cell replacement to improve setup time error, the total delay exceeds the setup constraint value for the MAX path where the total delay becomes the maximum after calculating setup slack and hold slack, in the same way as improvement of hold time error. If there is a setup time error, a setup time error is determined, and a cell on the path in which the setup time error has occurred is searched for a cell having the smallest setup slack and the largest hold slack. A setup error can be eliminated by replacing the searched cell with a cell having a small delay time to reduce the total delay. At the same time, the hold delay value approaches as the total delay decreases, but a hold time error does not occur because the cell having the net with the largest hold slack value is exchanged.
FIGS. 11 and 12 are flowcharts showing the procedure of the cell size optimization process by the cell size optimization unit 18 of FIG. 4, and this flowchart represents the program for the cell size optimization process according to the present invention at the same time. Yes.
In FIG. 11, first, in step S1, hold slack values and setup slack values of all nets are calculated and stored in a file. Subsequently, in steps S2 to S7, cell size optimization processing for improving the hold time error is performed. That is, in step S2, a path is selected and the delay time is calculated. In step S3, the path delay time and the hold constraint value are compared to determine a hold time error. If the path delay time is less than the hold constraint value, a hold time error occurs, and in step S4, a cell having the minimum hold slack value and the maximum setup slack value is determined as a temporary candidate. Subsequently, in step S5, delay provisional calculation is performed without actually exchanging cells. That is, for a cell that is a temporary candidate, a delay parameter of a cell having a delay time larger than that is obtained from the cell parameter library 24, and a delay delay calculation is performed by changing the delay of the cell. Ask for. Subsequently, based on the result of the preliminary delay calculation, it is checked in step S6 whether the hold time error is eliminated and the setup time error is not generated and the timing constraint is satisfied. If the timing constraint is satisfied in step S6, the temporary candidate determined in step S4 in step S7 is determined as a candidate cell for increasing the delay time. If the timing constraint condition is not satisfied in step S6, the processing from step S2 is repeated until the end of all paths is determined in step S13. If the timing constraint condition is not satisfied in step S6, the delay provisional calculation is performed by further increasing the delay time of the temporary candidate cell in the possible range in step S5. In S7, a candidate cell for increasing the delay time is determined.
On the other hand, if a hold time error is not determined in step S3, a cell size optimization process for improving the setup time error in steps S8 to S12 in FIG. 12 is performed. That is, in step S8, the path delay time is compared with the setup constraint value. If the setup constraint value is exceeded, it is determined that there is a setup time error, and the process proceeds to step S9. In step S9, a cell having the smallest setup slack value and the largest hold slack value is determined as a tentative candidate for cells existing in the path where the setup time error has occurred. Subsequently, in step S10, parameters of a temporary candidate cell having a small delay time are acquired by referring to the cell parameter library 24, and temporary delay calculation is performed. In step S11, it is determined whether or not the total delay based on the provisional delay calculation satisfies both timing constraints based on the setup constraint value. If the timing constraint is satisfied, a candidate cell whose delay time is reduced is determined in step S12. If the timing constraint is not satisfied in step S11, the process returns to step S2 until all paths are completed in step S13, and the same processing is repeated for the next path. If the timing constraint is not satisfied in step S11, the process returns to step S10, the delay candidate parameter is changed to a smaller delay time parameter, and temporary delay calculation is performed to determine whether the timing constraint is satisfied. Also good.
FIG. 13 is a block diagram of a functional configuration of the net thickening unit 20 of FIG. The net thickening unit 20 includes an input unit 42, a net search unit 44, and a thickening unit 46. The input unit 42 inputs the slack value of the hold time obtained from the timing verification result in the electronic circuit design. The net search unit 44 searches a net having a positive slack value from nets on a path in which a setup time error has occurred due to delay over, and searches for a net satisfying a predetermined specified condition as a thickening candidate.
The specified conditions for this net search are
(1) Net wiring length
(2) Driver driving capability
Two of these are set.
The thick line unit 46 replaces the net wiring searched as a thick line candidate by the net search unit 44 with a thick line in order to reduce the delay time.
The improvement of the setup time error in the net thickening shown in FIG. 13 aims to improve the delay time by thickening the net having the positive hold slack in the path in which the setup time error has occurred. However, when the timing improvement that increases the delay time due to thickening of the net with positive hold slack is performed, many nets that are not very effective when viewed as a whole path are targeted for improvement, and as a result, the wiring channel Insufficient wiring or increased wiring capacity due to thick lines intended to reduce delays may prevent timing improvements from being properly achieved with drivers with low driving capability.
Therefore, in the embodiment of FIG. 13, as a net for reducing the delay time by thickening, the net wiring length is limited to a predetermined value or more and the driving capability of the driver is limited to a net exceeding the predetermined value, so that only the hold slack is used. The problem when searching the improvement net is solved.
FIG. 14 and FIG. 15 are flowcharts showing the procedure of the net thickening process by the net thickening unit of FIG. 13, and this flowchart simultaneously represents the program for the net thickening process. In FIG. 14, in step S1, hold slack values and setup slack values for all nets are calculated and stored in a file. In step S2, a path is selected, and a delay time, that is, a total delay of the path is calculated. Subsequently, in step S3, the path delay time is compared with the setup constraint value, and if it is greater than or equal to the setup constraint value, it is determined as a setup time error, and in step S4, it is stored in the file as an error path. Such determination of error paths in steps S2 to S4 is repeated until all paths are completed in step S5. In step S6, one error path stored in the file is selected. In step S7, one net on the error path is selected. In step S8, it is checked whether the hold slack value of the net is a positive value. If it is positive, it is checked in step S9 whether the net wiring length is larger than the predetermined value Ln, and if it is larger, it is checked in step S10 whether the driver driving capability is equal to or larger than the predetermined value Dn. If the driver driving capability is equal to or greater than the predetermined value Dn, a duplicate check is performed to determine whether or not the same net that has already been processed exists in step S11, and then, in step S12, a temporary candidate net for thick line is determined.
Subsequently, the process proceeds to step S13 in FIG. 15, where the values of the wiring capacitance C and the wiring resistance R according to the assumed wiring thickness are obtained from the thick line net information file 26, and the thickened value of the temporary candidate net is changed to change the delay temporary value. Perform the calculation. The timing state after the thickening of the net can be analyzed without going back to the wiring process and performing the actual wiring in order to perform the thickening when the improvement net is determined by the delay temporary calculation. Subsequently, in step S14, a setup time check is performed on the total delay of the path after the net thickening obtained from the provisional delay calculation. In step S15, the total delay of the path is less than the hold constraint value, and the setup time error is eliminated. Check whether or not. If the setup time error has been eliminated, the current temporary candidate is determined as a thickening candidate net in step S16. If the setup time error has not been resolved, the temporary candidate is discarded, and after checking whether or not all nets on the path have ended in step S17, the process returns to step S7 in FIG. Repeat the process. If the processing of all nets on the path is completed in step S17 in FIG. 15, it is checked in step S18 whether the processing for all paths is completed. If not completed, the process returns to step S6 in FIG. Select an error path and repeat the same process. When the processing is completed for all error paths in step S18, net thickening processing is performed on the candidate net determined in step S19. The net thickening process is actually performed through the logic design, cell placement, wiring, timing analysis, and timing analysis result analysis in steps S9 to S14 as shown in the flowchart of FIG.
16 and 17 are flowcharts showing another embodiment of net thickening processing in the present invention. Even in this embodiment, the basic configuration is composed of the input unit 42, the net search unit 44, and the thick line unit 46 as in the net thick line unit 20 of FIG. The conditions for narrowing down the net are different. In other words, in this embodiment, a predetermined upper number of worst paths are selected from the worst paths for which a setup time error has been determined, net thickening processing is performed, and the network that is the target of net thickening in the worst path is selected. As a condition for narrowing down
(1) Net length
(2) Driver drive capability
(3) Net delay
(4) Waveform dullness on the receiver side
(5) Number of fan-outs
A net that satisfies the above five conditions is thickened as a thickening candidate net. As a result, only one net can be selected as a thickening candidate from one error path. On the other hand, in the net thickening process of FIGS. 14 and 15, since a net having a positive hold time slack value on the error path is selected, a plurality of nets are bolded for one error path. Will be different.
Accordingly, the net thickening process will be described with reference to the flowcharts of FIGS. 16 and 17 as follows. First, in step S1, hold slack values and setup slack values of all nets are calculated and stored in a file. Then, in step S2, a path is selected and a delay time, that is, a total delay of the path is calculated, and then setup is performed in step S3. The time error is determined by comparing the path delay time with the setup constraint value. If a setup time error is determined, it is stored in the file as the worst path in step S4. The processes in steps S2 to S4 are repeated until all paths are completed in step S5. Next, in step S6, one worst path is selected from the worst paths stored in the file in descending order of the path delay time difference with respect to the setup constraint value. Next, one net on the worst path selected in step S7 is selected. If the net length is larger than the predetermined value Ln in step S8, the process proceeds to step S9. If the driver driving capability is greater than the predetermined value Dn, the process proceeds to step S10. Here, if the net delay is larger than the predetermined value Tn, the process proceeds to step S11. Here, if the receiver-side waveform dullness is larger than a predetermined value (Tsin) n, the process proceeds to step S12. Here, if the number of fan-outs is equal to or greater than the predetermined value Fn, the thick line is set as a net. After checking whether or not the same net is the target in step S13, it is registered as a thick line temporary candidate net in step S14. Next, after acquiring the wiring capacitance C and the wiring resistance R based on the wiring thickness assumed for the temporary candidate net from the thick line net information file 26 in the step S15 of FIG. Perform preliminary delay calculation. Next, in step S16, a setup time check is performed using the result of the provisional delay calculation. If the setup time error is eliminated in step S17, the temporary candidate is determined as a thickening candidate net in step S18. Subsequently, the process returns to step S7 in FIG. 16 and the same processing is repeated until all nets on the path are completed in step S19. When all nets on the path are completed in step S19, it is checked in step S20 whether or not a predetermined number of upper worst paths have been completed. If not, the process returns to step S6 in FIG. Select and repeat the same process. If it is determined in step S20 that the predetermined number of upper worst paths have ended, the process proceeds to step S21 to thicken the determined candidate net. This net thickening is actually processed through logic design, cell arrangement, wiring, timing analysis, and timing analysis result analysis shown in steps S9 to S13 as shown in the flowchart of FIG.
In the above embodiment, cell optimization processing and net thickening processing are sequentially performed in step S7 and step S8 as in the time chart of FIG. 2, but cell optimization processing and thickening processing are performed. Either of these may be performed. The present invention is not limited to the above-described embodiments, and includes appropriate modifications that do not impair the objects and advantages thereof. Further, the present invention is not limited by the numerical values shown in the above embodiments.

Industrial applicability

As described above, according to the present invention, a setup error that is a hold time error or an over delay error is determined from a result of timing analysis of an electronic circuit design that has been subjected to logic design, cell placement, and wiring processing. In this case, the timing error can be efficiently eliminated by determining the replacement cell for the timing line on the error path using the comparison information obtained from the timing verification result.
In addition, when cells on the path causing a timing error are randomly selected and replaced, the intention to improve the timing error will cause a timing error on another path, but the error will not converge, In the present invention, since the optimum cell is selected and replaced so that the timing error improvement in the cell exchange does not cause a timing error on another path, the timing error can be efficiently eliminated.
In addition, the setup time error that becomes an over delay error is eliminated by reducing the delay time for thickening the wiring of the net, but at that time, the wiring channel is made by thickening the net that is the most effective and the minimum necessary. The timing error can be eliminated by thickening the net without causing shortage of the network.
Also, when the cell or net to be replaced is determined, whether or not the timing error is resolved by delay provisional calculation using the improved cell and net parameters without actually replacing the cell or thickening the net Since actual cell replacement and net thickening are performed after verification, it is possible to minimize cell replacement, net thickening, and repetition of timing verification and reduce processing time.

Claims (33)

In the timing improvement method of electronic circuit design after logic design, cell placement and wiring processing,
An input step of inputting slack information obtained from the timing verification result in the electronic circuit design by the input unit;
Focusing on slack information in cell pins on routes that do not satisfy timing constraints by the cell search unit, even if cells are replaced to improve timing, other routes that pass through the replaced cells do not cause timing errors A cell search step for searching for cells as exchange candidates;
A cell replacement step of replacing a cell searched as an exchange candidate by a cell replacement unit with a cell satisfying a timing constraint;
A timing improvement method comprising: In the timing improvement method of claim 1,
In the input step, a slack value that is a margin value of a setup time check obtained from a timing verification result in electronic circuit design, and a slack value that is a margin value of a hold time check are input,
The cell search step searches for a cell having a positive value of a slack value of a hold time check of all pins as a replacement candidate for a path causing a setup time error due to delay over,
The cell exchange step replaces a cell searched as an exchange candidate with a cell having a small delay time. In the timing improvement method of claim 1,
The input step inputs a slack value that is a margin value for a setup time check and a slack value that is a margin value for a hold time check,
The cell search step searches for a cell having a positive value of a slack value of a setup time check of all pins as a replacement candidate for a path causing a hold time error due to insufficient delay, as a replacement candidate,
The cell exchanging step is characterized in that a cell searched as an exchange candidate is replaced with a cell having a long delay time. In the timing improvement method of claim 1, the net search step determines a timing error by temporarily calculating a net delay after changing a delay parameter of a cell searched as a replacement candidate to a value of a cell after replacement. And determining a replacement candidate when no timing error occurs. In the timing improvement method of electronic circuit design after logic design, cell placement and wiring processing,
An input step of inputting a slack value that is a margin value of a hold time check obtained from the timing verification result in the electronic circuit design by the input unit;
Net search for searching for a net having a pin with a positive slack value and satisfying a specified condition as a thickening candidate from nets on a path causing a setup time error due to delay over by a net search unit. Steps,
A thickening step of replacing the wiring of the net searched as a thickening candidate by a thickening unit with a thick line with a small delay time;
A timing improvement method comprising: 6. The timing improvement method according to claim 5, wherein the net search step searches for a net having a net wiring length and a driver driving capability equal to or greater than a specified value as a thickening candidate as a net satisfying the specified condition. A characteristic timing improvement method. 6. The timing improvement method according to claim 5, wherein the net search step calculates the net delay after changing the line capacity and resistance of the net searched as a thick line candidate to a thick line value, and sets up a time error. And a timing improvement method characterized in that a net whose setup time error has been resolved is determined as a thick line candidate. In the timing improvement method of electronic circuit design after logic design, cell placement and wiring processing,
An input step of inputting a slack value that is a margin value of a hold time check obtained from the timing verification result in the electronic circuit design by the input unit;
A net search step for searching a net satisfying a predetermined specified condition as a thickening candidate from all nets on a path causing a setup time error due to delay delay by a net search unit;
A thickening step of replacing the wiring of the net searched as a thickening candidate by a thickening unit with a thick line with a small delay time;
A timing improvement method comprising: 9. The timing improvement method according to claim 8, wherein, in the net search step, a net wiring length, a driver driving capability, a net delay, a waveform dullness on the receiver side, and a fanout number are selected from the nets causing a setup time error. A timing improvement method, wherein a net having a value larger than a specified value is searched as a thickening candidate. In the timing improvement method according to claim 8, in the net search step, a predetermined number of upper worst paths having a large delay time are selected from the nets having a setup time error to search for thick line candidates. A timing improvement method characterized by repeating. 9. The timing improvement method according to claim 8, wherein the net search step changes a line capacity and a line resistance of a net searched as a thick line candidate to a thick line value, then temporarily calculates a net delay and sets up a setup time. A timing improvement method, wherein an error is determined, and a net in which a setup time error is eliminated is determined as a thickening candidate. In a computer program for improving the timing of electronic circuit design after logic design, cell placement and wiring processing,
An input step of inputting slack information obtained from a timing verification result in the electronic circuit design;
Pay attention to slack information at the pin of a cell on a route that does not satisfy the timing constraints, and even if a cell is exchanged for timing improvement, a cell that does not cause a timing error in another route that passes through the exchanged cell is used as an exchange candidate. A cell search step to search;
A cell replacement step of replacing a cell searched as an exchange candidate with a cell satisfying a timing constraint;
A program characterized by having executed. In the program of claim 12,
In the input step, a slack value that is a margin value of a setup time check obtained from a timing verification result in electronic circuit design, and a slack value that is a margin value of a hold time check are input,
The cell search step searches for a cell having a positive value of a slack value of a hold time check of all pins as a replacement candidate for a path causing a setup time error due to delay over,
The cell replacement step replaces a cell searched as a replacement candidate with a cell having a long delay time. In the program of claim 12,
The input step inputs a slack value that is a margin value for a setup time check and a slack value that is a margin value for a hold time check,
The cell search step searches for a cell having a positive value of a slack value of a setup time check of all pins as a replacement candidate for a path causing a hold time error due to insufficient delay, as a replacement candidate,
The cell replacement step replaces a cell searched as a replacement candidate with a cell having a small delay time. In the program according to claim 12, in the net search step, the delay parameter of the cell searched as the exchange candidate is changed to the value of the cell after the exchange, and then the net and gate delays are provisionally calculated to generate a timing error. A program for determining and determining a replacement candidate when no timing error occurs. In a computer program for improving the timing of electronic circuit design after logic design, cell placement and wiring,
An input step of inputting a slack value that is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design;
A net search step for searching for a net having a pin whose slack value is positive and satisfying a predetermined designated condition as a thickening candidate from nets on a path causing a setup time error due to delay over;
A thickening step for replacing the wiring of the net searched as a thickening candidate with a thick line with a small delay time;
A program characterized by having executed. The program according to claim 16, wherein the net search step searches for a net having a net wiring length and a driver driving capability equal to or greater than a specified value as a thickening candidate as a net satisfying the specified condition. Program to do. The program according to claim 16, wherein the net search step determines a setup time error by temporarily calculating a net delay after changing a wiring capacitance and a wiring resistance of a net searched as a thickening candidate to a thickened value. And determining a thick line candidate for a net from which a setup time error has been eliminated. In a computer program for improving the timing of electronic circuit design after logic design, cell placement and wiring processing,
An input step of inputting a slack value that is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design;
A net search step for searching a net satisfying a predetermined designated condition as a thickening candidate from all nets on a path causing a setup time error due to delay over;
A thickening step for replacing the wiring of the net searched as a thickening candidate with a thick line with a small delay time;
A program characterized by comprising: In the program according to claim 19, in the net search step, a net wiring length, a driver driving capability, a net delay, a waveform dullness on the receiver side, and a fanout number are designated from among the nets causing a setup time error. A program that searches for a net that is smaller than the set value as a thickening candidate. 20. The program according to claim 19, wherein the net search step selects a predetermined number of upper worst paths having a large delay time from the nets having a setup time error, and repeats the search for a thickening candidate. A program characterized by In the program according to claim 19, in the net search step, a net delay is temporarily calculated after changing the wiring capacitance and wiring resistance of the net searched as a thickening candidate to a thickened value, and a setup time error is generated. A program for determining and determining a net for which a setup time error has been eliminated as a thickening candidate. In an apparatus for improving the timing of electronic circuit design after logic design, cell placement and wiring processing,
An input unit for inputting slack information obtained from a timing verification result in the electronic circuit design;
Pay attention to slack information at the pin of a cell on a route that does not satisfy the timing constraints, and even if a cell is exchanged for timing improvement, a cell that does not cause a timing error in another route that passes through the exchanged cell is used as an exchange candidate. Cell search program to search,
A cell replacement unit that replaces a cell searched as an exchange candidate with a cell that satisfies the timing constraint;
A device characterized by comprising: In the device of claim 23,
The input unit inputs a slack value that is a margin value of a setup time check obtained from a timing verification result in electronic circuit design, and a slack value that is a margin value of a hold time check,
The cell search unit searches for a cell having a positive value of a slack value of a hold time check of all pins as a replacement candidate for a path causing a setup time error due to delay over, as a replacement candidate,
The cell exchange unit replaces a cell searched as an exchange candidate with a cell having a small delay time. In the device of claim 23,
The input unit inputs a slack value that is a margin value for a setup time check and a slack value that is a margin value for a hold time check,
The cell search unit searches, as a replacement candidate, a cell having a positive slack value of a setup time check of all pins for a route causing a hold time error due to lack of delay as a replacement candidate,
The cell switching unit replaces a cell searched as a replacement candidate with a cell having a long delay time. In the apparatus of claim 23, the net search unit determines a timing error by temporarily calculating a net delay after changing a delay parameter of a cell searched as a replacement candidate to a value of a cell after replacement, An apparatus for determining a replacement candidate when no timing error occurs. In an apparatus for improving the timing of electronic circuit design after logic design, cell placement and wiring,
An input unit for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design;
A net search unit that searches for a net having a pin having a negative slack value and satisfying a predetermined designated condition as a thickening candidate from nets on a path causing a setup time error due to delay over,
A thickening unit that replaces the wiring of the net searched as a thickening candidate with a thick line with a small delay time;
A device characterized by comprising: 28. The apparatus according to claim 27, wherein the net search step searches for a net having a net wiring length and a driver driving capability equal to or greater than a specified value as a thickening candidate as a net satisfying the specified condition. Device to do. 28. The apparatus according to claim 27, wherein the net search step determines a setup time error by temporarily calculating a net delay after changing a line capacitance and a line resistance of a net searched as a thick line candidate to a thick line value. And determining a net with the setup time error eliminated as a thick line candidate. In an apparatus for improving the timing of electronic circuit design after logic design, cell placement and wiring processing,
An input unit for inputting a slack value which is a margin value of a hold time check obtained from a timing verification result in the electronic circuit design;
A net search unit that searches a net satisfying a predetermined designated condition as a thickening candidate from all nets on a path causing a setup time error due to delay over,
A thickening unit that replaces the wiring of the net searched as a thickening candidate with a thick line with a small delay time;
A device characterized by comprising: In the device of claim 30, the net search unit designates a net wiring length, a driver driving capability, a net delay, a waveform dullness on the receiver side, and a fanout number from among the nets causing a setup time error. An apparatus for searching for a net larger than a set value as a thickening candidate. 30. The apparatus according to claim 30, wherein the net search unit selects a predetermined number of upper worst paths having a large delay time from the nets having a setup time error, and repeatedly searches for a thickening candidate. A device characterized by. In the apparatus according to claim 30, the net search unit changes a wiring capacitance and a wiring resistance of a net searched as a thick line candidate to a thick line value, and then temporarily calculates a net delay to generate a setup time error. An apparatus for determining and determining a net in which a setup time error is eliminated as a thick line candidate.

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