JP2715931B2 - Semiconductor integrated circuit design support method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit design support method, and more particularly to a semiconductor integrated circuit design support method applied to a semiconductor integrated circuit designed by automatic placement and routing.

[0002]

2. Description of the Related Art In recent years, with the improvement of semiconductor integrated circuit technology,
As the scale of LSIs and the complexity of LSIs have advanced, the degree of integration of semiconductor integrated circuits has tended to increase further. At present, automatic placement and routing of this type of semiconductor integrated circuit is performed by computer processing, but simulation is performed based on the resulting wiring length, and if the required placement and routing requirements are not met, The fact is that the placement and routing is performed again. As described above, the repetition of the placement and routing causes an increase in design man-hours, and hinders efficient design. As a countermeasure, before performing the actual placement and routing, a floor plan is performed to predict the wiring length, a simulation is performed based on the prediction, and when a circuit design that satisfies the requirements is completed, the actual placement is completed. Wiring is performed.

[0003] As a conventional semiconductor integrated circuit design support method, one method is proposed in Japanese Patent Application Laid-Open No. 2-264451. FIG. 3 is a flowchart showing a processing procedure of a conventional semiconductor integrated circuit design support method described in Japanese Patent Application Laid-Open No. 2-264451. In FIG. 3, first, in a processing step 33, a floor plan schematic diagram is created by hand, and in a processing step 34, the floor plan schematic diagram is input. Then processing step 35
In the above, a block conforming to the specification is picked up from standard blocks in a cell block stored in advance. In the processing step 36, data of the floor plan knowledge rule stored in advance is fetched, and in the processing step 37, it is determined whether or not the schematic diagram of the floor plan complies with the flour plan knowledge rule. If the rule is satisfied, the process proceeds to processing step 41, where a layout process is performed according to the rule, and the automatic placement and routing process ends. If they do not match, the process proceeds to processing step 38, where the processing of changing the arrangement of blocks, pads, and the like is performed until the rules are satisfied. Next, in a processing step 39, a flare plan diagram based on the result of the change in the processing step 38 is displayed on a graphic display or the like. In a processing step 40, the floor plan is checked and checked. Then, the processing including the correction / re-input after the processing step 34 is repeated. On the other hand, if it is determined in the processing step 40 that it is appropriate, the layout processing is performed in the processing step 41, and the automatic placement and routing processing ends.

[0004] In the above processing step 39, there is a grouping as a technique which is used for setting an optimal arrangement in order to obtain an optimal arrangement and wiring between blocks in accordance with the floor plan knowledge rule. This is because, on a logic circuit, circuit blocks having a strong connection relationship are grouped, and the result is given as a constraint to a placement and routing tool, placed close to each other, and the wiring between a plurality of circuit blocks included therein is set. It is a way to keep the length as short as possible. By this method, blocks having a strong connection relationship are grouped together, and an area to be arranged is determined by this. FIG. 4 is a schematic diagram illustrating an example of an arrangement relationship of grouped blocks arranged in a certain area 42. In FIG. 4, the grouped blocks a, b, c, and d are arranged in the region 42. In the case of this example, the predicted wiring length in this group is, for example, (L _X + L _y ). Is calculated as

[0005]

In the conventional semiconductor integrated circuit design support method described above, when estimating the wiring length, the half-perimeter of the rectangle surrounding the grouped blocks, that is, ( L _X + L _y ), the smaller the rectangle includes the block group, that is, the higher the block use rate within the group,
As a result, the predicted wiring length between the blocks included in the group is calculated to be short. However, if the block usage rate within the group is too high,
When performing the wiring processing, the arrangement of the blocks becomes congested and the wiring processing becomes difficult, and the number of detours increases, and the actual wiring length becomes longer. In the worst case, the wiring processing is partially performed. It can be impossible. In addition, if the designer sets the grouping area too large for fear of unwiring, blocks are not arranged close to each other, resulting in a redundant wiring length. As a result, the design cannot be satisfied. Therefore, there are drawbacks that these factors reduce the design accuracy of the semiconductor integrated circuit and require a great deal of time as design man-hours.

An object of the present invention is to provide a semiconductor integrated circuit design support apparatus which eliminates the above-mentioned disadvantages.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit design support method for performing a floor plan by an electronic computer. The method receives a data input of a logic circuit forming a semiconductor integrated circuit. A first processing step of referring to predetermined block data and performing a floor plan of a circuit component including a logic circuit block, a memory block, a power supply circuit, a pad, and the like; and an analysis result obtained by the first processing step. A second area for grouping the logic circuit blocks and setting an area where blocks included in each logic circuit block are arranged.
And a third step of extracting the half circumference of the area as a parameter by referring to the size of the area set in each logic circuit group in the second processing step.
And comparing the parameters with the floorplan parameters previously stored as a floorplan database and the correlation relating to the wiring length as a result of the actual placement and routing, and performing the grouping by the second processing step. If the validity is determined, and if it is determined that there is no validity, the process returns to the second processing step, and if it is determined that there is validity, the process proceeds to the next fifth processing step. And, in the fourth processing step, when it is determined that the grouping is valid, it is determined whether or not all necessary groupings are completed.
If the processing is not completed, the process returns to the second processing step. If the processing is completed, the processing proceeds to the next sixth processing step. And a sixth processing step of estimating the estimated wiring length when it is determined that all the groupings have been completed.

[0008] In the fourth processing step,
When it is determined that there is no validity, a warning that there is no validity may be displayed, and the process may return to the second processing step.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit design supporting method for performing a floor plan by an electronic computer. A first processing step of performing a floor plan of a circuit component including a logic circuit block, a memory block, a power supply circuit, a pad, and the like with reference to block data; A second processing step of grouping circuit blocks and setting an area where blocks included in each logic circuit block are arranged, and a size of an area set in each logic circuit group in the second processing step A third processing step of extracting a half circumference of the area as a parameter with reference to And the correlation between the floor plan parameters stored in advance as the floor plan database and the wiring length as a result of the actual placement and routing, and the validity of the grouping in the second processing step is determined. If it is determined that there is no validity, the fifth
And the fourth processing step proceeds to the seventh processing step when it is determined that there is legitimacy. In the fourth processing step, it is determined that the grouping is not valid. In this case, based on the floor plan database, the fifth processing step of presenting an appropriate grouping correction plan, and the grouping correction plan presented in the fifth processing step are requested by a designer. It is determined whether or not they match, and if it is determined that they do not match, the process returns to the fifth processing step or the second processing step. If it is determined that they match, the processing of step 7 is performed. A sixth processing step that shifts to a step, a case where it is determined that the grouping is valid in the fourth processing step, and a design in the sixth processing step. If it is determined that the request meets the requirements, it is determined whether or not all necessary groupings have been completed. If not, the process returns to the second processing step. The seventh processing step proceeds to the next eighth processing step, and the seventh processing step
And the eighth processing step of estimating the estimated wiring length when it is determined that all the necessary groupings have been completed.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flowchart showing a processing procedure in one embodiment of the present invention. In FIG. 1, first, in processing step 10, logic circuit data to be designed as a semiconductor integrated circuit is input. Next, in a processing step 11, the block data is read from a file 12 in which the block data constituting the logic circuit is stored, and the number of blocks included in the logic circuit and the connection relationship are read using the block data. , The number of pin pairs and the size of each block are analyzed. In the processing step 13, the blocks having a strong connection relationship are respectively divided into a plurality of block groups based on the analysis result in the processing step 11, and for each group group, a plurality of blocks included in the group group are determined. The area to be arranged is given as the size of the area. In this case, the shape is made to be variable by giving the area fixedly or by giving a half circumference of the area. Then, the arrangement position of the area of the group group on the chip is determined, or an arbitrary range is designated, and the area is designated to be arranged within the range, or the group is arranged on the chip. It is also possible to have the automatic placement and routing apparatus determine the placement position without specifying the position. In the processing step 14, parameters are extracted from the group group determined in this way. The parameters referred to here indicate the size and half circumference of the group group area. This parameter is temporarily stored in the file 15. Next, in the processing step 17, the parameters read out from the file 15 and the information on each block group already analyzed and obtained in the processing step 11 are stored in the file 16 in advance, and the floor plan results are stored in the file 16. An inquiry is made to a floor plan database showing the correlation between the results of the actual placement and routing. In this floor plan database, floor planning is performed based on various data, grouping is performed, a wiring length is predicted, parameters of each group are extracted, and thereafter, actual placement and routing are performed based on these data. The process is performed to extract the actual wire length,
The result includes the correlation between the estimated wiring length, the actual wiring length, and the grouping parameter. In the processing step 17, it is determined whether or not the grouping is appropriate by comparing with the contents of the floor plan database, and when it is determined that the grouping is inappropriate,
The result is displayed on the display 18 as a warning. In accordance with the warning, the process returns to the processing step 13 again, and the grouping processing is performed again through the processing steps 14 and 17. This grouping process is repeatedly performed until it is determined in step 17 that the grouping is appropriate. If it is determined in the processing step 17 that the grouping is appropriate, it is determined in the processing step 19 whether or not the grouping processing for all the group groups has been completed, and if not, the processing is performed again. Returning to step 13, grouping processing is performed on the next group. If all necessary grouping processes have been completed, the estimated wiring length is estimated in processing step 20.

FIG. 2 is a flowchart showing a processing procedure in the second embodiment of the present invention. In FIG. 2, first, in processing step 21, logic circuit data to be designed as a semiconductor integrated circuit is input. Next, in processing step 22, the block data is read from the file 23 storing the block data constituting the logic circuit, and the number of blocks included in the logic circuit and the connection relation are read using the block data. , The number of pin pairs and the size of each block are analyzed. In processing step 24, based on the analysis result in processing step 22, the blocks having a strong connection relationship are respectively divided into a plurality of block groups, and for each group group, a plurality of blocks included in the group group are determined. The area to be arranged is given as the size of the area. In this case, the shape is made to be variable by giving the area fixedly or by giving a half circumference of the area. Then, the arrangement position of the area of the group group on the chip is determined, or an arbitrary range is designated, and the area is designated to be arranged within the range, or the group is arranged on the chip. It is also possible to have the automatic placement and routing apparatus determine the placement position without specifying the position. In the processing step 25, parameters are extracted from the group group determined in this way. This parameter is temporarily stored in the file 26. Next, in processing step 28, the parameters read from the file 26 and the processing steps 2
The information about each block group obtained by analysis in step 2 is referred to a floor plan database stored in advance in the file 27 and a floor plan database showing the correlation between the results of actual placement and routing of the floor plan. Is done.
In this floor plan database, a floor plan is performed based on various data and grouping is performed.
The wiring length is predicted, the parameters of each group are extracted, and then the actual wiring length is extracted based on these data to extract the actual wiring length. And the result of obtaining the correlation between the grouping parameters. Processing step 2
In step 8, it is determined whether or not the grouping is appropriate by comparing with the contents of the floor plan database. If it is determined that the grouping is inappropriate, the process proceeds to processing step 29 and is appropriate. If determined to be, the process proceeds to processing step 31. Note that the above processing step 2
The contents of the processing steps up to the processing step 28 are:
This is the same as in the first embodiment. In processing step 29, in response to the determination that the grouping is inappropriate, the grouping is improved. In this improvement processing, adjustment is made based on the floor plan database to adjust the block area ratio in the group, or to modify the shape of the group area to a more appropriate one, and the correction plan is presented. Then processing step 30
In the above, it is determined whether or not the amendment is against the request of the designer. If the amendment is against the request, the process returns to the process step 29 to present another amendment, or Returning to step 24, the grouping process is performed again by repeating the above processing steps. This grouping process is repeatedly performed until it is determined in step 30 that the grouping is appropriate. If it is determined in the processing step 30 that the modification plan meets the requirement of the designer, it is determined in the processing step 31 whether or not the grouping processing for all the group groups has been completed. If the processing has not been completed, the flow returns to the processing step 24 again, and the grouping processing for the next group is performed. If all the necessary grouping processes have been completed, the estimated wiring length is estimated in processing step 31. Even in the case where it is determined in the processing step 28 that the grouping is appropriate, it is determined in the processing step 31 whether or not the grouping processing for all the group groups has been completed.
If not, the process returns to the processing step 24 again.
A grouping process is performed on the next group.

[0013]

As described above, the present invention relates to a grouping process which is performed to connect blocks having a strong connection relationship to a circuit including a plurality of logic circuits by wiring as short as possible. Correspondingly, by querying the grouping parameters according to the floorplan already obtained for various data and the floorplan database showing the correlation between the predicted wiring length and the actual wiring length due to the actual placement and routing, It is possible to perform more optimal grouping, improve the accuracy of the estimated wiring length, eliminate the loss of the design period of performing redesign after actual wiring, and reduce the design period. effective.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flowchart of a processing procedure in a first embodiment of the present invention.

FIG. 2 is a diagram showing a flowchart of a processing procedure in a second embodiment of the present invention.

FIG. 3 is a diagram showing a flowchart of a processing procedure in a conventional example.

FIG. 4 is a schematic diagram of grouping.

[Explanation of symbols]

 10, 21, 34 Data input processing 11, 22 Data analysis processing 12, 15, 16, 23, 26, 27 File 13, 24 Grouping processing 14, 25 Parameter extraction processing 17, 28 Floor plan determination processing 18 Warning display 19, 31 Grouping end determination processing 20, 32 Predicted wiring length estimation processing 29 Grouping improvement processing 30 Grouping improvement determination processing 33 Floorplan outline creation processing 35 Functional block extraction processing 36 Floorplan knowledge rule processing 37 Floorplan knowledge rule determination processing 38 Block pad change Processing 39 Floor plan output / message processing 40 Confirmation judgment processing 41 Layout processing 42 Area

Claims (3)

(57) [Claims] 1. A semiconductor integrated circuit design support method for performing a floor plan by an electronic computer, comprising the steps of: receiving data input of a logic circuit forming a semiconductor integrated circuit, referring to predetermined block data, and executing a logic circuit block, a memory block, A first processing step of performing a floor plan of a circuit component including a power supply circuit, a pad, and the like; and grouping the logic circuit blocks based on an analysis result of the first processing step. A second processing step of setting an area in which the included block is arranged; and referring to a size of the area set in each logic circuit group in the second processing step, using a half circumference of the area as a parameter. A third processing step to be extracted; the parameters; and a pre-stored as a floor plan database. When the validity of the grouping by the second processing step is determined by comparing the floor plan parameters and the correlation relating to the wiring length of the result of the actual placement and routing, and if it is determined that there is no validity, Is the second
Returning to the processing step, if it is determined that there is validity, the fourth processing step proceeds to the next fifth processing step; and in the fourth processing step, it is determined that the grouping is valid. In this case, it is determined whether or not all necessary groupings have been completed. If not, the process returns to the second processing step. If completed, the process proceeds to the next sixth processing step. A fifth processing step to be shifted; and a sixth processing step for estimating a predicted wiring length when it is determined in the fifth processing step that all necessary grouping is completed. Semiconductor integrated circuit design support method. 2. In the fourth processing step, when it is determined that there is no validity, a warning indicating that there is no validity is displayed, and the process returns to the second processing step.
13. The method for supporting design of a semiconductor integrated circuit according to the above. 3. A semiconductor integrated circuit design supporting method for performing a floor plan by an electronic computer, comprising the steps of: receiving data input of a logic circuit forming a semiconductor integrated circuit; A first processing step of performing a floor plan of a circuit component including a power supply circuit, a pad, and the like; and grouping the logic circuit blocks based on an analysis result of the first processing step. A second processing step of setting an area in which the included block is arranged; and referring to a size of the area set in each logic circuit group in the second processing step, using a half circumference of the area as a parameter. A third processing step to be extracted; the parameters; and a pre-stored as a floor plan database. When the validity of the grouping by the second processing step is determined by comparing the floor plan parameters and the correlation relating to the wiring length of the result of the actual placement and routing, and if it is determined that there is no validity, Shifts to a fifth processing step, and if determined to be valid, shifts to a seventh processing step; and in the fourth processing step, a determination is made that there is no validity of grouping. If determined, the fifth processing step of presenting an appropriate grouping correction plan based on the floor plan database; and the grouping correction plan presented in the fifth processing step is a designer Is determined to meet the requirements of
When it is determined that they do not match, the process returns to the fifth processing step or the second processing step, and when it is determined that they match, the sixth processing step proceeds to the processing step of 7 When it is determined in the fourth processing step that the grouping is valid, and when it is determined in the sixth processing step that the grouping meets the requirements of the designer, all necessary grouping is completed. It is determined whether or not the processing has been completed. If the processing has not been completed, the processing returns to the second processing step; if completed, the processing proceeds to the next eighth processing step, the seventh processing step; In a seventh processing step, when it is determined that all necessary groupings are completed, an eighth processing step of estimating a predicted wiring length is provided. Conductor integrated circuit design support method.