JP3576614B2 - Method and apparatus for searching minimum delay compensation point - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a method for searching for a minimum delay compensation point, for example, when designing a delay of a digital synchronous circuit.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for example, in the design of a logic circuit such as a gate array LSI, the propagation delay of a combinational circuit (hereinafter referred to as an inter-register circuit) that connects sequential circuits such as registers depends on a clock interval and a skew of a clock signal. It is designed to fit within the setup and hold time of the considered sequential circuit. The propagation delay of the inter-register circuit is approximated as the sum of the delay of each combinational logic gate included in the inter-register circuit and the media delay of the transmission path.
[0003]
If the delay time of a certain path does not fall within the setup / hold time between two sequential circuits connected to the path, the path becomes an error path. In this case, a case where the minimum delay time is shorter than the setup / hold time is called a minimum error, and a case where the maximum delay time is longer than the setup / hold time is called a maximum error.
[0004]
An increase in the design scale of a logic circuit such as a gate array LSI requires a large amount of design time for correcting such an error path, and the burden on the designer for this is extremely large. In this case, the designer generally corrects the maximum error path by changing a logic circuit or the like, and corrects the minimum error path by inserting a delay gate.
[0005]
[Problems to be solved by the invention]
By the way, paying attention to the insertion point of the delay gate for correcting the minimum error path, the minimum error path usually has a number of branches and also has a portion shared with other paths. In other words, the shared part may include a part of the max error path, and therefore, if a delay gate is inserted at random, the max error path is affected and a larger max error path is caused. There was a possibility.
[0007]
Further, when the insertion position of the delay gate for correcting the minimum error path is determined by automation, as a result of trial and error by the inventor, it has been found that the following problems must be cleared.
[0008]
That is, by correcting a certain minimum error path, there is a case where a minimum error path having a small amount of correction and having a part in common with the minimum error path cannot be corrected (mutual interference of the minimum error paths). In addition, correction of a certain minimum error path may increase the delay value of a path that does not cause an error, and may result in a maximum error path (maximization of an invisible path).
In order to prevent such a problem from occurring, it is important to determine which minimum error path has a higher priority and determine the branch point, and which part of each path to be corrected should be the branch point.
[0009]
An object of the present invention is to provide a technique for performing appropriate minimum delay compensation at the time of designing a delay of a digital synchronous circuit in view of the above problems.
[0010]
Means and Action for Solving the Problems
The method for searching for the minimum delay compensation point according to the present invention is a method in which, in a logic circuit having a plurality of paths, the maximum error path does not pass, the point on the uncompensated minimum error path, and the point closest to the end point register. Finds each as a minimum delay compensation point, and sets a priority on a point on the minimum error path having the same end point as the end point of the maximum error path from the plurality of minimum delay compensation points obtained as a highest priority point. In addition, priority is set in order of priority from a path having a large required compensation amount, and delay gates are inserted in order from a minimum compensation point having a high priority. In the minimum error path that passes through the searched minimum delay compensation point, the path that does not satisfy the compensation has its required compensation amount reduced to the value obtained by subtracting the delay amount of the inserted delay gate from the original necessary compensation amount. Preferably, it is updated.
[0011]
In the method of the present invention, the priority of the minimum error path is determined first, and then the point on the minimum error path that has not passed through the uncorrected minimum error path and that is closest to the end point register. The point is found as the minimum delay compensation point. Then, a delay gate for compensating for the minimum error path of the search source is inserted at the minimum delay compensation point. As a result, in the path that can be compensated for in the subsequent processing, all points on the path are recognized as points where delay gates cannot be inserted.
[0012]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a processing procedure diagram when a method for searching for a minimum delay compensation point according to an embodiment of the present invention is realized by a logic circuit design device having a predetermined operation analysis program.
In this method, as shown in FIG. 1, first, the priority order of the minimum error path for analyzing the insertion point of the delay gate is determined (S1). In this priority order determination, a point on the minimum error path having the same end point as the end point of the maximum error path is set as the highest priority point, and then the priority is determined by sequentially giving priority to the path requiring the larger compensation amount. Based on these conditions, the order of the minimum error path for analyzing the insertion point of the delay gate is determined.
[0013]
Next, a delay gate is set with (1) a point on the minimum error path not passing through the maximum error path, (2) a point on the uncompensated minimum error path, and (3) a point closest to the end point register as a minimum delay compensation point. Is analyzed (S2). More specifically, this processing is performed by sequentially searching for points satisfying the above definitions (1) to (3) from the end point register in the path in the direction of the start point register.
[0014]
After considering the influence on other minimum error paths passing through the analyzed point by a predetermined procedure (S3), a delay gate for compensating for the minimum error path of the search source is inserted at the point. As a result, in the subsequent processing, in the path that can be compensated, all points on the path are recognized as points where the delay gate cannot be inserted.
[0015]
At this time, in the minimum error path that passes through the insertion point of the found delay gate, for the path that does not satisfy the compensation, the delay amount of the inserted delay gate is subtracted from the original necessary compensation amount of the necessary compensation amount. Update to a value. This prevents excessive compensation of the once-compensated minimum error path, and prevents the minimum error path from becoming a maximum error path by the minimum compensation. Next, the processes in steps S2 and S3 are repeatedly executed until the compensation for all the minimum error paths is completed (S4).
[0016]
Next, the procedure of the present embodiment will be described more specifically with reference to FIGS. FIG. 2 is a diagram showing an example of a path configuration for explaining this procedure, and FIG. 3 is a diagram showing each path route in FIG.
[0017]
2 and 3, a minimum error path having a start register A and an end register C is a minimum error path {1}. Similarly, a minimum error path having a start register A and an end register D is a minimum error path. A path (2), a minimum error path having a start point register of A and an end point register of E is a minimum error path (3). 2 and 3, a path in which the start point register is B and the end point register is D, a path in which the start point register is B and the end point register is E are a maximal error path, and the other paths are normal paths. . Then, it is assumed that there are simply points (a) to (e) at which a delay gate can be inserted.
[0018]
In the following, different cases of the minimum error paths (1), (2), and (3) will be described according to the magnitude of the required compensation amount.
[0019]
(When the required compensation amount is (1) <(2) <(3))
In this case, the order of the minimum error paths for analyzing the insertion points of the delay gates is (3), (2), and (1). From the minimum error path (3), (a) Is determined. By inserting a delay gate that satisfies the compensation of the minimum error path (3) at point (a), the minimum error paths (3), (2), and (1) can satisfy the minimum compensation, respectively. It becomes.
[0020]
(When the required compensation amount is (3) <(2) <(1))
In this case, the order of the minimum error paths for analyzing the insertion points of the delay gates is (2), (3), and (1). From the minimum error path (2), (a) Is determined. By inserting a delay gate that satisfies the compensation of the minimum error path (2) at the point (a), the minimum compensation that satisfies both the minimum error paths (2) and (3) becomes possible.
[0021]
Since point (a) is also a point on the minimum error path (1), the necessary compensation for the minimum error path (1) is inserted to compensate for the minimum error path (2) from the original necessary compensation amount. The required compensation amount is updated to a value obtained by subtracting the delay amount of the delay gate.
[0022]
Next, from the minimum error path {circle around (1)}, (d) is determined as a delay gate insertion point. By inserting a delay gate having a delay value of the updated compensation amount of the minimum error path (1) at this point (d), the minimum error path (1) can perform satisfactory minimum compensation. .
[0023]
As described above, according to this embodiment, the influence on the maximum error path and the normal path is small, and all the minimum error paths can be appropriately compensated. Therefore, excessive delay compensation and leakage of points at which minimum compensation is to be performed are prevented, and appropriate minimum delay compensation can be performed.
[0024]
As described above, the present invention has been specifically described based on the preferred embodiments. However, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof. . For example, the path configuration examples shown in FIGS. 2 and 3 are merely examples, and the present invention is also effective in other path configurations.
[0025]
【The invention's effect】
As is clear from the above description, according to the present invention, (1) the maximum error path does not pass, (2) the point on the uncompensated minimum error path, and (3) the point closest to the end point register. Excessive delay compensation is prevented by searching for the point as the minimum delay compensation point, and the minimum error having the same end point as the end point of the maximum error path is selected from the plurality of minimum delay compensation points searched. The priority on the points on the path is determined as the highest priority point, and (2) the priority is determined by sequentially giving priority to the path requiring a large amount of required compensation, thereby preventing leakage of points to be subjected to minimum compensation. be able to.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a method for searching for a minimum delay compensation point according to an embodiment of the present invention.
FIG. 2 is a view showing an example of a path configuration for explaining an operation example of the embodiment.
FIG. 3 is a diagram showing each path route in FIG. 2;
[Explanation of symbols]
1 Start point register 2 End point register 3 Gate 4 Point where only the minimum error path passes 5 Point where only the maximum error path passes 6 Point where both the minimum error path and the maximum error path pass

Claims (4)

A method for searching an appropriate minimum delay compensation point at the time of delay design of a digital synchronous circuit by a logic circuit design device having a predetermined operation analysis program,
The minimum error path, its delay compensation amount and the maximum error path are input to the memory,
A processor acquires a minimum error path, a delay compensation amount thereof, and a maximum error path from the memory,
When the processor executes the operation analysis program, the highest priority is given to the minimum error path having the same end point as the end point of the maximum error path, and then the priority is determined in order from the minimum error path having the largest minimum delay compensation amount. error path is not through a point on the uncompensated minimum error path, and a minimum delay compensation point each closest point to end point register, the minimum delay compensation point on the higher priority minimum error path A method for searching for a minimum delay compensation point, which determines insertion points of delay gates in order . In the minimum error path that passes through the minimum delay compensation point that has been found, the path that does not satisfy the compensation updates its necessary compensation amount to a value obtained by subtracting the delay amount of the inserted delay gate from the original necessary compensation amount. 2. The method for searching for a minimum delay compensation point according to claim 1, wherein A logic operation circuit design apparatus for searching for a delay compensation point in a logic circuit having a plurality of paths,
A memory into which the minimum error path, its delay compensation amount and the maximum error path are input;
A processor that obtains a minimum error path and its delay compensation amount and a maximum error path from the memory,
By executing a predetermined operation analysis program, the processor gives priority to the minimum error path having the same end point as the end point of the maximum error path, and sets the priority in order from the path with the larger necessary compensation amount, and sets the maximum priority. error path is not through a point on the uncompensated minimum error path, and a minimum delay compensation point each closest point to end point register, the minimum delay compensation point on the higher priority minimum error path A logic operation circuit design apparatus characterized by sequentially determining insertion points of delay gates. In the minimum error path passing through the searched minimum delay compensation point, for the path that does not satisfy the compensation, the necessary compensation amount is subtracted from the original necessary compensation amount by the delay amount of the inserted delay gate. 4. The logic operation circuit designing apparatus according to claim 3, wherein the logic operation circuit design value is updated to a value.

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