JP3177218B2 - Function level design method of integrated circuit and recording medium recording function module model data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a function level design of an integrated circuit, and more particularly to synthesis of a pipeline circuit and a function module model used for the synthesis.

[0002]

2. Description of the Related Art In order to speed up the operation of electronic circuits,
A pipeline architecture is used. For information on how to pipeline common circuits,
A detailed explanation is given in "Principles of Digital Design" (author: Gajski, publisher: Prentice Hall).

The term "pipelining" means that a pipeline register is inserted on a signal path so that operations can be executed in parallel in each area divided by each pipeline register.

[0004] FIG. 14 is a diagram for explaining the basic concept of pipelining. In the figure, (a) is a given circuit diagram, and (b) is a diagram showing a result of the pipeline of the circuit of (a). In FIG. 14, reference numeral 310 denotes a symbol model of a computing unit (module), and 320 denotes a symbol model of a pipeline computing unit. In FIG. 14A, the positions where the pipeline registers can be inserted include a position 330 on the signal path between the arithmetic units 310 and 320 and a preset pipeline register insertion position 340 of the pipeline arithmetic unit 320. is there.

In FIG. 14B, four pipeline registers 350 are inserted in FIG. 14A. Each of the data data (i) to data (i + 6) propagates in each area divided by the pipeline register 350 in order for each clock. Pipeline register 35
The delay of each area separated by 0 is ds1,
Assuming that ds2 and ds3, the clock cycle of this circuit is
max (dsi), ie, delays ds1, ds2, ds3
Can be reduced to the maximum value.

[0006]

The number of pipeline stages is N.
Then, ideally, the clock cycle can be reduced to 1 / N of the original processing time. If the number of data is M, the original processing time (M +
The processing can be executed in a time of (N-1) / N. M
Is sufficiently larger than N, it is possible to realize a speedup of about N times by pipelining.

Conventionally, however, the insertion position of a pipeline register is limited to a position on a signal path between operation units or a position set in advance in a pipeline operation unit. For this reason, the delay of each area divided by the pipeline register cannot be equalized. The clock cycle becomes 1 / N of the original processing time when the delay is equal in each area divided by the pipeline register. Conventionally, the delay in each area can be equalized. As a result, the clock cycle could not be optimized sufficiently.

Further, since the layout of each module has already been designed and the values of the delay and the area are fixed, for example, in a region divided by the pipeline register, the delay has a margin with respect to the clock cycle. Even so, the settings of the delay and the area could not be changed.

As described above, conventionally, it has not always been possible to realize an optimum pipeline.

[0010] In view of the above problems, an object of the present invention is to make it possible to realize an optimal pipeline in synthesizing a pipeline circuit.

[0011]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is a computer- implemented method.
As a method of designing the function level of an integrated circuit by data processing, the pipeline circuit
A synthesizing process for synthesizing the functional module.
And a pipeline register
Represent multiple division lines that indicate the positions where
Using the function module model having a secant data, wherein
For the function module for which the function module model is
Out of the plurality of dividing lines represented by the dividing line data.
Is selected as the pipeline register insertion position.
And the step of selecting .

[0012] According to the present invention 1, the functional module model, its pipeline register allows insertion position
Is provided with the dividing line data representing a plurality of dividing lines indicated respectively, in the synthesis of the pipeline circuit, it is possible to select the position to insert a pipeline register from the position indicated by the dividing line. Therefore, the insertion position of the pipeline register can be optimized.

According to the second aspect of the present invention, the functional module model in the integrated circuit function level designing method according to the first aspect includes a delay representing a trade-off relationship between a delay and an area in a divided region divided by a dividing line. It is assumed that area data is provided, and the combining process includes the function
Module models are provided for the prepared function modules.
Then, the delay and the area in the divided area are calculated by the delay area data.
From the trade-off relationship between delay and area represented by data
Steps shall be included .

According to the second aspect of the present invention, the functional module model includes delay area data representing a trade-off relationship between delay and area in the divided area divided by the dividing line. ,
The delay and the area in the divided region can be set from the trade-off relationship between the delay and the area. For this reason,
Adjustment of the delay and area of the partial circuit is facilitated, and the delay and area of the entire pipeline circuit can be optimized.

Further, according to the third aspect of the present invention, the delay area data in the integrated circuit function level designing method according to the second aspect has at least a critical path delay in the divided region as a delay in the divided region. I do.

[0016] In the invention of claim 4, according to claim 1 of the present invention.
The function module model in the integrated circuit function level design method described above expresses a computing unit.

Further, solutions for the invention is taken of claim 5, as a method for performing the function level design of an integrated circuit by the computer processing, path from the connection relation of the functional module
A synthesizing process for synthesizing the pipeline circuit;
Is a functional module, and the pipe
The line register insertion position is fixed, and
In each area delimited by the position where the pline register is inserted
Area representing the trade-off relationship between delay and area
Using a functional module model with the data, before Symbol function
Module models are provided for the prepared function modules.
And separated by the pipeline register insertion position
The delay area data shows the delay and area in each region.
Set from the trade-off relationship between delay and area.
It includes a loop .

According to the fifth aspect of the present invention, since the functional module model includes delay area data representing a trade-off relationship between delay and area in the divided area divided by the pipeline register insertion position, , The delay and the area in the divided region can be set from the trade-off relationship between the delay and the area. Therefore, it is easy to adjust the delay and area of the partial circuit, and it is possible to optimize the delay and area of the entire pipeline circuit.

In the invention according to claim 6, the delay area data in the method of designing a function level of an integrated circuit according to claim 5 is defined as a delay in each region divided by a pipeline register insertion position, at least in this region. It has a critical path delay.

[0020] In the invention of claim 7, according to claim 5,
The function module model in the integrated circuit function level design method described above expresses a computing unit.

The present invention according to claim 8 is function module model data representing a function module used when performing synthesis of a pipeline circuit by computer processing in a function level design of an integrated circuit, wherein the pipeline register has A function module including dividing line data indicating a plurality of dividing lines each indicating an insertable position;
When synthesizing a pipeline circuit from connection relationships
The function for which the function module model data is prepared
Modules represented by the dividing line data
One of the divider lines is
A computer-readable recording medium on which functional module model data characterized by being selected as an input position is recorded.

According to the eighth aspect of the present invention, the functional module model data recorded on the computer-readable recording medium indicates the position where the pipeline register can be inserted.
Is provided with the dividing line data representing a plurality of dividing lines respectively, in the synthesis of the pipeline circuit, it is possible to select the position to insert a pipeline register from the position indicated by the dividing line. Therefore, the insertion position of the pipeline register can be optimized.

According to a ninth aspect of the present invention, there is provided function module model data representing a function module used when performing synthesis of a pipeline circuit by computer processing in a function level design of an integrated circuit. insertion position has determined, and a delay section data representing the trade-off relationship between the delay and the area of each region separated by the pipeline registers inserted position, pipelines from connection of functional modules
The function module model is
Pipes for the function modules for which
In each area divided by the line register insertion position
Delay and area represented by the delay area data
And a computer-readable recording medium on which function module model data is set, which is set based on a trade-off relationship with the function module model data.

According to the ninth aspect of the present invention, the functional module model data recorded on the computer-readable recording medium is the delay area data representing the trade-off relationship between the delay and the area in the divided area divided by the dividing line. With the provision, the delay and the area in the divided region can be set from the trade-off relationship between the delay and the area in the synthesis of the pipeline circuit. Therefore, it is easy to adjust the delay and area of the partial circuit, and it is possible to optimize the delay and area of the entire pipeline circuit.

[0025]

FIG. 1 is a diagram conceptually showing a functional module model according to an embodiment of the present invention. In the figure, (a) is a diagram showing a layout configuration of a functional module, (b) is a diagram showing symbols representing the functional module of (a) in a functional circuit diagram, and 10 is an input signal, 2
0 is an output signal, and 30 is a dividing line indicating a position where a pipeline register can be inserted. a1 to a5 are areas in the divided area divided by the dividing line 30, d1 to d5 are delays in the divided area divided by the dividing line 30,
That is, the time required for the signal to pass through the divided area.

The functional module shown in FIG. 1A has one or more dividing lines 30 into which pipeline registers can be inserted, and the position of each of the dividing lines 30 is Insertion is possible. In each divided region divided by the dividing line 30, the area ai and the delay di (i = 1 to 5) have a trade-off relationship. That is, the delay can be reduced by increasing the signal propagation speed by increasing the drive capability of the circuit in the divided region,
On the other hand, since the size of the transistor constituting the circuit increases, the area increases.

FIG. 1C is a graph showing a trade-off relationship between the area ai and the delay di in the divided region.
For example, when a delay value is given to a certain divided region, the minimum area operable within the delay value is obtained from the relationship shown in FIG. Further, when an area value is given, the minimum delay that can be realized within the area value is obtained from the relationship shown in FIG.

FIG. 2 is a diagram showing an example of an expression on a computer of the functional module model according to the present embodiment. The functional module model 100 includes terminal data 110 representing information on external terminals, functional data 120 representing internal operations, symbol data 130 representing symbols in a functional circuit diagram, dividing line data 140 representing information on dividing lines, and a It has delay area data 150 representing the relationship between delay and area. The function module model 100 shown in FIG. 2 corresponds to a multiplier.

As shown in FIG. 2, the dividing line data 140 represents a plurality of dividing lines line1 to line4 indicating positions where pipeline registers can be inserted. The circuit division of this functional module is performed by dividing lines line1 to line4.
This is done by inserting a pipeline register into any of

FIG. 3 is a diagram schematically showing information on a dividing line represented by the dividing line data 140 shown in FIG.
In FIG. 3, line1 to line4 are dividing lines, bl
ock1 to block5 are the respective division lines line1 to lin
divided areas divided by e4, a0 to a7, b0
b7 is an input terminal of this functional module, x0 to x14,
co is an output terminal of the functional module, and d0 to d22 are output terminals of the divided area block1 (the divided area block1).
2 input terminal).

Further, as shown in FIG.
Reference numeral 50 denotes a plurality of combinations of the delay and the area in each of the divided regions block1 to block5, thereby indicating a trade-off relationship between the area and the delay in each of the divided regions block1 to block5. For example, in the delay area data 150 of FIG. 2, in the divided area block1, when the area is 3.0, the delay from the terminal a0 to the terminal d0 is 2.0, and when the area is 4.0, the terminal b
This indicates that the delay from 1 to the terminal d0 is 1.6. Further, in the present embodiment, the delay of the divided area is represented by the largest delay among the paths of the divided area, that is, the delay of the critical path. For example, the delay of the divided region block1 is 2.3 when the area is 3.0.
(The critical path is a path from the terminal a1 to the terminal d1). When the area is 4.0, the critical path is 1.8 (a critical path is a path from the terminal a0 to the terminal d0). In the present embodiment, by preparing such delay area data 150, it becomes possible to flexibly select a solution in which the area and the delay of the divided region become more optimal.

FIG. 4 is a diagram showing a conventional function module model. As shown in FIG. 4, the conventional function module model 200 does not include division line data. Further, the delay data 240 shows only the delay value from the input terminal to the output terminal of this functional module, and the delay value is fixed. Further, the area data 250
Merely showed the area information of the entire functional module.

The use of the functional module model according to the present embodiment makes it possible to optimize the insertion position of the pipeline register, adjust the delay and area of the partial circuit, and optimize the delay and area of the entire pipeline circuit. Can be

The functional module model according to the present embodiment will be described more specifically taking an arithmetic unit as an example.

FIG. 5 is a circuit diagram of a carry look-ahead type multiplier. The multiplier shown in FIG. 5 is an array type multiplier configured by arranging a plurality of full adders FA in an array. A0 to A7 are each bit signal line of input A, B0 to B7 are each bit signal line of input B, X0 to X1
Reference numeral 4 denotes each output bit signal line.

The features of the functional module model according to the present embodiment are as follows: (1) a position where a pipeline register can be inserted, that is, a dividing line is shown; and (2) a circuit in a divided area divided by the dividing line. The trade-off between area and speed can be analyzed by adjusting the drive capability or the transistor size of the transistor.

When the multiplier shown in FIG. 5 is represented by the functional module model according to the present embodiment, eight dividing lines 3
1 to 38 can be set. The area of the circuit divided by the dividing lines 31 to 38 can be changed by adjusting the transistor size. For example, Fishburn et al., "TILOS: A Posynomial Programm
ing Approach to Transistor Sizing ", ICCad85, pp.326-
By using the transistor size optimizing method disclosed in U.S. Pat. No. 3,328,1985, it is possible to calculate the transistor size that minimizes the area when a predetermined delay is given. Therefore, by using this transistor size optimizing method while changing the delay, a trade-off relationship between the delay and the area as shown in FIG. 1C can be obtained.

FIG. 6 is a circuit diagram after the pipeline register is inserted into the multiplier shown in FIG. As shown in FIG. 6, the dividing line 36 is the insertion position 36 of the pipeline register.
The pipeline register 39 is inserted at the intersection of the insertion position 36A and each signal line.

The functional module model according to the present embodiment can be applied to arithmetic units other than multipliers, such as floating-point arithmetic units, adders, and dividers. Also,
The functional module model according to the present embodiment is applicable not only to the arithmetic unit but also to modules such as a storage circuit and a combinational circuit.

Next, a description will be given of a pipeline circuit synthesis method using a functional module model according to the present embodiment.

In the pipeline circuit synthesis according to the present embodiment, a pipeline register is actually inserted from a dividing line indicating a position where a pipeline register can be inserted in a functional module in which the above-described functional module model is prepared. It can be defined as a problem in which a position is selected, and a delay and an area in a divided region divided by a dividing line are set from the trade-off relationship.

Here, for example, the following problem is defined according to the design purpose. (Problem 1) The area of the pipeline circuit is minimized by giving the number of pipeline stages and the clock cycle as conditions.

FIG. 7 is an example of a pipeline circuit synthesizing method according to the present embodiment, and is a flowchart showing a processing procedure for giving a solution to the problem 1. The processing procedure shown in FIG. 7 will be described with reference to FIGS.

FIG. 8A shows a pipeline circuit to be synthesized, which is represented by a connection relationship between functional modules. 8, 41 to 45 are registers, 5
1 and 52 are multipliers and 53 is an adder. That is, FIG. 8A shows a circuit that outputs the sum of the product of the inputs A and B and the product of the inputs C and D as the output Y. FIG. 8B is a functional module model representing a multiplier, and FIG. 8C is a functional module model representing an adder. FIG. 8 (b),
In (c), each broken line represents a dividing line, and the number in each divided region divided by the dividing line represents the relationship between the delay and the area in the divided region. The number before “/” indicates the delay, and the number after “/” indicates the area. For example, “2.3 / 3” indicates that the divided area has a delay of 2.3.
Indicates that the area is 3.

For the pipeline circuit shown in FIG. 8A, the number of pipeline stages is 2, and the clock cycle is 1
3.0 is given as a condition. That is, by inserting pipeline registers, the space between the registers 41 to 44 and the register 45 is divided into two stages, the delay between the registers is reduced to 13.0 or less, and the area is minimized.

First, in step S11, the insertion position of the pipeline register and the delay and area in each divided area are initialized. Here, it is assumed that the dividing line 61 of the multiplier 51 and the dividing line 65 of the multiplier 52 are initially set as the insertion positions of the pipeline registers.
In addition, the delay and the area of each divided region are selected to have the minimum delay. That is, for the multipliers 51 and 52, 1.8 from the top of the divided area.
/ 4, 6/4, 4.4 / 4, and 6/9 are selected. With respect to the adder 53, 0.6 / 3,
It is assumed that 0.6 / 3 and 0.6 / 3 are selected.

Next, in step S12, the set pipeline register insertion position and the delay and area in each divided area are evaluated. The delay from the registers 41 and 42 to the dividing line 61 and the delay from the registers 43 and 44 to the dividing line 65 are 1.8, respectively, but the delay from the dividing line 61 to the register 45 and the dividing line 65
To the register 45 are 18.2 (= 6
+ 4.4 + 6 + 0.6 + 0.6 + 0.6), which is much longer than the given clock period of 13.0. At this time, the areas of the multipliers 51 and 52 are 21
(= 4 + 4 + 4 + 9), and the area of the adder 53 is 9
Since (= 3 + 3 + 3), the total area is 51.

Next, in step S14, the setting change of the pipeline register insertion position (S14a) or the setting change of the delay and area in the divided area (S14b) is performed. Here, it is assumed that the pipeline register insertion position is changed to the dividing line 62 of the multiplier 51 and the dividing line 66 of the multiplier 52. Then, in step S12, evaluation is performed. As a result, the delay from the registers 41 and 42 to the dividing line 62 and the delay from the registers 43 and 44 to the dividing line 66 are 7.8 (= 1.8 + 6), respectively.
And the delay from the dividing line 62 to the register 45 and the delay from the dividing line 66 to the register 45 are each 1
2.2 (= 4.4 + 6 + 0.6 + 0.6 + 0.6), both of which became equal to or less than the given clock cycle of 13.0.

Further, in order to make the total area smaller,
continue processing. In step S14, for example, the delay and area of the first divided region of the multiplier 51 are set to 1.8 / 4.
Is changed to 2.3 / 3. As a result of the evaluation in step S12, the delay from the registers 41 and 42 to the dividing line 62 increases to 8.3 (= 2.3 + 6), but the area of the multiplier 51 decreases to 20 (= 3 + 4 + 4 + 9), and the total area increases. Is 5
Decrease to zero.

Such steps S14 and S12
Is repeatedly executed until the end condition of step S13 is satisfied. As the end condition of step S13, the number of repetitions of steps S14 and S12 may be used, or the number of consecutive times that the evaluation of step S12 has not been improved may be used.

FIG. 9 is a diagram showing an execution result of the processing of FIG. 7 for the pipeline circuit of FIG. As shown in FIG. 9, a multiplier 5
The division line 63 of 1 and the division line 67 of the multiplier 52 are finally selected (shown by a chain line). The delay and area of each of the divided regions are 2.3 / 3, 6/4,.
4/4 and 10/6 are selected, and as for the adder 53,
、, 、, １ ／ are finally selected in order from the top of the divided area. As a result, the first-stage region α has a delay of 12.7 and an area of 22.0, and the second-stage region β has a delay of 13.0 and an area of 18.0. That is, it can operate at a clock cycle of 13.0 and has a total area of 4
A solution of 0.0 was obtained.

FIG. 10 shows a pipeline circuit using a conventional functional module model. As shown in FIG. 8A, the sum of the product of inputs A and B and the product of inputs C and D is output as output Y. FIG. 3 is a diagram illustrating a circuit that performs the following.

Conventionally, the insertion position of a pipeline register has been limited to a signal path between modules or to a register insertion position of a module in which a function module model having a fixed register insertion position exists.
For example, when a function module model representing the multipliers 81 and 82 has a fixed register insertion position,
As shown in FIG. 10, the positions where pipeline registers can be inserted are register insertion positions 91 and 82 of multipliers 81 and 82.
93, and four pipeline register insertion positions 92 and 94 between the multipliers 81 and 82 and the adder 83.

That is, since the degree of freedom of the insertion position of the pipeline register is low, the delay of each area divided by the pipeline register cannot be leveled sufficiently.
Therefore, the clock cycle cannot be sufficiently shortened. Further, since the values of the delay and the area of each module are fixed, the area cannot be reduced even if the delay of the area divided by the pipeline register has a margin with respect to the clock cycle. .

On the other hand, in the present embodiment, for example, FIG.
In the circuit (a), there are nine positions where pipeline registers can be inserted, and it is possible to perform more detailed optimization than before. That is, since the degree of freedom of the pipeline register insertion position is increased, the delay of each area divided by the pipeline register can be sufficiently leveled, so that the clock cycle can be sufficiently shortened. Further, since a trade-off between delay and area can be made in each divided area, the area of the area where the delay has a margin with respect to the clock cycle can be reduced, so that the area of the entire circuit can be reduced. Can be minimized.

In the process shown in FIG. 7, the insertion position of the pipeline register and the delay and area in each divided region may be evaluated using, for example, the following cost function Cost.

Cost = A * Σai + B * max (dsi) + C * p where ai is the area of each divided area divided by the dividing line, and Σai corresponds to the sum of the module areas. Dsi is the delay of each area divided by the pipeline register, and max (dsi) corresponds to the maximum value of the delay of each area, that is, the operable clock cycle. Also,
p is a value indicating whether or not the operable clock cycle is longer than a given clock cycle, and is “1” when it is larger, and “0” otherwise. Also, A,
B and C are parameters for weighting each term.
>> B >>A> 0 is set so as to satisfy the relationship.

Step S14 is repeatedly executed to minimize the cost function Cost by the successive improvement method. In step S14, one of step S14a and step S14b is selected by using a random number. When step S14a is selected, a division line adjacent to the division line currently selected as the pipeline register insertion position is selected as a new pipeline register insertion position. When step S14b is selected, an arbitrary divided region is selected by a random number, and the delay and area of this divided region are changed to an adjacent solution.

Note that a simulated annealing method can be applied instead of the successive improvement method.

As described above, according to the pipeline circuit synthesizing method shown in FIG. 7, the delay and the area of each divided region are optimized together with the selection of the insertion position of the pipeline register. The synthesis of the pipeline circuit can be performed so that the area is minimized with respect to the number of line stages.

The following problems are defined depending on the design purpose. (Problem 2) Given a clock cycle as a condition, obtain the number of executable pipeline stages, and minimize the area of the pipeline circuit for each pipeline stage number. In this case, a plurality of feasible solutions are obtained.

FIG. 11 is an example of a pipeline circuit synthesizing method according to the present embodiment, and is a flowchart showing a processing procedure for giving a solution to the problem 2.

In step S21, a critical path is determined for the pipeline circuit to be synthesized. Then, for each module on the critical path, the values of the delay and the area that minimize the delay are selected from the trade-off relationship between the delay and the area.

In step S22, a pipeline register is inserted into the critical path so that the delay of each area divided by the pipeline register is equal to or less than a given clock cycle. At this time, the number of pipeline stages is made as small as possible. The number of pipeline stages at this time is set as the minimum number of pipeline stages.

In step S10, the processing shown in FIG. 7 is executed. That is, the pipeline circuit to be synthesized can operate with the minimum number of pipeline stages set in step S22 and the given clock cycle,
In addition, the insertion position of the pipeline register and the delay and area in the divided area are determined so that the area is minimized.

In step S23, the number of pipeline stages is increased by one and set. Then, step S23
Using the number of pipeline stages set in step S10,
Execute That is, the pipeline circuit to be synthesized can operate with the number of pipeline stages set in step S23 and the given clock cycle, and
In order to minimize the area, the insertion position of the pipeline register, and the delay and area in the divided area are determined.

Steps S23 and S10 are
The process is repeatedly executed until the termination condition in step S24 is satisfied. In step S24, for example, if the minimum area of the pipeline circuit has not become smaller due to the increase in the number of pipeline stages from the result of step S10, the process may be terminated.

As described above, according to the pipeline circuit synthesizing method shown in FIG. 11, the optimal number of pipeline stages is determined while optimizing the delay and area of each divided region while selecting the pipeline register insertion position. Therefore, the synthesis of the pipeline circuit can be performed at a high speed and with a minimum area.

It is also possible to optimize the pipeline circuit by changing only the pipeline register insertion position without changing the delay and area of the divided region.
In this case, for example, the same processing as in FIG. 7 may be performed, but in step S14, only the step S14a, that is, the change of the pipeline register insertion position is performed.

FIG. 12 shows the result of optimizing the pipeline circuit only by changing the pipeline register insertion position. 12, an inverter 54 is inserted between the register 41 and the multiplier 51 and an inverter 55 is inserted between the multiplier 52 and the adder 53 in the pipeline circuit of FIG. As a result of the optimization, the multiplier 51 is set as the pipeline register insertion position.
And the dividing line 67 of the multiplier 52 are selected, and as a result, 12.8 is realized as the clock cycle.

If the pipeline register insertion positions of the multipliers 51 and 52 are fixed at the same position, the first stage region α and the second stage region β
The delays cannot both be 12.8. For example,
If the pipeline register insertion position is fixed to the second dividing lines 62 and 66 of the multipliers 51 and 52, the delay of the second stage region β is 17.2. On the other hand, the pipeline register insertion position is the third dividing line 6 of the multipliers 51 and 52.
If it is fixed at 3,67, the delay of the first stage area α will be 17.2.

As described above, it is also possible to optimize the pipeline circuit by changing only the pipeline register insertion position. In this case, the functional module model is
What is necessary is just to provide the dividing line data representing the dividing line, and the delay area data representing the trade-off relationship between the delay and the area in the divided region becomes unnecessary.

Further, the functional module model according to the present embodiment does not include the dividing line data, so that even if the insertion position of the pipeline register is fixed, the delay, the area, and the area in the region divided by the insertion position of the pipeline register are determined. If it is provided with delay area data representing the trade-off relationship of the above, it can be used for optimization of a pipeline circuit. In this case, for example, the same processing as that of FIG. 7 may be performed, and in step S14, only step S14b, that is, only the change of the delay / area may be performed.

FIG. 13 is a schematic diagram of a layout of a pipeline circuit device designed by the pipeline circuit synthesis method according to the present embodiment. In FIG. 13, 1A, 1
B is a block having the same function, and is a block 1A
Is composed of partial circuits 2A, 3A and 4A, and block 1B is composed of partial circuits 2B, 3B and 4B. Partial circuit 2A and partial circuit 2B, partial circuit 3A and partial circuit 3B, partial circuit 4
A and the partial circuit 4B correspond to each other and have the same function. However, in the block 1A, the partial circuit 3A
The pipeline register 5A is provided between the partial circuit 2B and the partial circuit 3B, whereas the pipeline register 5A is provided between the partial circuit 2B and the partial circuit 3B.
Is provided.

In the conventional pipeline circuit device, when there are a plurality of blocks having the same function, the insertion position of the pipeline register is the same in each block. On the other hand, in the pipeline circuit device according to the present embodiment, as shown in FIG. 13, blocks having the same function may have different insertion positions of pipeline registers. Further, in the pipeline circuit device according to the present embodiment, in the blocks having the same function, the sizes of the corresponding partial circuits may be different. Such a circuit device may not operate properly when the insertion position of the pipeline register is the same in each block or when the size of the corresponding partial circuit is the same. This is because the delay between pipeline registers changes, and if this delay exceeds the clock period, a timing error occurs.

[0076]

As described above, according to the present invention, in synthesizing a pipeline circuit, it is possible to optimize the insertion position of a pipeline register and to adjust the delay and area of a partial circuit, and Delay and area
Can be more optimized.

[Brief description of the drawings]

FIGS. 1A to 1C are diagrams conceptually showing a functional module model according to the present invention.

FIG. 2 is a diagram showing an example of an expression on a computer of a functional module model according to the present invention.

FIG. 3 is a diagram schematically showing information on a dividing line represented by the dividing line data shown in FIG. 2;

FIG. 4 is a diagram showing a conventional function module model.

FIG. 5 is a circuit diagram of a carry look-ahead type multiplier.

FIG. 6 is a circuit diagram after a pipeline register has been inserted into the multiplier shown in FIG. 5;

FIG. 7 is a flowchart illustrating an example of a pipeline circuit synthesis method according to the present invention.

FIGS. 8A to 8C are diagrams showing pipeline circuits to which the pipeline circuit synthesizing method according to the present invention is applied.

9 is a diagram showing an execution result of the processing of FIG. 7 for the pipeline circuit of FIG. 8;

FIG. 10 is a pipeline circuit using a conventional function module model.

FIG. 11 is a flowchart showing another example of the pipeline circuit synthesis method according to the present invention.

FIG. 12 is a diagram illustrating a result of optimizing a pipeline circuit only by changing a pipeline register insertion position;

FIG. 13 is a schematic diagram of a layout of a pipeline circuit device designed by the pipeline circuit synthesis method of the present invention.

FIGS. 14A and 14B are diagrams for explaining the basic concept of pipelining.

[Explanation of symbols]

 1A, 1B block 5A, 5B pipeline register 2A, 3A, 4A, 2B, 3B, 4B partial circuit 30 division line 31-38 division line 39 pipeline register 61-70 division line 100 function module model 140 division line data 150 delay Area data line1 to line4 Division line block1 to block5 Division area

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshiro Akino 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Masaharu Imai 2-15-30-2-2- Hibarigaoka, Takarazuka City, Hyogo Prefecture 404 (72) Inventor Yoshinori Takeuchi 2-14-3-201 Shibahara-cho, Toyonaka-shi, Osaka

Claims (9)

(57) [Claims] By 1. A computer processing, a method of performing the function level design of an integrated circuit, the connections of the function module, if the pipeline circuit
Comprising a synthesis process, wherein the synthesis process represents a functional module, and
Multiple dividing lines, each indicating a position where a register can be inserted
Using a functional module model having division line data representing the function module, wherein the functional module model is prepared
For the plurality of dividing lines represented by the dividing line data
One of them is the position where the pipeline register is inserted.
A function level design method for an integrated circuit, comprising the step of selecting a function level. 2. The method for designing a function level of an integrated circuit according to claim 1, wherein the function module model includes delay area data representing a trade-off relationship between delay and area in a divided region divided by a dividing line. It is those who are, the synthetic
The processing is performed on a functional module in which the functional module model is prepared.
, The delay and the area in the divided region, the delay plane
From the trade-off relationship between delay and area
Functional level design method for an integrated circuit comprising the steps of a constant. 3. The integrated circuit function level designing method according to claim 2, wherein the delay area data has at least a critical path delay in the divided region as a delay in the divided region. Function level design method for integrated circuits. 4. The method according to claim 1, wherein the functional module model represents an arithmetic unit. By 5. The computer processing, a method of performing the function level design of an integrated circuit, the connections of the function module, if the pipeline circuit
Comprising a synthesis process, wherein the synthesis process represents a functional module, and
Register insertion position is fixed, and
In each area delimited by the register insertion position
Delay area data showing the trade-off relationship between delay and area
Using a functional module model having a functional module model, wherein the functional module model is prepared
Are separated by the pipeline register insertion position.
The delay and area in each of the obtained
From the trade-off relationship between delay and area represented by data
A method for designing a function level of an integrated circuit , comprising the steps of : 6. The function level designing method for an integrated circuit according to claim 5, wherein said delay area data is at least a critical path delay in this area as a delay in each area divided by a pipeline register insertion position. A method for designing a function level of an integrated circuit, comprising: 7. The method according to claim 5, wherein the functional module model expresses an arithmetic unit. 8. A function module model data representing a function module used when performing synthesis of a pipeline circuit by computer processing in a function level design of an integrated circuit, wherein a position where a pipeline register can be inserted is specified. Show
Includes a division line data representing a plurality of dividing lines, the connection relation of functional modules, if the pipeline circuit
When performing the processing, the function module in which the function module model data is prepared is prepared.
Table, a plurality of segments represented by the dividing line data.
One of the split lines is a pipeline register insertion
A computer-readable recording medium in which function module model data is selected as a position . 9. A function module model data representing a function module used when performing synthesis of a pipeline circuit by computer processing in a function level design of an integrated circuit, wherein an insertion position of a pipeline register is determined. , if provided with a delay area data representing the trade-off relationship between the delay and the area of each region separated by the pipeline registers inserted position, the connection relation of functional modules, the pipeline circuit
When performing the processing, the function module in which the function module model data is prepared is prepared.
Module, depending on the pipeline register insertion position.
The delay and area in each of the regions separated by the
From the trade-off relationship between delay and area
A computer-readable recording medium that the functional module model data is recorded, characterized in that the constant.