JPH02162914A - Digital signal processing processor - Google Patents

Abstract

PURPOSE:To save useless operation to suppress required arithmetic quantity effectively and to make the processing time efficient by adopting the constitution such that a minimum distortion is compared with the result of calculated distortion for each cycle at the calculation of distortion between blocks and a number of a block giving the minimum distortion is stored. CONSTITUTION:The result of accumulation supplied from an output path 62 of an accumulator 7 via a branched output path 105 and an output data supplied from a minimum distortion register 10 via an output path 106 are compared for each cycle by a comparator 11. The accumulation is executed for a number of times provided in a repeat counter 9 and when the accumulation is finished normally, the write update of a value of an accumulation register 8 to a minimum distortion register 10, the write update of a value of a block counter 12 to a minimum distortion position register 13 and the control of the block counter 12 by an increment control signal are implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a digital signal processor.

[Conventional technology]

Figure 4 shows, for example, the 1986 International Conference on Acoustics, Speech and Signal Processing (ICASSP86) Proceedings P401'A30NS.
FLOATING-POINT5IGNAL PR
OCESSOR VLSI''l: is a simplified block diagram illustrating the configuration of the described conventional digital signal processing processor.

In the figure, (1) is an instruction memory that stores instruction words;
(2) outputs the address of the instruction memory (1) to the output path (51
), the program counter (3) decodes the instruction word supplied from the instruction memory (1) via the output path (52) and outputs it to the program φ counter (2) and the arithmetic unit, etc. to the output path (53). (4) is an internal data memory that stores calculation data; (5) is an internal data memory that transfers read data from the internal data memory (4) via an output path (54); (6) is a multiplier that multiplies the input data supplied from the data bus (5) via the output path (55), and (7) is an accumulator 1.1 that performs accumulation. (8) is an accumulation register for holding the accumulation result, and (9) is a repeat counter for repeating the same instruction multiple times.

(63) is the repeat counter (9) and data bus (5)
An input/output bus (64) connects the data supplied from the multiplier (6) via the output path (56) and the data supplied from the data bus (5) via the output path (57). A selector that inputs and outputs data to the accumulator (7) via an output path (58), and a register (65) for accumulating the output data supplied from the data bus (5) via the output path (59). (8) to output path (60
) and supplies the output data to the accumulator via an output path (61), and (66) is an output path that transmits a control signal for the repeat counter (9).

Next, the operation will be explained. Program φ counter (2
) via the output path (51), the instruction word read from the instruction memory (1) is input to the instruction execution control unit (3) via the output path (52).

The instruction execution control section (3) sends control signals to each section via the output path (53) based on the decoded instructions to control operations.

The internal data memory (4) reads up to two pieces of data via the output path (54) onto the data bus (5) and the multiplier (
6) outputs the multiplication result of two input data supplied from the data bus (5) via the output path (55) as output data.

The selector (64) connects the multiplier (5) to the output path (56)
Output data and data path (5) fed through
, one of the output data supplied via the output path (57) is selected.

The selector (65) also outputs output data supplied from the data reference bus (5) via the output path (59) and output data supplied from the accumulation register (8) via the output path (60). Choose one.

The accumulator (7) performs an addition operation between the output data supplied from the selector (64) via the output path (58) and the output data supplied from the selector (65) via the output path (61), The calculation result is output to the output path (
62) to the accumulation register (8).

Note that the same instruction such as the above-mentioned accumulation can be repeated the number of times set in the repeat counter (9) by the output data of the data bus (5) supplied via the input/output path (63).

In accordance with this configuration, the flowchart in FIG. 6 shows the operation for detecting a block with the minimum distortion from block A of a certain data string shown in the data relationship diagram in FIG. 5 and M blocks to be searched.

The amount of distortion is calculated using equation (1).

dk-Σ (yhh-Xb) ""'
(1) &-1 Here, Ni block A
yi) K-1~M M and W are fixed integer values.

That is, the output data of xkn)'lh read from the data memory (4) of each block is accumulated by the number of data (step 5T6-1.6-2), and the After obtaining all M distortions, perform a distortion comparison,
The minimum distortion and the block number resulting in the minimum distortion are determined (step 5T6-3).

In this case, since the digital signal processing processor having the configuration shown in FIG.
M) times, and further M times are required for comparison and updating processing to obtain the minimum distortion and the number of the block that results in the minimum distortion. As a result, if one machine cycle is t, the processing time is t
(MXW+M).

[Problem to be solved by the invention]

Since conventional digital signal processing processors are configured as described above, for example, when detecting a block with the minimum distortion from among a block of a certain data string and M blocks to be searched, Since the distortion is determined, the distortions are further compared, and the block number (position) with the minimum distortion is detected, there is a problem that the amount of calculation required is extremely large and the processing time is long.

This invention was made to solve the above-mentioned problems, and at the same time reduces the number of distortion calculations and outputs the minimum distortion and the number of the block that produced the minimum distortion, thereby reducing the amount of calculations. The object of the present invention is to obtain a digital signal processing processor that improves the efficiency of processing time.

[Means to solve the problem]

The digital signal processor according to the present invention includes a minimum distortion register that holds the minimum distortion, a minimum distortion position register that holds the number of the block where the minimum distortion has occurred, and a number of the block on which the current distortion calculation is being performed. When detecting the minimum distortion from among the blocks of M data strings (M is a positive integer), the block counter to be held and the A comparator that compares the output of the accumulator and the value of the minimum distortion register every cycle when performing distortion calculation with the block, and a comparator that compares the output of the accumulator with the value of the minimum distortion register every cycle, and performs an accumulation operation when the output of the accumulator exceeds the value of the minimum distortion register during the execution of the accumulation. is canceled and proceeds to the next instruction or the instruction at the specified address, and if the accumulation is completed normally, the value of the accumulation register is written to the value of the minimum distortion register. The apparatus is equipped with an instruction execution control section that makes it possible to maintain the minimum distortion up to the second block using a predetermined instruction word from the instruction memory.

[Operation] During accumulation, the digital signal processor of the present invention compares the accumulated data with the minimum distortion every cycle, and when the minimum distortion is exceeded, the accumulation is forcibly terminated, and the block in which the accumulation has been normally completed is By updating the minimum distortion and updating the block number, the amount of required calculations is reduced and the processing time is made more efficient.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram schematically showing a digital signal processor according to the present invention, and the same or corresponding parts as in FIG.

In Fig. 1, (10) is a minimum distortion register that holds the minimum distortion, and (11) is a minimum distortion register (11) that compares the value of the minimum distortion register (10) with the output of the accumulator (7) and sends the comparison result to the instruction execution control unit (3). (12) is a block counter that indicates the number of the block currently being accumulated;
3) is a minimum distortion position register that holds the number of the block that has the minimum distortion.

(1θ1) is the data bus (5) and block counter (1
2), the input/output path (102) is the output bus from the minimum distortion position register (13) to the data bus (5), and (103)
) is the block counter (12) from the instruction execution control unit (3).
), an output path that provides an incrementing control signal to (1
04) sends the comparison result of the comparator (11) to the instruction execution control unit (
3); (105) is an output bus that supplies the output data of the accumulator (7) to the comparator (11); (106) is the output bus that supplies the data of the minimum distortion register (10) to the comparator (11); The output bus to be supplied, (107) is the update path from the accumulation register (8) to the minimum distortion register (10), and (108) is the update path from the block counter (12) to the minimum distortion position register (13). be.

FIG. 2 is a flowchart illustrating the operation of determining the distortion and block number in a certain block and M blocks that have the minimum distortion using the digital signal processor configured as shown in FIG. 1.

Now, an instruction word is read from the instruction memory (1) according to the address output from the program counter (2) and inputted to the instruction execution control section (3) via the output path (52). The instructions decoded by the instruction execution control section (3) send control signals to each section to control operations.

If the decoded instruction is an instruction that performs minimum distortion detection that involves accumulation of absolute difference values, sum of products, etc., the data memory (4)
transfer of read data from the data bus (5) to the data bus (5), transfer of up to two output data from the data bus (5) to the arithmetic unit (6), output data of the arithmetic unit (6) by the accumulator (7), and The cumulative result is transferred with the output data of the calculation register (8) (step 5T2-1).

On the other hand, the accumulation result is supplied via the output path (105) branched from the output path (62) of the accumulator (7), and the accumulation result is supplied via the output bus (10B) from the minimum distortion register (10). The output data is compared every cycle by the comparator (11) (step 5T2-2).

The comparison result in the comparator (11) is transferred to the instruction execution control unit (3) every cycle, and if the accumulated result in the accumulator (7) is greater than the value in the minimum distortion register (10),
In other words, in the case of YES, the accumulation is stopped, the repeat counter (9) is cleared to "θ", and at the same time, the increment control signal from the instruction execution control section (3) is used to block the
The value of the counter (12) is incremented and the process proceeds to the next instruction (step 5T2-3.2-4).

Execute the accumulation the number of times set in the repeat counter (9), and if the accumulation is completed normally, the accumulation register (8)
The value of the block counter (12) is updated by writing to the minimum distortion register (10) (step 5T2-5), and the value of the block counter (12) is updated by writing to the minimum distortion position register (13) (step 5
T2-6) and the block counter (12) is controlled by the increment control signal (103) (step 572-7).

By the above processing operation, blocks A and M of a certain data string are
When detecting the block with the minimum distortion from among the search target blocks y1, if the number of times the k-th block performs accumulation is Wk (Wm is an integer of 1≦Wk≦W), then the product-sum calculation process is (ΣWh) Once, the minimum distortion and the number of the block with the minimum distortion are obtained at the same time as the accumulation. Therefore, there is no need to compare and update the minimum distortion and the number of the block with the minimum distortion, and the calculation processing time is reduced to tX(ΣW,) as shown in Figure 3.
It is shortened to only.

1.1 Note that although the above embodiment uses the sum of squared differences for distortion calculation, the absolute value of the difference or the inner product may be used.

In addition, although the judgment criterion for the comparator is ``if the accumulated output of the accumulator exceeds the value of the minimum distortion register'', it may also be ``if the accumulated output of the accumulator exceeds or becomes equal to the value of the minimum distortion register''. .

〔Effect of the invention〕

As described above, according to the present invention, when calculating distortion between blocks, the number of the block with the minimum distortion is held compared with the minimum distortion every cycle, so unnecessary calculations can be omitted. This has the effect of effectively suppressing the amount of required calculations and increasing the efficiency of processing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital signal processor according to an embodiment of the present invention, FIG. 2 is a flowchart showing the minimum distortion detection operation in the example of FIG. 1, and FIG. 3 is a distortion calculation according to the present invention. 4 is a block diagram of a conventional digital signal processing processor, FIG. 5 is a data related diagram, FIG. 6 is a flowchart showing the operation of minimum distortion detection in the example of FIG. 4, and FIG. It is a figure which shows the amount of distortion calculations in a conventional example. In the figure, (1) is an instruction memory, (3) is an instruction execution control unit, (4) is a data memory, (6) is an arithmetic unit, and (7) is a data memory.
is an accumulator, (8) is an accumulation register, (10)
is a minimum distortion register, (11) is a comparator, (12) is a block counter, and (13) is a minimum distortion position register. Agent: Patent attorney Masuo Oiwa (2 others) Flowchart diagram showing 20 Shobutsu movements Figure 2 n1 between two times Il/]l2 according to l[fε child 4 figure 3 figure 3 subordinate mo's saving zokuru fνLhikoipu0 sepn block diagram figure shiba pot f? = ('11j +, -, sorw) = ('11j +, -, sorw) = ('11j +, -, sorw) = ('11j +, -, sorw) = ('11j +, -, sorw) = ('11j +, -, sorw) 2j ~H ：J3 Distorted drawings and drawings procedure amendment (voluntary) -・15 Year 5, Heisei year 5, Column for detailed explanation of the invention of the specification to be amended.

Claims (1)

[Scope of Claims] An instruction memory in which instruction words for instructing various internal operations are stored in advance; an internal data memory for storing operation data; and an instruction word for one or more pieces of data read from the internal data memory. An arithmetic unit that performs various operations according to instruction words read from memory, an accumulator that accumulates the output of the arithmetic unit, an accumulation register that holds the output of the accumulator, and a minimum distortion that holds the minimum distortion. a register, a minimum strain position register that holds the number of the block that caused the minimum distortion, a block counter that holds the number of the block that is currently performing the distortion calculation, and a register that stores the minimum strain by M (M is positive When detecting from a block of data strings (integers), the kth block of M data strings (k is 1≦k≦M
a comparator that compares the output of the accumulator with the value of the minimum distortion register every cycle, and a comparator that compares the output of the accumulator with the value of the minimum distortion register every cycle, and the output of the accumulator exceeds the value of the minimum distortion register during the execution of the accumulation. When the accumulation is completed, the accumulation is stopped and the process proceeds to the next instruction or the instruction at the specified address. If the accumulation is completed normally, the value of the accumulation register is written to the value of the minimum distortion register. an instruction execution control section that makes it possible to maintain the minimum distortion up to the k-th block in the instruction memory using a predetermined instruction word from the instruction memory.