JPH0512009A - Digital signal processing device - Google Patents

Abstract

PURPOSE:To reduce the number of physical steps of a program eliminating a need to insert a NOP instruction after an instruction of immediate transfer to an index register with respect to improvement of the address update method of DSP having the pipeline constitution. CONSTITUTION:A private transfer instruction LXX 8 which commands only transfer of immediate data D to index registers Xo to Xn and a private bus 7 through which immediate data D is directly transferred from a first instruction register IR1 to the index register Xn are provided. Immediate data D is transferred to the index register Xn through the private bus 7 based on the transfer instruction 8 to complete data transfer in the instruction decoding cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device (hereinafter referred to as a DSP) adopting a pipeline processing system, and more particularly to a DSP having an improved index register updating method.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional DSP uses a sequence control unit 1 for sequentially reading out instructions to control each unit, a data RAM 2 for storing data, and data from a data RAM. An arithmetic processing unit 3 for performing an arithmetic operation,
It has an address calculation unit 4 for calculating addresses of a data RAM and an instruction ROM, and an internal data bus 5 for transferring data between these units.

The sequence controller 1 includes a program counter PC, an instruction ROM IROM, two-stage instruction registers IR1 and IR2,
It has a decoder DEC, and instructions are sequentially read from the instruction ROM 32 by the designation of the program counter PC, latched in the instruction register IR1 in the first stage, and transferred to the instruction register IR2 in the second stage in the next machine cycle. .. The address calculation unit 4 includes a plurality of index registers X _O , X ₁ , X ₁ .
₂ and the input selectors SELX0 to SELX2 for selecting the data to be set in the index register, and the address selector SELX for selecting the output of any one of the index registers and outputting the effective address to the data RAM.
And an update value register I to which the update value of the index register is set, and an adder ADD that adds the update value to the effective address to update the values of the index registers X _O , X ₁ and X ₂ .

Then, the index registers X _O , X
Data transfer to ₁ and X ₂ is performed by a data path via the internal data bus 5. On the other hand, the DSP data processing is performed by a two-stage pipeline, and as shown in FIG. 5, one instruction is executed through the following three cycles. The figure is a time chart showing the transition of the instruction designated by the program counter PC and the instruction held in each of the two instruction registers.

Instruction fetch cycle: An instruction is read from the instruction ROM IROM by the designation of the program counter PC and latched in the first instruction register IR1 at the end of the cycle.

Instruction decode cycle: The instruction code of the first instruction register IR1 is decoded to generate a control signal for controlling each part, and the instruction is latched in the second instruction register IR2 at the end of the cycle. The address calculation unit 4 also calculates an effective address and an address for updating the address.

Instruction execution cycle: Execution of instruction processing and data transfer according to control signals. In this cycle, the operand of the instruction held in the second instruction register IR2 is transferred to various registers via the internal data bus 5.

Here, for example, as shown in FIG. 6, a case where a data transfer instruction "LDI D, X ₀ " for transferring the immediate data D to the index register X ₀ is executed will be described. The instruction code is decoded in the instruction decode cycle of, and by this control signal, the immediate data D which is the operand of the instruction held in the instruction register IR2 in the execution cycle of is transferred to the index register X ₀ via the internal bus 5. It

However, due to the configuration of pipeline processing, in the execution cycle of, the address calculation of the next instruction is performed in the address calculation unit. In this case, the index register X _O during data transfer by the immediately preceding instruction may be used for address calculation of the next instruction. For example, the next instruction is “MOV B, (X ₀ + I)”, that is, the data of the general-purpose register B is transferred to the address of the data RAM designated by the contents held in the index register X _O , and the value of the index register X ₀ is changed. In the case of an instruction that increments and replaces only I, D is transferred to the index register X ₀ in the machine cycle, so the data of X _O is not fixed at the beginning of the cycle of Correct X ₀ + in address calculation of next instruction
I is not latched in index register X ₀ .

Therefore, in order to avoid this, after the data transfer instruction to the index register, the non-processing instruction "N
By inserting "OP", the address calculation of the next instruction is not performed in the execution cycle of.

[0011]

The above-mentioned insertion of the NOP instruction causes a problem that the number of program steps for executing the instruction increases and the processing time becomes long, and a non-processing instruction must be inserted after the specific instruction. There is a problem that programming becomes complicated because it does not happen.

The present invention has been made in view of the above problems, and an object of the present invention is to prevent a NOP instruction from being inserted after an immediate data transfer instruction to an index register in a DSP having a pipeline structure. ..

[0013]

FIG. 1 is a block diagram showing the principle of the DSP of the present invention. The above-mentioned problem is, as shown in FIG. 1, an instruction decoding process for decoding an instruction sequentially read to the first instruction register IR1 and an address calculation using the index register X, and a second instruction based on the decoding result. In a digital signal processing device having a two-stage pipeline structure in which instruction execution processing for transferring immediate data held in the register IR2 to various registers via the internal data bus 5 is performed in parallel, the immediate data D is transferred to the index register Xn. The dedicated transfer instruction 8 (for example, LXX) for instructing only the transfer to the index register Xn and the dedicated bus 7 for directly transferring the immediate data D from the first instruction register IR1 to the index register Xn are provided. Index register X based on
Transfer of the immediate data D to the dedicated bus 7
It is solved by the digital signal processing device of the present invention, which is characterized in that it is completed within the instruction decoding cycle by performing the processing via.

[0014]

When the data transfer to the index register Xn is immediate data, the first instruction register IR
Index register Xn from 1 via dedicated bus 7
Since the data transfer is directly performed to the second instruction register IR2 and the internal data bus 5, the transfer is completed within the instruction decode cycle. That is, since the instruction is executed within the instruction decode cycle, it does not affect the use of the index register when calculating the address of the next instruction. Therefore, after the immediate data number command,
There is no need to insert the P instruction, the number of steps in the program can be reduced, and programming becomes easy.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 2 is a block diagram showing a main part of the DSP of the present invention,
FIG. 3 is a time chart when the LXX instruction is executed according to the present invention. Note that the same reference numeral represents the same object throughout the drawings.

A feature of the DSP of the present invention is that a dedicated bus for transferring immediate data and a dedicated transfer instruction for instructing its processing are provided in each register of the address operation unit, and other configurations and functions are provided. 4 is the same as the conventional example described above with reference to FIG.

In FIG. 2, in addition to the conventional immediate data transfer instruction LDI to a general-purpose register, a dedicated transfer instruction 8 (for example, "LXX" for instructing immediate data transfer to an index register and an update register is provided.
D, Xn ": Immediate data D is transferred to the index register Xn). Then, the hardware provided separately from the first instruction register IR1 internal data bus 5 a dedicated bus 7 to direct only the operand of the instruction to each index register X ₀ to X ₂ and the update value register I, the The input selector SELXn provided corresponding to the register is set to three inputs and one of them is input. Further, an update value selector SELD is newly provided so that immediate data can be used separately from the data of the update value register I as the address update value input to the address adder ADD. Each input selector is LXX
Controlled by the instruction decode output signal, the data selected from the plurality of input data is latched in the index register. Note that the decoder DEC of the sequence control unit 1 normally has a flip-flop circuit for holding the decoded control signal until the instruction execution cycle. Make sure the decode output is available within the machine cycle time.

FIG. 3 is a time chart when the dedicated transfer instruction LXX is executed by the DSP having the above configuration. An instruction "LXX D, X ₀ " that transfers immediate data D to the index register X ₀ in a machine cycle
Is fetched into the first instruction register IR1 by the program counter designation. In the machine cycle, the operand D of the instruction is input through the dedicated bus 7 to the input selector SEL.
Is input to the X0, since SELX0 based on the decoding signal of the instruction code to select the input D, the index register X ₀ completes the processing by latching the end D of the machine cycle. In this cycle, the next instruction “MOV B, (X ₀ + I)” including the address calculation using the index register X ₀ is fetched, and the address calculation is performed in the cycle. At this time, the index register X ₀ contains Since the regular number D has been latched, the contents of X ₀ are correctly updated to D + I.

An update value selector SELD is newly provided,
By inputting the dedicated bus 7 from the instruction register IR1 to this update value selector and controlling it with the LXX instruction, the index register can be updated not only by the value of the update value register I but also by the immediate data D. The number of steps can be reduced.

Further, since the conventional transfer instruction for setting a numerical value in the index register is also left via the internal bus, the conventional program can be operated as in the conventional case.

As described above, according to the present invention, it is possible to reduce the number of instruction steps when updating the index register by transferring the immediate data, and it is possible to update the immediate register by accumulating the immediate data. In addition, by leaving the conventional method, LDI D,
A conventional program using a combination of an X ₀ instruction and a NOP instruction can be executed without modification, and it is possible to avoid confusion in programming.

[0022]

As described above, according to the present invention, in a DSP having a pipeline structure, after the immediate data transfer instruction to the index register, NO is output.
Since it is not necessary to insert the P instruction, there is an effect that the number of steps of the program can be reduced.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a DSP of the present invention.

FIG. 2 is a diagram showing a main part of a DSP of the present invention.

FIG. 3 is a time chart when executing an LXX instruction according to the present invention.

FIG. 4 is a diagram showing a main part of a conventional DSP.

FIG. 5 is a time chart of transition of contents of instruction register in pipeline processing method.

FIG. 6 is a time chart showing problems of the conventional technology.

[Explanation of symbols]

1-Sequence control unit, 2-Data RAM, 3-Operation processing unit, 4-Address operation unit, 5-Internal data bus, 7-
Dedicated bus, 8-dedicated transfer instruction, Xn-index register, IR1-first instruction register, IR2-second instruction register

Claims (1)

Claim: What is claimed is: 1. An instruction decoding process for decoding an instruction sequentially read to a first instruction register (IR1) and an address calculation using an index register (Xn), and based on a decoding result. In a digital signal processing device of a two-stage pipeline configuration in which the immediate data held in the second instruction register (IR2) is transferred in parallel to the instruction execution processing for transferring it to various registers via the internal data bus 5, Dedicated transfer instruction for instructing only transfer of data (D) to the index register (Xn)
(8) and a dedicated bus (7) for directly transferring the immediate data D from the first instruction register (IR1) to the index register (Xn) are provided, and the index based on the transfer instruction (8) is provided. A digital signal processing device characterized in that the transfer of the immediate data (D) to a register (Xn) is completed within an instruction decode cycle by performing the transfer via the dedicated bus (7).