JPH0616287B2 - Vector arithmetic processor with mask - Google Patents

Description

The present invention relates to an apparatus for calculating vector data at high speed.

[Prior art]

In order to achieve higher speed processing of the vector processor, it is an issue that more kinds of processing can be processed at higher speed by the vector processor. Above all, FOR
In the TRAN program, a higher-level processing device is required to process a DO loop containing an IF statement at high speed. However, the conventional DO loop processing procedure shown in FIG. This will be described with reference to FIG. 3 and FIG.

In the DO loop shown in FIG. 1, only when the value of the result of the logical operation as shown in Expression (1) is "true" and the logical operation result shown in Expression (2) is "true". , Expression corresponding to the index value: I is added and assigned between the elements having the expression (3), and the expression between the elements having the index value such that either expression (1) or expression (2) does not hold Do not add or substitute in (3). Such processing is repeated for N sets of elements.

In FIG. 2, the number of elements: N is 6, and the operand A (1
~ 6), B (1-6), C (1-6), D (1-6),
It shows a data flow when the calculation of FIG. 1 is performed by assuming appropriate numerical values for F (1-6) and G (1-6).

The value "X" in FIG. 2 is not changed by these processes,
It also indicates that it is not involved in this process.

The processing procedure is shown below.

Step 1: Comparing the corresponding element members of the operands A (1 to 6) and B (1 to 6), respectively, to create a vector mask: VM (1 to 6). In this case, when the values of both corresponding elements match and the logical operation result is “true”, the value “1” is written in VM, and when they do not match, VM
The value "0" shall be written in. Therefore, in this example, VM
The values of (1 to 6) are 0, 1, 0, 1, 1, 0, respectively.

Step 2: At the next Step 3, the vector mask: VM
In order to use the vector mask register, which stores the above, for writing again, the contents of VM (1 to 6) are saved in another register SR1. Note that this SR1 is not a register dedicated to a vector mask, and can only process all the elements of the held data collectively. Therefore, this step is performed after all steps 1 are completed.

Step 3: The operation of the equation (2) shown in FIG. 1 is performed in the same manner as the step (1), and the result is written in the VM (1-6). Also here, when the value "1" is associated with the logical operation value "true" and the value "0" is associated with the "reason", the values of the VMs (1 to 6) in this case are 0, 1, respectively. It becomes 1,1,0,1.

Step 4: In the next step 5, the logical operation between the general purpose registers is performed by using the general purpose arithmetic unit capable of performing only the batch processing for all elements. Therefore, the value of VM (1 to 6) is stored in the general purpose register SR2. evacuate. This step is also step 2
For the same reason as above, it is performed after all the steps 3 are completed.

Step 5: The logical product of each bit of SR1 and SR2 is SR
Ask for 3. This step is performed after step 4 is completed.

Step 6: The value of SR3 obtained in Step 5 is set to VM (1
To 6).

Step 7: Based on the value of VM (1 to 6) obtained in Step 6, addition and substitution shown in the equation (3) of FIG. 1 are performed.
At this time, the result of the operation is invalidated for the element whose corresponding vector mask VM (I) value is “0”. That is, the value of E (I) at that time is not changed. In this example, the operation result operates only for the second and fourth elements so as to change the value of E (I) in the main memory.

The state of the above processing is shown in the time chart of FIG.
The vertical axis of the time chart shows each step, and the horizontal axis shows time. Each number indicates the first cycle of processing of that element number, and the time shift between steps indicates the start time shift.

As described above, the processing by the vector processor of the DO loop including the complicated conditional statement according to the conventional technique has only one vector mask register. Therefore, the processing is moved to the batch processing register to perform the calculation by the batch processing. Unless the final vector mask is processed and transferred to the vector mask register again, conditional arithmetic processing cannot be performed. Therefore, as shown in FIG. 3, in the prior art, the vector processing is performed in steps 1, 3, and 7.
In addition, there is a problem that the processing time zones can be divided and processing cannot be performed in parallel or at high speed between these steps.

In general, a vector processor achieves high speed by processing the elements of different vector operations differently in parallel, but steps 2, 4, 5, 6
Since the above process is not suitable for the vector processor, it prevents the steps 1, 3 and 7 from being processed in parallel as shown in FIG.

[Object of the Invention] It is an object of the present invention to provide a vector operation processing device capable of simultaneously performing vector mask generation, vector mask operation processing, and conditional vector operation processing in parallel. .

[Outline of Invention]

Therefore, in the device according to the present invention, (1) a plurality of vector mask dedicated registers that can be simultaneously written and read.

(2) One or more vector mask dedicated arithmetic units for calculating a new vector mask value by inputting the data in the vector mask dedicated register.

(3) A means for synchronizing the writing of the vector mask and the reading to the vector mask dedicated arithmetic unit.

(4) A means for synchronizing the writing of the vector mask and the reading to the arithmetic unit for vector arithmetic processing with a mask.

By newly providing (1) and (2), vector mask generation, vector mask calculation, and conditional vector calculation processing can all be processed in parallel at the same time.

However, in this specification, the term "arithmetic processing"
Main memory refers to all operations such as main memory reference, addition / subtraction between vectors, and storage of results in main memory. In the embodiments of the present specification, masked main memory storage is taken as an example.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to examples. Fifth
The figure shows an embodiment of the invention.

The part of the apparatus not directly related to the present invention has the same structure as a normal vector processor, and the description of that part will be briefly described.

In FIG. 5, 101 is a main storage device, 102 is a main storage control device, 103 is a scalar processing device, 104 is a scalar instruction control device which is a part thereof, and 105 is a vector instruction control device.

The scalar instruction control unit 104 decodes the instructions sequentially read from the main storage unit 101 via the main storage control unit 102 and the signal line 201, and when this is a normal scalar instruction, the scalar processing unit 103 causes a normal scalar The arithmetic processing is performed, and the result is written in the main storage device 101 via the signal line 202. If the instruction decoded by the scalar instruction control device 104 is an instruction to start the vector instruction sequence, the signal line 2
The start address of the vector instruction string on the main storage device 101, the number of vector elements to be processed, and the activation signal are passed to the vector instruction control device 105 via 03. Subsequently, the vector instruction control device 105 sequentially reads the vector instruction sequence from the main storage device 101 via the signal lines 201 and 204 in accordance with the given address, decodes the vector instruction, and registers and arithmetic operations specified in the instruction. Based on the instruction that the controller, memory requester, etc. are in a usable state, the resources required for the instruction are activated via the signal lines 205, 206, and 207, respectively, and at the same time, control including the number of vector elements to be processed is performed. Transfer information. The processing for each element of the vector instruction is sent from the vector register controller 110 or the vector mask register controller 120. The process proceeds in accordance with the processing permission signal for each element. The execution of the vector instruction according to the present invention will be described below by taking the case of performing the processing of the DO loop shown in FIG. 1 as an example. In this example, buffer storage called a vector register is used, and a series of data consisting of N elements, A (1 to N) and B (1
~ N), C (1 ~ N), D (1 ~ N), E (1 ~ N),
It is necessary to store G (1 to N) in the vector registers 111 to 116 via the signal lines 211 to 216, respectively, but the processing during this period is to follow the processing by a normal vector processor.

To execute the processing of FIG. 1, in addition to the six instructions that perform the above processing, A (I) and B (I) are compared element by element,
Seventh instruction to write the comparison result to the vector mask register. Similarly, an eighth instruction to write the comparison result of each element of the values of C (I) and D (I) to a mask register different from that written by the seventh instruction. A ninth instruction that performs a logical operation between two vector masks obtained by the seventh instruction and the eighth instruction and writes the result to the third vector mask register.
The tenth instruction for adding F (I) and G (I) element by element and storing the result in the vector register, and the addition result obtained by the tenth instruction are given by the ninth instruction. Only when the obtained vector mask takes "1" (or
The eleventh instruction for writing to the memory address corresponding to E (I) is used only when “0” is taken).

The process of FIG. 1 will be described below with reference to FIG. In response to the seventh command, the vector command control device is
The value in the vector register 111, 112 is sent to
Compare (1). In this case, the value “1” is written to the vector mask register 122 via the signal line 231 when the relation of equality is established, and the value “0” is written to the other case. This comparison operation is 131
1 in 1 cycle by using pipeline arithmetic unit
You can proceed with the pitch of the element. Similarly, the eighth instruction compares equation (2), and if it is satisfied, “1”
If not satisfied, “0” is set, and the pipeline arithmetic unit 132
From the vector mask register 1 via the signal line 232.
Write in 23.

An operation is performed between the values written in 122 and 123, this time by the ninth instruction. This is not a register and an arithmetic unit capable of only batch processing as described in the prior art, but a dedicated register 12 for vector mask.
1 to 123 and the dedicated pipeline arithmetic unit 141 are used, the elements for which necessary data are gathered are synchronized so as to immediately shift to the process of taking the logical product.

In addition, the value of the vector mask created by the ninth instruction is
Also when referred to by the eleventh instruction, the data to be stored in the memory and the elements having the same vector mask are synchronized so that the processing is immediately performed.

The former synchronization mechanism between the vector mask registers will be described with reference to FIG. 6, and the latter synchronization mechanism between the vector mask registers and the vector registers will be described with reference to FIG. 7 by taking conditional vector operation as an example.

The value of the vector mask register written by the 7th and 8th instructions can be read from anywhere as long as the writing is completed over all the elements, but it can be written if the elements in the middle are being written. If the previous value is read, the process of FIG. 1 will not be executed correctly. For the purpose of knowing the written range, for example, the vector mask register 122 that is read out to obtain the logical product after writing the comparison operation result
Corresponding to (hereinafter, referred to as VMR2), an up-down counter 322 for storing how much the number of written elements exceeds the number of read elements, and a register for storing a state of being written or being read 321 is prepared. The permission signal 404 for reading one element from the VMR2 is issued when the VMR2 is not writing or when writing is being performed but the element to be read from now is already written. Counter 32
Since 2 holds the difference obtained by subtracting the number of read elements (or the number of read scheduled elements) from the number of write elements, a signal 4 indicating that the value of this counter is positive
01, a signal 402 indicating that VMR2 is writing and reading, and a signal 403 indicating that VMR2 is not writing and that is in a simple read state, the logics of the AND circuit 323 and the OR circuit 324 are taken. And then signal 4
04 can be obtained.

Further, the VM may be operated between the VMR2 and the vector mask register 123 (hereinafter referred to as VMR3).
Both R2 and VMR3 are limited to the case where permission signals for reading one element are available. The 1-element operation permission signal 406 includes a VMR 2 1-element read permission signal 404 and a VMR 3 1-element read permission signal 4.
It is obtained by ANDing 05 using the AND circuit 301. When the value of the read address 302 of VMR2 and 3 is added by the operation permission signal 406 of this one element and the value of the counter 303 which stores the number of unprocessed elements is not 1, it is decremented by 1 and the next element is processed. And proceed. This logical product operation is written in the vector mask register 121 (hereinafter referred to as VMR1) via the stages 1411 to 1413 of the pipeline arithmetic unit 141. At this time, the addition to the write-side address 304 and the up-down counter 312 is performed by synchronizing the data processing by appropriately adding the synchronization flip-flops 306 to 307. In order to read the element data written in VMR1 at the same time as writing, if necessary, after the +1 operation to the up-down counter 312 is performed,
The time difference until the data is actually written in 122 is calculated after the -1 operation of the up-down counter 312 is performed.
It is necessary to design equal to the time difference between reading. In this example, therefore, the signal 407 is 307
Of the flip-flops are sent to the up-down counter 312. The transmission time of the signal from the first one 3071 of the flip-flops 307 to VMR1 and the transmission time from 312 to the read address of VR1 (503 in FIG. 7) omitted in FIG. 6 are made equal. Thus, the data written in VMR1 can be immediately read out.

In FIG. 6, WT is a signal issued by a write command to each vector mask register. In this example, with the start of the processing of the equation (1) in FIG. 1, the state 321 of the VMR2 is set to the write state and the up-down counter 322 is reset to 0 by the signal 421. And the write signal 4 for each element
The number of writes is counted up by 22 and the result is written in VMR1 by a signal 423. And
The value of the counter 303 is 1 when the processing for all elements is completed.
The signal 424 indicating that the write status is detected and the record indicating that the write status is set from 311 and the record indicating that the read status is set from 321 to 331 are released.

The above operation is the same as the write control method of VMR1 by the vector mask register calculation explained in FIG. 6, and therefore the write side control circuits of VMR2 and VMR3 are omitted in FIG.

INiT is written when the vector-mask operation instructions of equations (1) and (2) are started without waiting for all elements of equations (1) and (2) in FIG. 1 to be processed. The signal 207 first sets the state 311 of VMR1 to the write state and resets the up-down counter 312 to 0, as in the case of the above-described equation (1).
Further, the state of VMR2 and VMR3 or the read state is set. Therefore, when the processing of the program shown in FIG. 1 is performed in this example, the VMR2 is in a state of reading and writing, and since the signal 401 is on and the signal 403 is off,
Control is performed to give read permission only to the elements that have been written.

The counter 322 is incremented by 1 every time one element is written by the instruction of the above formula (1). Therefore, in the vector-mask operation using the result, as long as the value of the counter 322 is positive, the read permission signal 404 Is issued and the counter 322 is decremented by -1. In the example, -1 is given by 408 for the sake of simplicity, but -1 may be given by 406.

In the case of -1 by 408, the performance may deteriorate as compared with the case of -1 by 406, but this deterioration is 3
This can be avoided by the circuits in 91-394. Signal 406
Therefore, when -1 is applied, the circuits 391 to 394 are unnecessary. In the following, for simplification, the circuits corresponding to 391 to 394 at the time of creating the read enable signal of the vector register and the vector mask register and the operation enable signal are omitted in the drawing.

Like the VMR2, the VMR3 also creates a read enable signal, and the AND condition 406 of both is used as the final operation enable signal to advance the value of the read address 302, and through the read selectors 326 and 336, The data is sent to the vector mask dedicated arithmetic unit 305, the value of the counter 312 is incremented by 1 as a write enable signal, and the value of the write address 304 is advanced. Here, by dedicating the computing unit 141 to the computation between the vector mask registers, it is possible to speed up the processing by adding a little cost. In FIG. 5, three vector register arithmetic units and one vector mask dedicated arithmetic unit are provided, but the vector mask dedicated arithmetic unit has an input data width of 32 to 32.
The latter is 1 bit / element with respect to 64 bits / element, and the cost can be reduced accordingly.

By the control of FIG. 6, it can be seen that the 7th to 8th instructions and the 9th instruction are synchronized, but FIG. 7 shows the 11th instruction and the 1st instruction.
2 shows a method of synchronizing the two instructions. VR2 and VR
Since the read control circuit of No. 3 adopts the same one as that of VMR2 and VMR3 of the vector mask register of FIG. 6, its explanation is omitted here. The difference between the read control circuit of VMR1 and the read control circuit of FIG. 6 is that a flip-flop 502 is newly provided so as to record that it is not a conditional instruction, and in that case, a vector mask value 603 to be sent to an arithmetic unit or the like is added. That is, it is always set to “1” via the signal 602. By this flip-flop, the same arithmetic unit 505 can be used in addition to the conditional vector arithmetic instruction.

In addition, in FIG. 6, corresponding to the signal 406 obtained by ANDing the read permission signals of VMR2 and VMR3, the arithmetic processing permission in FIG. 7 (in this example, the main memory storage permission of one element) is permitted.
The signal 606 is an AND of the read permission signal 644 of the vector mask register VMR1, the read permission signal 634 of the vector register VR1, and the acceptance permission signal 601 from the main memory write control circuit 1021. When processing a main memory write instruction other than a conditional instruction, 1 is stored in the register 502 by the signal 207, and the signal 644 is always set to 1 by the signal 602 and the OR circuit 543.

〔The invention's effect〕

As described above, as shown in the time chart of FIG. 4, it is possible to process the conventional 3N + 3 cycles by N + 3 cycles according to this patent. This shortened 2N
The breakdown of the cycles is that the loss in the conventional method due to the non-parallelization of the processing between the vector mask generation comparison operation instruction and the logical product operation instruction between the vector masks is N cycles, the logical product operation instruction, and the conditional operation The loss in the conventional method due to the non-parallelization of the processing with the vector operation processing (conditional main memory storage in this example) instruction is N cycles, and both losses can be improved by referring to FIGS. 6 and 7. The two types of synchronization mechanisms shown in (1) contribute to each. Both improvements can be achieved by expanding and using a normal vector register without using a dedicated vector mask register and arithmetic unit. It is clear that there is an advantage of 32 to 64 times.

[Brief description of drawings]

FIG. 1 shows FORTRAN including vector processing with mask.
Program example. FIG. 2 is a processing procedure of the FIG. 1 program according to the prior art. FIG. 3 is a time chart of the processing of FIG. 1 according to the prior art. FIG. 4 is a time chart of the process of FIG. 1 according to the present invention. FIG. 5 shows a structural example of the processing apparatus according to the present invention. FIG. 6 shows an embodiment of arithmetic execution control between vector mask registers, and FIG. 7 shows an embodiment of conditional vector main memory storage processing execution control. 121-123
Is a vector mask dedicated register. 141 is a vector mask dedicated arithmetic unit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Abe 1 Horiyamashita, Hadano City, Kanagawa Pref., Kanagawa Factory, Hiritsu Seisakusho Co., Ltd. (56) Reference JP-A-57-23174 (JP, A) JP-A-56 -22168 (JP, A) JP-A-56-88562 (JP, A)

Claims (2)

[Claims] 1. A plurality of vector registers, a plurality of arithmetic processing means for performing arithmetic processing on vector data held therein, and a plurality of vector masks used by any one of the plurality of arithmetic processing means. Of the mask registers and the vector masks held in those mask registers, and a mask calculator for supplying the result to any one of the mask registers, and the first and second mask registers held in the first and second mask registers. When the second vector mask is read out, supplied to the mask arithmetic unit, and the resulting third vector mask is being written in the third mask register, in parallel with the writing, one of the vector registers In order to perform a masked operation on any one of the vector data held by the third vector matrix, Masked vector operation processing apparatus having a synchronization means for sequentially reading corresponding pairs of elements in the written element and the vector data of click. 2. A plurality of vector registers and a plurality of arithmetic processing means for performing arithmetic processing on vector data held therein, which are first and second for creating a vector mask.
Including first and second arithmetic processing means capable of executing the arithmetic operation, a plurality of mask registers respectively holding vector masks used by any of the plurality of arithmetic processing means, and the mask registers The first and second arithmetic operations are performed in parallel by a mask arithmetic unit that performs an arithmetic operation on the held vector mask and supplies the result to one of the mask registers, and the first and second arithmetic processing means. When the resulting first and second vector masks are written into the first and second mask registers, respectively, the third
For the generation of the vector mask, the first synchronization is performed in parallel with the writing, and the pair of written elements corresponding to each other of the first and second vector masks are sequentially read and supplied to the mask calculator. And writing the third vector mask to the third mask register in order to perform a masked operation on the vector data held in any of the vector registers by any one of the arithmetic processing means. , A second vector synchronization processing device for sequentially reading a pair of a written element of the third vector mask and a corresponding element of vector data to be subjected to the masked operation.