JP2518293B2 - Data Flow Processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of use) The present invention relates to a data flow processor characterized in that a memory unit and an arithmetic unit are connected by a pipeline bus and the arithmetic order is controlled by a data flow method. It is about.

(Prior Art) Japanese Laid-Open Patent Publication No. 56-16
There is a technology described in Japanese Patent No. 9152, and a product of the technology is μPD7281 manufactured by NEC Corporation.
The μPD7281 has the structure shown in FIG. The token, which is the unit of data input to the device from the external bus, has a data value, a link table address for referring to the link table 92 after input, and a module number indicating the device on which the token is to be processed.
91 inputs the token internally when the module number of the token passing through the external bus matches the number of the device, and otherwise outputs the token through the token output unit 97 from the external bus. The input token refers to the link table 92 by its own link table address, and after obtaining the function table address for referencing the function table 93 and the link table address for referencing the link table 92 next time, the function is executed. Sent to table 93.

The token refers to the function table address in the function table 93, and then refers to and updates the management information of the data memory 94, and at the same time obtains a processing code indicating the processing content in the processing unit 96 and an access address of the data memory 94. , To the data memory 94, and waits for the operand of the other party of the binary operation or reads the constant for constant operation, if necessary. The queue memory 95 is a memory for temporarily holding the token when the processing unit 96 is processing the previous token and cannot input the next token, and when the processing unit 96 is not busy, the token is processed from the queue memory 95. It is sent to the unit 96, and depending on the processing code, one of the addition / subtraction multiplication of integer data, logical operation, shift, comparison, bit inversion, priority encoding, shunting, number generation, copy, operation using internal register, etc. Receive one treatment. If the processing coat of the token indicates output, the token is sent from the cue memotor 95 to the token output unit 97, transformed into the form of the input token, and then output to the external bus. The token processed by the processing unit 96 is sent to the link table 92, and again referred to by the link table address. In the same manner, the data is passed through the internal link bus until the output instruction is executed, and the necessary processing is performed on the data value.

(Problems to be Solved by the Invention) In the above-mentioned data flow processor, since the arithmetic operation processing supported is limited to addition / subtraction multiplication for integer data, it is necessary to arithmetically operate the data of the floating point representation other than these. Processing, and processing including division, calculation of elementary transcendental functions such as square roots and triangular relations could not be performed.

For example, when computer graphics processing by the Z-buffer method is performed, floating-point arithmetic is required to accurately process data having a relatively wide dynamic range, and division is performed for perspective projection conversion, intersection calculation, luminance calculation, and the like. , It is essential to calculate elementary transcendental functions such as Kaihei and triangular relations.

However, the following problems occur when the processing unit of the conventional apparatus is equipped with these numerical operation processing hardware as they are.

Conventional integer arithmetic processing can be performed in a short time with simple hardware, whereas floating-point arithmetic processing requires complicated hardware and a long processing time. Therefore, if it is attempted to finish the processing of the processing unit with the same number of steps for all instructions as in the conventional art, the operation pipeline cycle must be lengthened, and the processing speed of the entire data flow processor becomes slow.

The iterative method based on the convergence calculation is usually used for the elementary transcendental function operation, but the number of steps to the end is variable depending on the type of data and function, and the processing unit is occupied during that time, so the overall pipeline performance is improved. It deteriorates, and processing performance falls by this.

The present invention solves the problems described above, and reduces the pipeline performance as much as possible to the processing that requires the operation of the data of the floating point representation and the processing including the calculation of the elementary transcendental functions such as division, square root and triangular relation. The purpose of the present invention is to provide a data flow processor that can be executed without executing it, and to realize high-speed processing with computer graphics.

(Means for Solving Problems) A data flow processor of the present invention is a link table for storing destination addresses of tokens and a function table for storing instruction codes, which are connected in sequence so as to form a ring bus. , A data memory for temporarily storing operand data used for operations, a buffer queue for temporarily holding tokens, a processing unit for performing data processing on tokens, and an operation output selection circuit for controlling result output from the processing unit,
Furthermore, the processing unit is configured by having a token output unit for sending a token to an external bus and a token input unit for inputting a token from an external bus and sending it to the link table or the token output unit, and in particular, the processing unit is An integer arithmetic processor, which is arranged in parallel and mainly performs arithmetic on integer data,
It is composed of a floating point arithmetic processor for arithmetical operation of floating point data and a numerical function arithmetical processor for arithmetic of transcendental functions, and the buffer queues are arranged in parallel to hold tokens to be inputted to each processor of the processing unit. An integer arithmetic processor queue,
It is characterized by a numerical function arithmetic processor queue.

(Operation) In the data flow processor of the present invention, the token having the data to be processed obtains the necessary processing code, parameter, and binary data of the binary operation through the link table, function table, data memory and buffer queue. . Each token leaving the data memory is input to one of the integer arithmetic processor queue, the floating point arithmetic processor queue, and the numerical function arithmetic processor queue of the buffer queue according to the processing code, and the subsequent integer arithmetic processor and floating point arithmetic Processor,
When the numerical function arithmetic processor is not busy, it is input to it, processed there, and the token having the result data is sent to the arithmetic output selection circuit.

The integer arithmetic processor mainly performs operations such as arithmetic operations on integer data, and can further perform combined processing of a plurality of functions in a pipeline manner. Floating point processors perform floating point data calculations that require long steps. In addition, the numerical function arithmetic processor calculates the elementary transcendental function by iterative calculation, and the numerical function arithmetic processor performs such variable time iterative processing.
While one piece of data occupies the hardware, other integer arithmetic processors and floating point arithmetic processors can be supplied with input tokens from their corresponding buffer queues and operate in parallel.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is an internal block diagram showing a configuration of a data flow processor according to an embodiment of the present invention. 11 is a token input unit, 12 is a link table, 13 is a function table, 14 is a data memory, 15 is a buffer queue, 16 is a processing unit, 23 is a calculation output selection circuit, 17 is a token output section, and a link table 12, a function table 13, a data memory 14, a buffer queue 15,
As shown in the figure, the processing unit 16 and the operation output selection circuit 23 are connected in a ring shape by a pipeline type bus in this order, and tokens are transferred on this internal ring bus. The buffer queue 15 is an integer arithmetic processor queue 24, a floating point arithmetic processor queue 25, and a numerical function arithmetic processor queue 26 are processing units.
16 is an integer processor 20 and a floating point processor
21 and a numerical function processor 22 are arranged in parallel. The token leaving the data memory 14 is sent to one of the queues forming the buffer queue 15, and is then sent to one of the integer arithmetic processor 20, the floating point arithmetic processor 21 and the numerical function arithmetic processor 22 connected to the queue, and there. The token obtained as a result of the processing in (1) is sent to the operation output selection circuit 23.

FIG. 2 is an overall configuration diagram of an example of a data processing device using an embodiment of the present invention. In this device, a plurality of data flow processors 1 and 2 and one memory interface circuit 3 are connected by an external bus 5, and the external bus is connected to the memory 4 via the memory interface circuit 3. The token is transferred asynchronously on the external bus 5 by the handshake method.

FIG. 3 shows the format of a token which is a unit of data.
On the external bus 5, the token 60 comprises a module number 61, an organization identifier 62, a link table address 63 and a data section 64.

The tokens used in this embodiment can be processed as a group of one token or a plurality of tokens. The group token always flows continuously in the processing device, and has the same module number 61 and the same link table address 63. The organization identifier 62 is used to identify the token in the set token, and distinguishes "0" when the token constitutes a set token by itself, and distinguishes each other in a set token composed of multiple tokens. They can have different values if needed. However, the last token in the group token has "0" as an organization identifier.

The token input unit 11 takes in only the tokens whose module number 61 is equal to the number given to the device among the tokens input from the preceding data flow processor or memory interface circuit, and link table
It is sent to 12 in synchronism with the pipeline cycle, and other tokens are used as transit tokens as they are in the token output section 17
Send to. However, when the link table 12 or the token output unit 17 is in the busy state during the processing of the group token as described below, the token is not transmitted, and the input to the preceding data flow processor or memory interface circuit is stopped. .

The link table 12 inputs a token from the operation output selection circuit 23 or the token input unit 11, but when both are input at the same time, the input from the token input unit 11 is usually prioritized. However, if the organization identifier of the input token is not "0" regardless of which one, the token is a token other than the last token in the group consisting of multiple tokens, and the tokens are grouped consecutively. Since it can be seen that the rest of the tokens will be input, by notifying the non-source of those tokens that they are busy and stopping the input, priority will be given to the entire set of tokens in succession. input. This guarantees the continuity of the group token.

The token 60 of FIG. 3 input from the operation output selection circuit 23 or the token input unit 11 to the link table 12 refers to its internal memory using the link table address 63, and the function table address and the next link obtained there. It is sent to the function table 13 with the link table address for referring to the table 12.

In the function table 13, the internal table is accessed by the function table address of the input token, and the management information in the data memory 14 is referred to.
Simultaneously with the update, the processing code indicating the processing content in the processing unit 16 and the access address of the data memory 14 are added to the token. The processing code of the processing unit 16 is processed by the processing unit 16 and a processor selection code indicating whether the token should be processed by the integer arithmetic processor 20, the floating point arithmetic processor 21, or the numerical function arithmetic processor 22. Result token after calculation is the operation output selection circuit
Is sent from 23 to link table 12 or token output unit 17
And an output direction selection code indicating whether or not to be sent to.

The data memory 14 is accessed by the above access address, and as a queue for waiting for the token having the address and the token having the data for the binary operation data or the write token output to the memory interface circuit, if necessary. Or used as a memory for storing constants for constant operations,
When the token arrives, the data is read / written.

The buffer queue 15 is a FI for temporarily holding the token before inputting the token to the processing unit 16.
The FO memory is composed of an integer arithmetic processor queue 24, a floating point arithmetic processor queue 25, and a numerical function arithmetic processor queue 26. The token leaving the data memory 14 should be processed by the floating-point arithmetic processor 21 according to the processor selection code of the floating-point arithmetic processor 21 if the token is a token to be processed by the integer arithmetic processor 20. If it is a token, it is input to the floating point arithmetic processor queue 25, and if it is a token to be processed by the numerical function arithmetic processor 22, it is input to the numerical function arithmetic processor queue 26. Whether each processor is busy with the next token from the succeeding processor and the next token cannot be entered in each queue, or whether the token from the buffer queue 15 can be accepted at that clock without being busy The indicated signal is being sent. If the subsequent processor in each queue is not busy, the token is sent from the immediate queue to that processor, otherwise each queue stops outputting until it is no longer busy.

The arithmetic output selection circuit 23 receives a token from the integer arithmetic processor 20, the floating point arithmetic processor 21, and the numerical function arithmetic processor 22 that has issued a result output request, and returns an acknowledge signal to it. When requests are made simultaneously from multiple processors out of the three, numerical function arithmetic processor> floating point arithmetic processor>
The order of acceptance is determined by the priority of the integer arithmetic processor. When the token is received, the token is sent to either the link table 12 or the token output 17 according to the output direction selection code of the token. However, the token output unit 17 or the link table 12 is the token input unit 11
If it is in the busy state while accepting the token transfer from, the output is stopped, and the integer arithmetic processor 20,
Floating-point arithmetic processor 21, numerical function arithmetic processor
Do not return acknowledge signal to 22.

The token output unit 17 inputs a token from the operation output selection circuit 23 and the token nesting unit 11, and in the case of an input from the operation output selection circuit 23, the token is input to the external bus 5 in FIG. It is transformed into the token format 60 and output to the data flow processor or memory interface circuit in the subsequent stage via the external bus 5. However, when there is a request from both the operation output selection circuit 23 and the token input section 11 at the same time, the input from the token input section 11 is usually given priority. However, if the organization identifier of the input token is not "0" regardless of which one, the token is a token other than the last token in the group consisting of multiple tokens, and the tokens are grouped consecutively. Since it can be seen that the rest of the tokens will be input, by notifying the non-source of those tokens that they are busy and stopping the input, priority will be given to the entire set of tokens in succession. input. This guarantees the continuity of the group token.

When the memory interface circuit 3 in FIG. 2 receives a token 60 having a module number 61 destined for it from the data flow processors 1 and 2, the operation specified by the link table address 63 and the data section 64 therein is performed. To do. For example, when a read request token is given, a read operation is performed from the memory 4 using the value included in the data section 64 as an address, and the token having the read value is sent to the data flow processor designated by the link table address 63. Alternatively, when a token having write data and a token having a write address are given as a set token, they are used to perform a write operation to the memory 4.

Hereinafter, the integer arithmetic processor 20, the floating point arithmetic processor 21, and the numerical function arithmetic processor 22 which constitute the processing unit 16 will be described. These input tokens from the integer arithmetic processor queue 24, the floating point arithmetic processor queue 25, and the numerical function arithmetic processor queue 26, respectively, and execute arithmetic according to the processing code,
The token having the result data is sent to the operation output selection circuit 23.

The integer arithmetic processor 20 mainly inputs a token having integer data from the integer arithmetic processor queue 24, to which addition / subtraction, multiplication, logical operation, shift, comparison, bit inversion, priority encoding, sequence generation,
It operates internal registers and processes such as operations, and generally performs operations such as shunting, copying, and group token generation based on input tokens. More specifically, in this embodiment, the integer arithmetic processor 20 is composed of the following four parts.

a) Copying the input tokens, generating a plurality of token sequences from one token, generating a set token, or generating a sequence of numbers based on integer data.

b) Mainly binary or unary arithmetic operations, logical operations,
Arithmetic processing such as shift and comparison is executed without having an internal state.

c) Using a register, a process having an internal state is performed so as to take the sum of the data of token streams that flow in continuously.

d) A branch is realized by performing a positive / negative comparison judgment based on the operation result of the above part and changing the link table address of the token accordingly, or an operation of erasing unnecessary tokens is performed.

These parts operate serially in a pipeline manner on the token input from the integer arithmetic processor queue 24 according to the processing code that they have, and generate a token having result data. The integer arithmetic processor 16 is an arithmetic output selection circuit when a token having result data is output.
23 output request, and the output is calculated output selection circuit
When 23 is accepted, the next output operation starts.

The floating-point processor 21 has dedicated hardware for handling tokens that have floating-point format data, and the token data given from the floating-point processor queue 25 adds, multiplies, or floats floating-point data. Performs data type conversion from to integer data and vice versa. The floating-point arithmetic processor 21 issues an output request to the arithmetic output selection circuit 23 when there is an output of the token having the result data, and when the arithmetic output selection circuit 23 responds with an acknowledge, the next output operation is performed. Move.

For example, in order to add two floating-point data in the floating-point arithmetic processor 21, the exponent part data constituting them are compared and subtracted, and the mantissa part data corresponding to the smaller one is shifted by the difference. , The mantissa data after the shift are added together, the mantissa sum is shifted so that the obtained sum is normalized, and the shift number is subtracted from the exponent part, thereby performing a complicated and step-intensive process. There is a need. The floating-point arithmetic processor 22 divides the hardware necessary for such complicated processing in time order,
Each of them is designed to be able to operate in a pipeline manner with respect to continuously input data, which allows the floating-point arithmetic processor 22 to increase throughput even when performing complicated processing that requires a long number of steps. It is possible to maintain high processing performance.

When the numerical function arithmetic processor 22 receives a token having a data value and a processing code corresponding to the data value from the numerical function arithmetic processor queue 26, the numerical function arithmetic processor 22 performs a functional operation according to the code and outputs a token having result data to an arithmetic output selection circuit.
Output to 23. The operations to be performed include operations of elementary transcendental functions such as division, square root calculation, exponential / logarithmic function, trigonometric / hyperbolic function or the inverse function thereof. Is performed by the Newton-Raphson method which is obtained by iterative convergence calculation. The numerical function arithmetic processor 22 has arithmetic hardware for performing one iterative unit calculation of this method and hardware for judging the iteration end condition, and when an input token is given from the numerical function arithmetic processor queue 26, an appropriate initial value is given. Set the value to a register in the arithmetic hardware,
The unit processing is repeatedly performed until the iterative termination condition is satisfied by convergence. Until this end, the numerical function arithmetic processor 22 is in a busy state, and by issuing a busy signal to the numerical function arithmetic processor queue 26, the input of the next token is stopped. When the repetition end condition is satisfied, the result data is used to generate a token, an output request is issued to the operation output selection circuit 23, and the result token is transmitted. On the other hand, the calculation output selection circuit 23
When the acknowledge is returned from, the numerical function processor 22 completes the processing for one data, cancels the busy signal to the numerical function processor queue 26, and accepts its head token to start a new iterative processing operation. Start.

In this embodiment, Newton =
Although the Rafson method is used, this can be another method as long as the necessary calculation of the elementary transcendental function can be completed, for example, the Taylor expansion method.

In the present invention, as described above, the numerical function arithmetic processor which is a hardware resource for the function arithmetic occupied by the iterative calculation is arranged in parallel with another integer arithmetic processor and a floating point arithmetic processor, It is possible to operate independently, and the tokens to be input to each are held in different buffer queues. This makes it possible for the iterative computation to occupy a numeric function processor,
Other integer arithmetic processors and floating point arithmetic processors can input tokens from corresponding buffer queues and continue processing in parallel.

(Effects of the Invention) As described above, according to the present invention, it takes a variable time by arranging a numerical function arithmetic processor in parallel with an integer arithmetic processor and a floating point arithmetic processor and operating them independently and in parallel. Even if the numerical function arithmetic processor is occupied by the processing of the token during the repetitive arithmetic processing, the other integer arithmetic processors and floating point arithmetic processors can operate during that time.
Processing performance can be improved by parallel processing.

・ Because the buffer queue that is temporarily held before the token is input to the processing unit is also prepared separately for the integer arithmetic processor, floating point arithmetic processor, and numerical function arithmetic processor that make up the processing unit, and is retained separately. , Even if one processor is busy and the output of the buffer queue that supplies tokens to it is stopped, tokens to be processed are supplied to other processors one after another, and arithmetic operations are performed without interruption. It can be continued and efficient processing is possible.

-Floating-point addition / subtraction multiplication, which requires a large amount of hardware and would otherwise take a long time, is provided with dedicated hardware and is configured by dividing it into multiple steps that operate in a pipeline. As a result, the throughput of floating-point calculation can be improved, that is, the effective calculation time can be shortened, and further, the processing pipeline unit and the operation pipeline cycle of the entire data flow processor can be shortened. Processing performance is improved.

This has the effect of increasing the processing speed.

Especially for the first two points, it takes time to execute a certain part in the program as realized in the present invention, and even if the process proceeds only slowly, there are other unrelated items. The data processing method realized in the present invention in which the processing of the parts can proceed in parallel makes use of the characteristic of the data flow processor, which is determined at the time of execution by the data driven method in which the execution order of the operations is caused by the data dependency. This is a major reason why the present invention can achieve high processing performance. In addition, parallel operation of processors having different processing times such as those in the present invention or processors having variable processing times is relatively easy because the present device is based on the operation model of the data flow method. It is possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data flow processor of the present invention, FIG. 2 is an overall configuration diagram showing an example of a processing device using the data flow processor, and FIG. 3 is a diagram showing a format of a token used for explaining the present invention. , FIG. 4 is a diagram showing a configuration of a conventional data flow processor. In the figure, 11 …… Token input section, 12 …… Link table, 13 ……
Function table, 14 …… Data memory, 17 ……
Token output part, 24,25,26 …… Queue memory, 20,21,22
...... Processor, 23 …… Calculation output selection circuit.

Claims (1)

(57) [Claims] 1. A data flow processor for performing processing by flowing a token, which is a unit of data, to an internal ring-shaped bus, and destinations of the tokens connected in sequence so as to form the ring-shaped bus. A link table for storing addresses, a function table for storing instruction codes, a data memory for temporarily storing operand data used for operations, a buffer queue for temporarily holding tokens, a processing unit for processing data on tokens, and a processing unit from the processing unit. It has a calculation output selection circuit for controlling the result output, and further has a token output section for sending a token from the processing unit to the external bus and a token input section for inputting the token from the external bus and sending it to the link table or the token output section. Have In particular, the processing unit is arranged in parallel, and an integer arithmetic processor that mainly performs integer data arithmetic, a floating point arithmetic processor that performs floating point data arithmetic, and a numerical function arithmetic processor that performs transcendental function arithmetic. And the buffer queue comprises an integer arithmetic processor queue, an integer arithmetic processor queue, and a numerical function arithmetic processor queue arranged in parallel to hold a token to be input to each processor of the processing unit. Data Flow Processor to do.