JPH05225362A - Data flow type information processor - Google Patents

Abstract

PURPOSE:To provide a data flow type information processor capable of shortening an arithmetic operation time by applying a data packet only to a necessary operation part and eliminating processing for allowing the data packet to simply pass an unnecessary operation part. CONSTITUTION:The data flow type information processor includes a program storing part 1, a pair data detecting part 2 and an arithmetic processing part 3. The storing part 1 accesses a data program and outputs a data packet including a processing part identification(ID) number and an individual instruction code. The detecting part 2 queues two data packets including the same destination information out of plural data packets outputted from the storing part 1. The processing part 3 includes an input part 16, plural operation parts constituted in parallel and plural processing parts and the input part 16 decides the operation part for processing operand data included in a data packet based upon the processing part ID number and outputs the data packet to the decided operation part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dataflow type information processing device, and more particularly to a dataflow type information processing device in which a plurality of instructions are simultaneously driven by data.

[0002]

2. Description of the Related Art In a conventional Neumann computer, various instructions are stored in a program memory in advance as a program, and the addresses of the program memory are sequentially designated by a program counter so that the instructions are sequentially read and executed. It

On the other hand, the data flow type information processing apparatus is a kind of non-Neumann type computer which does not have the concept of sequential and instruction execution by a program counter. Such a data flow type information processing apparatus employs an architecture based on parallel processing of instructions. In the data-flow type information processing device, instructions can be executed as soon as the data to be operated are prepared, and a plurality of instructions are driven simultaneously by the data, so the programs can be executed in parallel according to the natural flow of data. To be done. As a result, it is considered that the time required for calculation is significantly shortened.

FIG. 5 is a block diagram showing an example of the configuration of a conventional data flow type information processing apparatus. FIG. 6 is a diagram showing an example of a packet field structure of data processed by the information processing apparatus. The data packet shown in FIG. 6 includes a destination field, a command field, a data 1 field and a data 2 field. Destination information is stored in the destination field, instruction information is stored in the instruction field, and operand data is stored in the data 1 field or the data 2 field.

The information processing apparatus shown in FIG. 5 includes a program storage unit 1, a pair data detection unit 2, and an arithmetic processing unit 3. The data flow program 10 shown in FIG. 7 is stored in the program storage unit 1. Each line of the data flow program 10 has destination information 11 and instruction information 1
2, copy presence / absence information 13 and constant presence / absence information 14. When the presence / absence of constant information indicates “present”, constant data 15 is stored in the next line. As shown in FIG. 7, the program storage unit 1 performs address designation based on the destination information of the input data packet, as shown in FIG. 7, the destination information 11, the instruction information 12, the copy presence / absence 13 and the constant presence / absence of the data flow program 10. No information 14
Is read, the destination information 11 and the instruction information 12 are stored in the destination field and the instruction field of the data packet, respectively, and the data packet is output.

The paired data detection unit 2 includes a program storage unit 1.
Waits for the data packet output from. That is, when the command information indicates a two-input command, two different data packets having the same destination information are detected, and the operand data (data 1 field in FIG. 6) of one of the data packets is detected. Content) is stored in the data 2 field of the other data packet, and the other data packet is output.
When the command information indicates a one-input command, the input data packet is output as it is.

The arithmetic processing unit 3 performs arithmetic processing on the data packet output from the paired data detection unit 2 based on the command information, stores the result in the data 1 field of the data packet, and programs the data packet. Output to the storage unit 1.

The program storage unit 1 and the paired data detection unit 2 are connected by two data transmission lines 4a and 4b. The data packet output from the program storage unit 1 is selectively transmitted through one of the data transmission paths 4a and 4b in accordance with whether the operand data is right operand data or left operand data in the arithmetic processing. .. Further, the paired data detection unit 2 and the arithmetic processing unit 3
Are connected by a data transmission line 5, and the arithmetic processing unit 3 and the program storage unit 1 are connected by a data transmission line 6.

The data packet is stored in the program storage unit 1,
By continuously rotating the paired data detection unit 2, the arithmetic processing unit 3, and the program storage unit 1 in order, the program storage unit 1
The arithmetic processing based on the data flow program 10 stored in the.

FIG. 8 is a diagram showing an example of the data flow graph. In FIG. 8, the node N1 indicates an addition instruction, the node N2 indicates a multiplication instruction, and the node N3 indicates a subtraction instruction. The node N4 indicates a decrement instruction, and the node N5 indicates an increment instruction. Node N
The commands 1, N2, N3 are two-input commands, and the node N
The commands N4 and N5 are one-input commands. The calculation result of the node N1 is referred to by the nodes N2 and N3. In this case, copy processing is performed in the program storage unit 1.

Next, the copy process will be described.
First, the data flow program 10 reads the contents of the addressed line based on the destination information of the input data packet. At this time, with / without copy information 1
If 3 indicates "absent," a data packet in which the contents of the destination field and the instruction field are updated is output, and the process ends.

On the other hand, if the copy presence / absence information 13 indicates "present", a data packet in which the contents of the destination field and the instruction field are updated is output, and
Destination information 11, command information 12 stored in the next line,
The copy presence / absence information 13 and the constant presence / absence information 14 are read. If the copy presence / absence information 13 read from the next row indicates “absent”, the same data as the input data packet is stored in the data 1 field of the new data packet and the new data packet The currently read destination information and instruction information are respectively stored in the destination field and the instruction field of, and the new data packet is output. With copy / read from the next line
If the non-information 13 indicates "present", the same copy process is further performed.

In the above information processing apparatus, if the packet data is processed according to the data flow graph shown in FIG. 8, only 3 steps are required. In order to perform such arithmetic processing, the arithmetic processing unit 3 uses a pipeline processing method.

An arithmetic processing unit using the pipeline processing method is described in the document “Floating point processors, 1989. IEEE In.
ternational Solid state Circuits Conference, DIGES
T OF TECHNICAL PAPERS ", pages 46 and 47.

FIG. 9 is a block diagram showing an outline of the arithmetic processing unit shown in the above document. In FIG. 9, the arithmetic processing unit includes an input unit 16, an output unit 17, a multiplication unit 18, an accumulator 19, a preprocessing unit 20, and a logical arithmetic operation unit 22.
And a post-processing unit 21.

The input section 16 has its input side connected to the output of the paired data detection section 2 (FIG. 5) and its output side connected to the multiplication section 1.
8 and the preprocessing unit 20. The output side of the output unit 17 is connected to the input side of the program storage unit 1 (FIG. 5). The output of the multiplier 18 is the accumulator 1
It is connected to the input side of the output unit 17 via 9. The output side of the preprocessing unit 20 is connected to the logical arithmetic operation unit 22. The output side of the logical arithmetic operation unit 22 is the post-processing unit 21.
Is connected to the input side of the output unit 17 via.

That is, the arithmetic processing unit is the input unit 16
From the multiplication unit 18, the accumulator 19, the output unit 17
From the input unit 16 to the preprocessing unit 20,
It has two parallel transmission paths each including a logical arithmetic operation unit 22, a post-processing unit 21, and a data path reaching the output unit 17.

In operation, the input section 16 and the output section 1
7 converts 2 words (operand data of data 1 field and data 2 field) included in the input packet data into 1 word for internal processing. The multiplication unit 18 multiplies two data converted into one word in the integer operation. The accumulator 19 is used to implement multiplication in integer multiplication instructions. The preprocessing unit 20 recognizes the floating point arithmetic operation instruction, reintegrates the data for the floating point arithmetic operation, and supplies it to the logical arithmetic operation unit 22. However, if the instruction is not a floating point arithmetic instruction, the given data is given to the logical arithmetic operation unit 22 as it is. The logical arithmetic unit 22 has a plurality of functions such as floating point arithmetic, logical arithmetic, and integer arithmetic,
Various operations are executed based on the instruction information included in the instruction field of the data packet. The post-processing unit 21 converts the floating point calculation result into normalized data. As for the other calculation results, the supplied data are sequentially output to the output unit 17.

According to the arithmetic processing section, the two operand data can be processed based on the instruction information included in the packet data output from the paired data detection section 2.

FIG. 10 is a diagram for explaining the processing time of the arithmetic processing section of FIG. Processing time "1" in FIG.
Is a time based on the processing time of the logical arithmetic operation unit 22. Based on the comparison with the reference unit, the multiplication unit 1
8 is the processing time 2, the processing time of the accumulator 19 is the processing time “1”, the processing time of the pre-processing unit 20 is the processing time “0.5”, and the processing time of the post-processing unit 21 is the processing time “0. 5 ”.

[0021]

In the arithmetic processing unit described in the above-mentioned document, all the other input data except the integer multiplication pass through the preprocessing unit 20, and all the other arithmetic results except the multiplication result are rearward. It passes through the processing unit 21. Therefore, the processing time of “0.
5 "is required, and the processing time" 0.5 "is required to perform the processing of passing through the post-processing section 21.

However, of the data processed by the logical arithmetic operation unit 22, data other than the floating point is converted to the preprocessing unit 2
No reintegration at 0 and conversion to normalized data at post-processing unit 21 is performed, it simply passes through these processing units 20 and 21. The total processing time "1" required for the processing for this passage is useless.

Further, although all the multiplication results are given to the accumulator 19, all the multiplication results do not have to be accumulated, and the processing time "1" for passing through the accumulator 19 is wasted.

An object of the present invention is to eliminate useless passage processing and shorten the arithmetic processing time in the above-mentioned conventional technique.

[0025]

A data flow type information processing apparatus according to the present invention comprises a plurality of arithmetic processing means, program storage means, paired data detection means and judgment means.

A plurality of arithmetic processing means are provided in parallel. The program storage means stores a data program in which the instruction information includes an identification code corresponding to the plurality of arithmetic processing means and an individual instruction code corresponding to the arithmetic instruction, and based on the destination information included in the input data packet. At least the next destination information and instruction information are read from the data program, and a data packet including the destination information and instruction information is output.

The pair data detection means receives the data packet output from the program storage means, detects two data packets having the same destination information, converts them into one data packet, and outputs it.

The judging means judges the arithmetic processing means corresponding to the identification code among the plurality of arithmetic processing means based on the identification code included in the data packet output from the paired data detecting means, and judges the arithmetic processing means. Output the data packet to.

[0029]

In the data flow type information processing apparatus according to the present invention, a plurality of arithmetic processing means are provided in parallel. The data packet output from the paired data detection means includes an identification code for identifying the plurality of arithmetic processing means and an individual instruction code, and the determination means is one of the plurality of arithmetic processing means based on the identification code. It is determined by which of the arithmetic processing means the arithmetic instruction corresponding to the individual instruction code is executed. The arithmetic processing means provided with the individual instruction code executes the arithmetic instruction corresponding to the individual instruction code. As a result, the data contained in each data packet is given only to the arithmetic processing means necessary for the processing and does not pass through the other arithmetic processing means, so that a wasteful transit time in the arithmetic processing can be eliminated as in the conventional example. .. Therefore, it is possible to shorten the time required to process the data.

[0030]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data flow type information processing apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing a field structure of a data packet processed by the information processing apparatus of FIG.

The data packet shown in FIG. 2 includes a destination field, a command field, a data 1 field and a data 2 field. Destination information is stored in the destination field, the processing unit identification number and the individual instruction code are stored in the instruction field, and the operand data is stored in the data 1 field or the data 2 field. The processing unit identification number is provided corresponding to the multiplying unit 18, the floating point arithmetic unit 23, the logical arithmetic unit 24, the integer arithmetic unit 25, and the like of the arithmetic processing unit 3'to be described later. For example, the number 1 for the multiplication unit 18, the number 2 for the floating point arithmetic unit 23, the number 3 for the logical arithmetic unit 24,
The integer arithmetic unit 25 is numbered 4. The individual instruction code is an instruction code for causing the multiplication unit 18, the floating point arithmetic unit 23, the logical arithmetic operation unit 24, the integer arithmetic unit 25, and the like to execute the instruction.

The information processing apparatus shown in FIG. 1 includes a program storage unit 1 ', a paired data detection unit 2, an arithmetic processing unit 3', a merging unit 40, a branching unit 50, and an external program storage unit 6.
Including 0. The merging unit 40 is provided on the input side of the program storage unit 1 ′, the branching unit 50 is provided on the output side of the paired data detection unit 2, and the external program storage unit 60 is provided on the output side of the branching unit 50 and the merging unit 40. It is provided between the input side. The merging unit 40 and the branching unit 50 have a packet buffering function. The external program storage unit 60 is slower than the program storage unit 1 ', but the program storage unit 1'
It has a larger memory capacity than the above and holds data that cannot be processed by the program storage unit 1 '. The external program storage unit 60 may not be provided if the storage capacity of the program storage unit 1'is sufficient.

The data flow program 10 'shown in FIG. 3 is stored in the program storage unit 1'. The data flow program 10 'of FIG. 3 is different from the data flow program 10 of FIG. 7 in that the instruction information is divided into a processing section identification number 12a and an individual instruction code 12b. As shown in FIG. 3, the program storage unit 1 ′ uses the data flow program 10 by addressing based on the destination information of the input data packet.
Destination information 11, processing unit identification number 12a, individual instruction code 12b, copy presence / absence information 13 and constant presence / absence information 14, and the destination information 11, processing unit identification number 12a, and individual instruction information 12b are data packets. In the destination field and the instruction field of each of them and output the data packet.

The configuration and operation of the paired data detector 2 are shown in FIG.
The configuration and operation of the paired data detection unit 2 shown in FIG.

The arithmetic processing section 3'includes an input section 16 ', an output section 17, a multiplication section 18, an accumulator 19, and a preprocessing section 2.
0, a post-processing unit 21, a floating point arithmetic unit 23, a logical arithmetic unit 24 and an integer arithmetic unit 25. Floating point arithmetic unit 2
3, the logical arithmetic operation unit 24 and the integer operation unit 25 are shown in FIG.
The logical arithmetic operation units 22 in are subdivided and arranged in parallel.

The input section 16 'has a branch section 50 on the input side.
Is connected to the output side of, and the output side is connected to the multiplication unit 18, the preprocessing unit 20, the logical operation unit 24, and the integer operation unit 25. The output side of the multiplication unit 18 is connected to the accumulator 19 and the output unit 17. The output side of the accumulator 19 is connected to the output unit 17. The output side of the preprocessing unit 20 is connected to the floating point arithmetic unit 23, and the output side of the floating point arithmetic unit 23 is connected to the output unit 17 via the postprocessing unit 21. The output sides of the logical operation unit 24 and the integer operation unit 25 are connected to the output unit 17. Output part 1
The output side of 7 is connected to the merging section 40.

The input unit 16 'sends the packet input based on the processing unit identification number included in the data packet to the arithmetic unit and the processing unit corresponding to the processing unit identification number. The multiplication unit 18, the floating point arithmetic unit 22, the logical arithmetic unit 24, and the integer arithmetic unit 25 execute arithmetic instructions based on the individual instruction codes given thereto.

With the above configuration, it is possible to process all multiplications, floating point operations, logical operations and integer operations in parallel. Further, by connecting the multiplication unit 18 and the accumulator 19 in parallel to the output unit 17, it becomes possible to give only the multiplication result that requires the accumulation rate to the accumulator 19.

The operation of this data flow type information processing apparatus will be described with reference to FIGS.

First, the packet data shown in FIG. 2 is supplied to the program storage unit 1'through the merging unit 40. The program storage unit 1'accesses the data flow program 10 'shown in FIG. 3 based on the destination information included in the packet data, and outputs a data packet storing the processing unit identification number 12a and the individual instruction code 12b. The paired data detection unit 2 waits for packet data including the same destination information among the data packets from the program storage unit 1 ', and when the data including the same destination information is prepared, the two data packets are converted into one data. It is converted and given to the branch unit 50.

Also, the paired data detection unit 2 attaches an identification tag of unprocessed data packet to the program storage unit 1 ′ that cannot be processed and outputs it to the branch unit 50. If there is an unprocessed identification tag, the branch unit 50 sends this data to the external program storage unit 60 and temporarily stores it there. The data stored in the external program storage unit 60 is given to the program storage unit 1 ′ through the merging unit 40 and processed again.

The branching unit 50 receives the data from the paired data detecting unit 2.
A data packet having one data set is given to the input unit 16 'of the arithmetic processing unit 3'.

The input unit 16 'outputs the input data packet based on the processing unit identification number 12a included in the input data packet to the arithmetic unit and the processing unit corresponding to the processing unit identification number 12a. For example, processing unit identification number 1
When 2a corresponds to the multiplication unit 18, the data packet is output to the multiplication unit 18, and when the processing unit identification number corresponds to the floating point arithmetic unit 23, the data packet is output to the preprocessing unit 20, When the processing unit identification number corresponds to the logical operation unit 24, the data packet is output to the logical operation unit 24, and when the processing unit identification number corresponds to the integer operation unit 25, the data packet is changed to the integer operation unit 25. Output to.

The multiplier 18 processes the operand data included in the data packet according to the individual instruction code included in the data packet. The multiplication result by the multiplication unit 18 is given to the output unit 17 as it is when the accumulator is not required, and is given to the accumulator 19 when the accumulator is required. The calculation result processed by the accumulator 19 is output by the output unit 17
To the outside or the merging portion 40.

The preprocessor 20 recognizes the floating point operation based on the individual instruction code and reintegrates the operand data. The re-integrated operand data is
It is given to the post-processing unit 21 after being arithmetically processed by the floating point arithmetic unit 23. The post-processing unit 21 converts the floating-point calculation result into normalized data and then supplies the normalized data to the output unit 17. The output unit 17 gives the normalized data to the outside or the merging unit 40. The logical operation unit 24 performs logical operation according to the individual instruction code included in the data packet. The result of this logical operation is given to the output unit 17, and the output unit 17 gives the given data to the outside or the merging unit 40. The integer calculation unit 25 performs integer calculation on the operand according to the individual instruction code included in the data packet, and gives the calculation result to the output unit 17. The output unit 17 gives the integer operation result to the outside or the merging unit 40. Junction 40
The data packet given to the
Program storage unit 1 ', paired data detection unit 2, branch unit 5
0 and the path to the arithmetic processing unit 3 ′ or the external program storage unit 60.

The packets output by the arithmetic processing are sequentially output from the output unit 17 in the order of early output. Further, since the respective arithmetic units are connected in parallel, the time required for the arithmetic processing of the data packet is significantly reduced.

FIG. 4 is a diagram showing the processing time of each block of the data flow type information processing apparatus shown in FIG.

In FIG. 4, the processing time is the same as the processing time of FIG. 10, with the processing time of the logical arithmetic operation unit (floating point operation unit, logical operation unit, integer operation unit) as the reference unit "1", and the preprocessing is performed. The processing time of the unit 20, the post-processing unit 21, the multiplication unit 18, and the accumulator 19 is set to the processing time “0.
5 ”,“ 0.5 ”,“ 2 ”, and“ 1 ”.

Next, referring to FIG. 4 and FIG. 10, the processing time shortened by this embodiment is 1. General case,
2. Worst case, 3. The best case will be described separately.

1. As a general case, consider a case where a data packet is processed in the order of floating point arithmetic, logical arithmetic, multiplication and accumulator, and integer arithmetic.

In the conventional example (FIG. 10), the preprocessing section 20 and the postprocessing section 21 are all except the multiplication and accumulator.
2 x processing time "0.5" for passing
Is required. Therefore, in order to perform the arithmetic processing according to the above-described order, the processing time “2” for the floating point operation, the processing time “2” for the logical operation processing, the processing time “3” for the multiplication and the accumulator, The processing time "9", which is the total of the processing times "2" for integer arithmetic, is required.

On the other hand, in this embodiment (FIG. 4), the data packet passes through the pre-processing unit 20 and the post-processing unit 21 only in the case of floating-point arithmetic, so if the arithmetic processing is executed in the order described above, the floating Processing time "2" for decimal point operation, processing time "1" for logical operation, processing time "3" for multiplication and accumulator, and processing time "1" for integer operation " 7 ”is required. Therefore, the efficiency of the arithmetic processing is about 1.
24 times better. 2. As the best case, a case where a logical operation or an integer operation is performed four times in succession will be taken as an example. In the conventional example, 4 × processing time “2” = processing time “8” is required.

On the other hand, in this embodiment, 4 × processing time “1” = processing time “4” is required. Therefore, the calculation processing efficiency is improved twice as compared with the conventional example. 3. As a worst case, the case where the multiplication and the accumulator are repeated four times is taken as an example.

In the conventional example, 4 × processing time “3” = processing time “12” is required. On the other hand, in this embodiment, 4 ×
Processing time “3” = processing time “12” is required. Therefore, in the worst case, the calculation processing efficiency is the same as that of the conventional example.

As described above, in this embodiment, even in the worst case, the processing efficiency is not lower than that of the conventional example, and in the best case, the processing efficiency can be doubled.

[0057]

As described above, according to the present invention, the data included in each packet data is given only to the necessary arithmetic processing means and does not pass through the other arithmetic processing means. The effect that the calculation processing time can be shortened is eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data flow type information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a field structure of a data packet processed by the embodiment.

FIG. 3 is a diagram showing a part of a data flow program stored in a program storage unit of the data flow type information processing apparatus of FIG.

FIG. 4 is a diagram showing a processing time of each block of the data flow type information processing apparatus shown in FIG.

FIG. 5 is a diagram showing an example of a configuration of a conventional data flow type information processing device.

FIG. 6 is a diagram showing a field structure of a data packet processed in the data flow type information processing apparatus.

FIG. 7 is a diagram showing a part of a data flow program stored in a program storage unit of the data flow type information processing apparatus.

FIG. 8 is a diagram showing a part of a data flow graph including a copy process.

FIG. 9 is a block diagram showing a configuration of a conventional arithmetic processing unit.

10 is a diagram showing a processing time of each block of the arithmetic processing unit shown in FIG.

[Explanation of symbols]

 1'Program storage section 2 Pair data detection section 3'Operation processing section 16 'Input section 17 Output section 18 Multiplying section 19 Accumulator 20 Pre-processing section 21 Post-processing section 23 Floating-point operation section 24 Logical operation section 25 Integer operation section

Claims (1)

[Claims] 1. A data flow type information processing apparatus for processing a data packet based on a data program including a plurality of sets of destination information and instruction information, wherein a plurality of arithmetic processing means arranged in parallel, said instruction. A data program in which information includes identification codes corresponding to the plurality of arithmetic processing means and individual instruction codes corresponding to arithmetic instructions is stored, and at least the data program is stored based on the destination information included in the input data packet. Program storage means for reading out next-order destination information and instruction information and outputting a data packet including those destination information and instruction information; two data having the same destination information for receiving the data packet output from the program storage means Paired data that detects a packet, converts it into one data packet, and outputs it Based on the identification code included in the data packet output from the detection means and the paired data detection means, the arithmetic processing means corresponding to the identification code among the plurality of arithmetic processing means is determined, and the determined arithmetic processing means is determined. A data flow type information processing device, characterized in that it comprises a determination means for outputting a data packet.