JPH0648499B2 - Processing unit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a processing unit of a data flow processor that connects a memory unit and an arithmetic unit by a pipeline bus and controls the arithmetic order by a data driven method. Is.

[Prior Art] Conventionally, JP-A-56-16915 has been used as a data flow processor.
There is a technology described in Japanese Patent Publication No. 2 and a μPD7281 manufactured by NEC Corporation is a commercialized product. μ
The PD7281 has a structure as shown in FIG. This μPD
According to 7281, a token that is a unit of data input to a device from an external bus has a data value, an identifier for referring to the link table 92 after input, and a module number indicating the device on which the token is to be processed. The token input unit 91 inputs the token internally when the module number of the token passing through the external bus matches the device number, and otherwise outputs the token directly from the external bus through the token output unit 97. The input token refers to the link table 92 by this identifier, and obtains the function table address for referencing the function table 93 and the identifier for referencing the link table 92 next time, and then the function table 93 is obtained.
Sent to.

The token refers to the function table address in the function table 93, refers to / updates the management information of the data memory 94, and at the same time, accesses the processing code indicating the processing content in the processing unit 96 and the data memory 94. The address is obtained and sent to the data memory 94, where the operand of the partner of the binary operation is waited for, or the constant is read for constant operation. The queue memory 95 is a memory for temporarily holding the token when the processing unit 96 is processing the previous token and cannot input the token, and when the processing unit 96 is not busy, the token is transferred from the queue memory 95 to the processing unit 96. Depending on the processing code, add / subtract multiplication of integer data, logical operation, shift, comparison, bit inversion, priority encoding, shunting, numerical value generation, copy, cumulative addition operation using internal register, etc.
Receive one treatment. If the processing code of the token indicates output, the token is the queue memory.
It is sent from 95 to the token output unit 97, transformed into the same shape as the input token, and then output to the external bus. The token processed by the processing unit 96 is sent to the link table 92, and again referred to by its identifier. In the same manner, it goes around the internal ring bus until the output instruction is executed, and receives the necessary processing for the data value.

[Problems to be Solved by the Invention]

In numerical calculation used in application fields such as numerical simulation and pattern recognition, it is necessary to handle floating-point data in order to ensure the accuracy of the data. In particular, multiplication of matrices and vectors with floating-point data as elements and matrix-to-matrix Multiplication is frequent in these applications.

Consider the case where so-called convolution processing is performed in the above-described data flow processor, in which a plurality of data existing in such a multiplication are multiplied by a certain coefficient and the sum of their products is obtained. In the conventional data flow processor, there is only one arithmetic unit, and when the token goes around the inner ring and enters the processing unit, only one binary operation between the two data of the token can be performed. In the case of volume, N tokens must go around the inner ring and flow into the processing unit N times to perform multiplication of N data sets, and (N-1) times to perform addition of the result. There is a problem that the processing time becomes long because the addition has to be performed serially in terms of time.

Among the above problems, the μPD7281 has a register in the processing unit to perform cumulative addition in order to speed up the addition of continuous data, but even this can only perform multiplication or addition at a time, so multiplication Can't speed up. Therefore, in order to speed up the convolution, a multiplier for multiplying the coefficient by the input data and an arithmetic unit for cumulatively adding the products by using the register must be arranged in a column.

On the other hand, in the above-mentioned data flow processor, since the supported arithmetic operation processing is limited to addition / subtraction multiplication for integer data, it is not possible to execute the processing that requires the operation of the data of the floating point representation other than these When trying to do so, it had to be realized by software, which caused an increase in processing time.

In order to solve this, it is possible to provide a processor in which the processing unit of the data flow processor incorporates the floating point arithmetic hardware used in a normal processor. But in this case
Floating-point operations require longer processing time than other fixed-point operations.Therefore, in data flow processors that perform token transfer inside the processor in synchronization with the pipeline clock, the entire operation pipeline cycle must be lengthened. Inevitably, there arises a problem that the overall processing speed decreases.

On the other hand, in general, when the floating point arithmetic unit requires complicated processing in this way, the internal clock is divided into a plurality of stages, and each stage is operated in a pipeline manner to shorten the entire clock cycle. The approach is taken. However, even in this case, for example, when the cumulative addition of the elements in the vector is taken, the next addition cannot be started unless the operation for taking the previous sum is completed. Only takes processing time.

For example, an m × n matrix A (element a [i, j]) each having floating point data as an element and a vector (element x [j] of length n multiplied by A = A are calculated from the floating point multiplier and the s stage. Consider a case where the data flow processor has a pipelined floating point adder.

In order to obtain, the sum of n products must be obtained in order to perform the cumulative addition of the results after the multiplication of two data strings that are continuously input. Therefore, for (n-1) times of addition, one addition takes s steps, and all the additions have to be performed serially in terms of time, so s * (n-1) steps. Therefore, it takes s × (n−1) × m steps in total.

An object of the present invention is to solve the above-mentioned problems, to execute a product-sum operation using data in floating-point representation without degrading the pipeline performance as much as possible, and to provide a data flow processor capable of speeding up the above-mentioned processing. It is to provide a processing unit.

[Means for Solving the Problems]

The processing unit according to the present invention is a token on the token having control information and operand data input from the internal memory unit via the bus.
An arithmetic calculation unit that calculates one operand data and outputs a token having result data; and result data on the output token of the arithmetic calculation unit, and
A register file composed of a plurality of registers for temporarily holding the intermediate result of the addition, an operation of the result data on the output token of the arithmetic calculation unit and the data read from the register file, and sending the result to the register file , A delay circuit for synchronizing the control information on the output token of the arithmetic calculation unit with the data passing through the adder, and the result output data of the adder and the control information obtained from the delay circuit It is characterized by comprising a result token generation unit for generating a token having result data.

[Action]

In the data flow processor having the processing unit of the present invention, when the matrix A and the vector are multiplied, the vector elements x [1], x [2] ,.
., X [n] is given from the outside and held in the internal memory. At the time of processing, the element data a [1,
1], a [2, 1], ..., a [m, 1], a [1, 2], ...
., A [m, 2], ..., a [1, n], ..., a [m, n]
The n × m number of tokens having in this order are input to the data flow processor. The inputted token obtains a vector element and a processing code which are the counterpart data of the binary operation required when passing through the internal memory. The other party data are x [1], ..., x [1] (m pieces), x [2] ,.
[2], ..., X [n], ..., X [n] are accessed m × n.

Tokens having two operands are successively input in sequence to the arithmetic calculation unit that constitutes the preceding stage of the processing unit. There, the two input operands are multiplied, and the product p [i,
j] = a [i, j] * x [j] whose data is p [1,1], p [2,1], ..., P [m, 1], p
.., p [1, n], ..., P [m, n] are transmitted in this order. In the accumulator, the partial sum q [1, k-1] = q [i, 1] of the i-th row is used by using it as a FIFO of register length m in the internal register file.
+ ··· + p [i, k-1] is cyclically held until p [i, k] is input, and the held partial sum comes next with a delay of m clocks to be added next data. These are sent to the adder to be synchronized with. In the adder, the consecutive incoming operand sets are independent from each other, such as for the (i-1) th column, for the i-th column, and for the (i + 1) th column, so that each stage of the pipeline is Can be used full to add, and after the addition the partial sum of the results is again held in the register file.

While m × n sets of data are input in this way, m
The sum of products can be obtained by an adder that operates in a pipeline manner.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is an internal block diagram showing the overall configuration of the data flow processor 1 according to one embodiment of the present invention. 10 is a token input unit, 11 is a link table, 12 is an operand fetch table, 13 is a data memory, and 14 is Function table, 15 is a buffer queue, 16 is a processing unit, 17 is a token output section, and a link table
11, operand fetch table 12, data memory 13,
The function table 14, the buffer queue 15, and the processing unit 16 are connected in a ring shape by a pipeline type bus in this order as shown in the figure, and tokens are transferred on this internal ring bus. Further, the processing unit 16 has an arithmetic calculation section 20 and a cumulative addition section 21 arranged in a column.

FIG. 3 is an overall configuration diagram of an example of a data processing device using the data flow processor of FIG. In this data processing device, a plurality of data flow processors 1 ...
2 and one memory interface circuit 3 are external buses 5
The external bus 5 is connected to the memory 4 via the memory interface circuit 3. The token is transferred asynchronously on the external bus 5 by the handshake method.

FIG. 4 is a data flow processor of FIG.
The format of the token which is a unit of data used by the data processing apparatus of the figure is shown. External bus 5 shown in FIG. 4 (a)
The token 60 above is composed of a module number 61, a control flag 62, a link table address 63 and a data section 64. The control flag 62 is used to distinguish the token used when the program is loaded into a table inside the data flow processor such as the link table 11 before executing the program from the execution token when executing the process.

The token input unit 10 fetches only the tokens whose module number 61 is equal to the number given to the device among the tokens inputted from the preceding data flow processor or memory interface circuit into the link table 11
It is sent in synchronization with the pipeline cycle, and other tokens are sent to the token output unit 17 as pass tokens as they are. However, the link table that should be sent for it
If the token output unit 11 or the token output unit 17 is in a busy state, the token is not sent and the input from the previous data flow processor or the memory interface circuit is stopped by not returning the handshake acknowledge signal.

The link table 11 inputs a token from the processing unit 16 or the token input unit 10, but when both input requests are made simultaneously, the input from the token input unit 10 is prioritized. The link table 11 is referred to by the link table address 63 of the token 60 input from the processing unit 16 or the token input unit 10, and the token is the address that accesses the operand fetch table 12, the address that accesses the function table 14, and the next link table. 11 Get link table address for lookup Operand fetch table 12
Sent to.

The operand fetch table 12 is referred to by the operand fetch table access address read from the link table 11 of the input token 60, and the read / write / data of the data memory 13 at the address is read.
Refers to the instruction code for term queue control, and refers to and updates the information for status management. As a result, the token receives the access address of the data memory 13 and the data memory processing code designating the operation in the data memory 13.

The data memory 13 is accessed by the data memory access address of the input token 60, and if necessary, 2
It is used as a queue for waiting for data of term operations or as a memory for temporarily storing one operand data for a binary operation. For example, a data memory read token having a first operand for a binary operation when the data input from the external memory to the data flow processor in advance is held by being written in consecutive addresses in the order of the data memory 13 and then arithmetic processing is performed. Then, the written data is read from the data memory 13 and the read data is added to the token as the second operand, so that it can be used for the binary operation in the processing unit 16. Furthermore, at the exit of the data memory 13, the first operand and the second operand can be exchanged according to the data memory processing code.

The token input in the function table 14 is
The internal table is accessed by the function table access address. As a result, a processing code indicating the processing content of the processing unit 16 is added to the token. At the same time, the link table address part of the flowing token is changed by the internal state stored in the function table 14 to control the flow as necessary. Further, instead of the flow control operation described above, the data in the internal state holding unit can be added to the token as the second operand and input to the processing unit 16 together with the data of the first operand held when the function table 14 was input. it can. Note that the processing code fetched in the function table 14 is an arithmetic calculation unit processing code that specifies processing in the arithmetic calculation unit 20, a cumulative addition unit processing code that specifies processing in the cumulative addition unit 21, and processing of the processing unit 16. The output selection code specifies whether to send the token having the result to the link table 11 or the token output unit.

The buffer queue 15 is a FI for temporarily holding the token before inputting the token to the processing unit 16.
It is an FO memory, and stops the output to the processing unit 16 when the processing unit 16 is stopping the token input. The format of the token when sent from the buffer queue 15 to the processing unit 16 is shown in the token 65 of FIG. 4 (b). The token 65 has a control flag 69, a link table address 70, a first operand 71 and a second operand 72 to be processed, and further, an arithmetic calculation unit processing code 66 fetched in the function table 14, a cumulative addition unit processing code 67, Has output selection code 68.

The processing unit 16 is, as shown in FIG.
The arithmetic calculation unit 20 and the cumulative addition unit 21 are configured to be connected in series, and when the input tokens pass through those operating independently, they act on these tokens in a pipeline manner.

The arithmetic calculation unit 20 is the arithmetic calculation unit processing code of the processing codes fetched by the function table 14 for the binary operation of the first operand and the second operand of the token input to it, or the unary operation of the first operand. The token having the result data is output to the cumulative addition unit 21 via the signal line 101. The arithmetic operations include arithmetic operations, logical operations, shifts, comparisons, bit operations and the like. In particular, if the data that the token has is floating-point data, and the token has a processing code that instructs floating-point multiplication, the multiplication is performed between the two input floating-point data, and the token that has the resulting floating-point data Is the result token. Since the arithmetic calculation unit 20 raises the entire pipeline clock, the hardware can be divided into a plurality of stages that operate in a pipeline manner.

The cumulative addition unit 21 sends the data to the adder 22 according to the cumulative addition unit processing code of the token input from the arithmetic calculation unit 20 through the signal line 101, and sends the data to the register file 23.
The data read from can be added, or the value can be set in an appropriate register in the register file 23. The input token from the arithmetic calculation unit 20 is held in the input token register 30, and the data value to be processed among the contents is output to the signal line 102, and the other token information for control is output to the signal line 107. As token information on the signal line 107, the link table address 70, the control flag 69, the cumulative addition unit processing code 67, and the output selection code 68 which the input token 65 for the processing unit 16 shown in FIG. is there. In particular, the register file 23
Write control code, read control code, result token generation control code, and output selection code 68,
As a result, a flag indicating whether to output the token to the token output unit 17 or the link table 11 and a module number to be possessed when the token output unit 17 outputs to the external bus are included.

The register file 23 consists of r registers, and the signal 109 is sent from the register file write control unit 24 to the signal line.
The above data is written to the specified register. The register file write control unit 24 uses signal 107 or signal 10
Controlled by the register file write control code of 8, the data input from the signal line 102 or 104 is sent to the designated register in the register file 23 by the signal line 10
Write through 5. Signal 107 and signal 108
Prioritize. The register file read control unit 25 sends the signal 10
It is controlled by the register file read control code 7 and the data of the designated register among the registers of the register file 23 is output to the signal line 103.

The adder 22 performs a pipelined addition operation on the two floating point data on the signal lines 102 and 103, and outputs result data having the same format to the signal line 104. Fifth
The figure shows an example of the adder 22 including five stages. In this example, the data to be handled conforms to the floating point format of the IEEE754 standard, and after the exponent part and the mantissa part of each data are separated, the operation is carried out while holding each in order by the internal 5-stage latches. . In FIG. 5, L is a latch for forming each stage of the pipeline. The operation will be briefly described below. The two input data are compared by the comparison / selection unit 150, and the larger exponent part of the two data in the signal 151, the mantissa part thereof in the signal 152, and the mantissa part of the smaller data in the signal 153,
The absolute value of the difference between the two exponents is selectively output as the signal 154. The mantissa part of the smaller data is right-shifted by the right shifter 155 by the difference of the exponent part and added to the other mantissa part by the adder 156. The number of consecutive zeros in binary notation from the uppermost result is counted by the zero counter 157, and the sum of the mantissas is left-shifted by the left shifter 158 by that number to obtain the mantissa part of the normalized operation result. At the same time, the output of the zero counter 157 is also added to the larger exponent of the original by the adder 159 to obtain the exponent of the operation result. Although the number of pipeline stages of the adder 22 is 5 here,
In the description below, the number of stages is generally assumed to be s.

The delay circuit 26 is configured by connecting s latches for delay in series, and delays the token information on the signal line 107 by s stages to generate a result token in synchronization with the operation data passing through the adder 22. It is used for sending to the unit 25 and the register file write control unit 24.

The result token generation unit 29 is controlled by the result token generation control code of the signal 107, and the link table address, the control flag, and the control flag among the token information sent to the floating point result data 104 output from the adder 22 via the signal line 107. An output selection code is added to format the output token from the processing unit 16, and the result token is output to the signal line 110 at a designated timing.

The output token from the processing unit 16 is normally sent to the link table 11, but when the token has an output selection code indicating that it should be output to the outside of the data flow processor, the external bus in the output selection code is used. The module number necessary for the token is added to the token and sent to the token output unit 17. However, when the token output unit 17 is in the busy state, the output to the token output unit 17 is stopped, and the input from the buffer queue 15 to the processing unit 16 is also prohibited.

The token output unit 17 outputs the token input from the processing unit 16 or the token input unit 10 to the subsequent data flow processor or memory interface circuit 3 via the external bus 5. However, when there is a request from both the processing unit 16 and the token input unit 10 at the same time, the input from the token input unit 10 is prioritized, and the processing unit 16 is sent a signal notifying that it is busy. Stop accepting tokens from the processing unit 16. Also, when the data flow processor or the memory interface circuit in the subsequent stage is busy and does not return the handshake acknowledge signal, the output is stopped, and the token reception from the processing unit 16 is also stopped.

In the processing unit described in the above embodiment, the number of stages s forming the adder 22, the number r of registers of the register file 23, and the size of the matrix A in the multiplication problem of the matrix A and the vector to be handled in the present invention. m
For xn, r ≧ m ≧ s must hold.

Next, using the present embodiment, for example, the matrix A as described above
The operation when the arithmetic processing of (size m × n) × vector (size n) is performed will be described. In the embodiment, the number of stages s = 5 constituting the adder 22, the register file
The number of registers of 23, r = 32, and m = 32, according to the above conditions. Although m = r here, if m <r, the access register is selected so that only m of the r registers of the register file 23 are used as the FIFO, and the same process is performed. To be

First, prior to the calculation, vector elements x [1], x [2],
.., x [n] is set in the data memory. Next, tokens having elements of the matrix A to be used for processing are sequentially input from the external memory 4 to the data flow processor via the memory interface circuit 3. At this time, a [1,1], a [2,1], ..., a [m, 1], a [1,2], a [2,2], ..., a [m, 2 ], ... a [1, n], a [2, n], ..., a [m, n], in this order, so that the element data of m × n matrixes are input in the external memory 4 To access.

The input token is input to the link table 11 from the token input unit 10, and in the operand fetch table 12, vector elements of the data memory 13 are input in the order of x [1] m times, x [2] m times, .., x [n] is controlled to be accessed m times. As a result, the set of two operands when input to the processing unit 16 is (a [1,1], x [1]), (a [2,1], x [1]), ..., (a [m, 1], x [1]), (a [1, 2], x [2]), (a [2, 2], x [2]), ..., (a [m, 2]) , X [2]), ... (a [1, n], x [n]), (a [2, n], x [n]), ..., (a [m, n], x [n]).

Next, each token in the function table 14 fetches a processing code designating the processing content in the processing unit 16. As described above, there are the following types of processing codes, and each of them is shown below together with the contents of the mnemonics used in the following description.

1. Code fmul that defines processing in the arithmetic calculation unit 20: Floating point multiplication of two input operands 1. Control code for writing register file of cumulative addition unit w0: cyclically write data on signal line 102 w1: cyclically write data on signal line 104 3. Control code for reading register file of cumulative adder 21: rdcyc: Read register cyclically-: Do not read 4. 4. Token generation control code of accumulative addition unit 21 fadd: token generation −: output token is not generated Output selection code out: Send the token to the token output unit 17-: Send the token to the link table 11.

Assuming that these five code groups are shown in parentheses for each token in order, the code groups for m × n tokens that flow in this process are as follows: (fmul, w0,- ,-,-) For the next m × (n-2) pieces: (fmul, w1, rdcyc,-,-) For the last m pieces: (fmul,-, rdcyc, fadd, out) . Processing unit
The m × n tokens having the data to be calculated in 16 and the processing code therefor continuously flow into the processing unit 16, that is, every clock.

Since the code defining the processing is fmnl for all tokens in the arithmetic calculation unit 20, the floating-point multiplication of the two input operands is performed, and the product of them is also sent to the cumulative addition unit 21 as continuous data. For the sake of simplicity, assuming that p [i, j] = a [i, j] · x [j], the data of the output token of the arithmetic calculation unit 20 is p [1,1], p [2,1] in order. , ..., p [m, 1], p [1, 2], p [2, 2], ..., p [m, 2], ... p [1, n], p [2, n ], ..., P [m, n], which also continuously flows into the cumulative addition unit 21 for each clock.

According to the token processing code input in the above order, the cumulative addition unit 21 a) cyclically writes the data for the first m in the register file 23, b) the next m × (n−2) Register file for
The data read cyclically from 23 and the input data are added by the adder 23, the resulting data is cyclically written to the register file 23, and c) the last m data are cyclically read from the register file 23. Added data and input data
Add in 22, generate a token with the result data,
The operation of sending to the token output section as the output of the processing unit 16 is performed. In this way, by using the register file 23 as a FIFO of length m, the first m tokens are delayed by m clocks and the next p [1, 2], ..., P
It is input to the adder 22 in synchronization with the token in the [m, 2] column. The resulting partial sum (second partial sum) is s in the adder 22.
It is delayed by s clocks to pass through the stage, then is written once in the register file 23, and is read out after (ms) clocks, resulting in a total delay of m clocks, and the next p [1,
3], ..., P [m, 3] will be input to the adder 22 in synchronization with the tokens in the sequence. After that, the sequence of the n-th partial sum is obtained by repeating this, and this is output as the final result from the result token generation unit 29, thereby ending the processing.

FIG. 6 shows an outline of the timing of the data processed by each part of the cumulative addition unit 21 in this processing. In the figure, p
_{i, j} means p [i, j] in the explanation, and Is. Therefore, q _{i, n} = y _i . further It means that during that timing, p _{1, j} , p _{2, j} , ...
It means that p _{m, j} flowed in order, and similarly Is added to the adder 22 as a set of two operands (p _{1, j} , q _{1, j-1} ), (p _{2, j} , q _{2, j-1} ), ..., (p
_{m, j} , q _{m, j-1} ) are input in order. At this time, the output of the adder 22 is of course q _{1, j} , q _{2, j} , ..., Q _{m, j} . Since the adder 22 takes s steps from the input of the set of operands to the output of the result, the operation timings of the register file write control unit 24 and the result token generation unit 29 using the result are delayed by s clocks.

〔The invention's effect〕

As described above, according to the present invention, (1) a plurality of dedicated hardware units for preparing floating-point addition, which requires a large amount of hardware and originally requires a long processing time, and which operates in a pipeline manner It is divided into stages. As a result, the throughput of floating-point calculation can be improved, that is, the effective calculation time can be shortened, and further, the processing pipeline unit and the operation pipeline cycle of the entire data flow processor can be shortened. Processing performance is improved.

(2) Further, by arranging an arithmetic calculation unit capable of floating-point multiplication in parallel with this adder, convolution of floating-point data can be performed only by passing the data through the processing unit once.

(3) When such a pipelined adder is installed, s × (n−1) is set as the number of stages of the adder when calculating the matrix × vector including the conventional product-sum operation.
It took xm steps, but in the present invention, as shown in FIG. 6, the process is completed in about m × n + s steps, and the processing speed can be increased. This is because it is possible to fully operate each pipeline stage of the adder by using the register file.

This has the effect of increasing the speed of numerical calculation processing.

[Brief description of drawings]

1 is a block diagram showing a configuration of an embodiment of a processing unit of the present invention, FIG. 2 is a configuration diagram of a data flow processor using the processing unit of FIG. 1, and FIG. 3 is a data flow of FIG. FIG. 4 is an overall configuration diagram showing an example of a data flow processing device using a processor, FIG. 4 is a diagram showing a format of a token used for explaining the present invention, and FIG. 5 is a block showing an example of configuration of an adder in a cumulative addition unit. 6 and 6 are timing charts showing the operation of the data processing in the accumulator, and FIG. 7 is a diagram showing the configuration of the conventional data flow processor. 16 …… Processing unit 20 …… Arithmetic calculator 21 …… Cumulative adder 22 …… Adder 23 …… Register file 24 …… Register file write controller 25 …… Register file read controller 26 …… Delay circuit 29 ...... Result token generator 30 …… Input token register

Claims (1)

[Claims] 1. A token, which is a unit of data, is sent to a pipeline-shaped bus connecting an internal memory unit and an arithmetic unit,
In a processing unit of a data flow processor that controls an operation order by a data driven method, 2 on a token having control information and operand data input from the internal memory unit via the bus.
An arithmetic calculation unit that calculates one operand data and outputs a token having result data; and result data on the output token of the arithmetic calculation unit, and
A register file composed of a plurality of registers for temporarily holding the intermediate result of the addition, an operation of the result data on the output token of the arithmetic calculation unit and the data read from the register file, and sending the result to the register file , A delay circuit for synchronizing the control information on the output token of the arithmetic calculation unit with the data passing through the adder, and the result output data of the adder and the control information obtained from the delay circuit A processing unit characterized by comprising a result token generation unit for generating a token having result data.