JP2573711B2 - Micro subroutine control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] [Overview] [Industrial Application Field] [Prior Art] FIG.
FIG. 4 is a diagram showing an example of a microprogram and a time chart for explaining nesting of the micro-subroutine control system in FIG. 4 (FIG. 5) [Problems to be solved by the invention] [Means for solving the problems] [ Operation] [Example] Diagram showing an embodiment of the present invention (FIG. 2) Diagram showing an example of a microprogram and time chart for double nesting (FIG. 3) [Effect of the invention] [ Outline] Regarding the micro subroutine control method which enables multiple nesting by adding a small amount of hardware to the existing hardware, with the aim of performing multiple nesting of micro subroutines, the first selection in the address system of the control memory Circuit,
A second selection circuit is provided in the write system and the read system of the main memory, so that the address of the control memory is written to the main memory, read, and supplied to the address system of the control memory.

[Industrial applications]

The present invention relates to a micro subroutine control method that enables multiple nesting by adding a small amount of hardware to existing hardware.

A computer system or the like may be configured to execute the macro instruction by a microprogram. Micro-subroutines are also used in computer systems employing such microprogram control. The micro subroutine of the micro program is configured to suppress the complexity of the micro program. Even in a micro program, there is a case where nesting of the micro subroutine is required and it is necessary to be able to perform the nesting without limiting the number of nesting steps.

[Conventional technology]

FIG. 4 shows a conventional micro subroutine control system.
In this figure, the microinstruction of the main routine read from the control memory 2 is set in a microinstruction register (MiR) 30 in the CPU 19 and is called when the microinstruction is a subroutine call microinstruction. The return address from the subroutine is set in the return address input register (MiA) 38. The NA section 31 of the microinstruction register 30 contains the next address (the microprogram address to be executed next in the microprogram) and the BC section.
33 contains a branch condition information bit (for performing gate control of the contents of the status register 34). The contents of the status register 34 are stored in the E section 35 of the micro instruction register 30 set by the micro subroutine control system.
Is set by the CPU whose operation is regulated in accordance with the contents (the execution instruction information bits of the micro instruction).

The BC unit 33 is used to control the above-mentioned subroutine call. This will be described below. The subroutine read is coded so that the LSB of the microprogram address of the read microinstruction is "0" (described later). In the execution of the subroutine read microinstruction (the microinstruction execution cycle), the return address set in the return address input register 38 in the reading of the subroutine read microinstruction (see the address "M" in FIG. 5).
Is copied to the return address output register (BMiA) 40 (the return address from the subroutine is prepared). The LSB "0" of the next address (NA) of the subroutine read microinstruction (see CALL "SUB" in FIG. 5) read from the control memory 2 and set in the microinstruction register 30 is removed by the multiplexer 36. The result is set in the return address input register 38, and the access of the control memory 2 by the address of the NA section 31 of the microinstruction, that is, the branch to the subroutine is performed. M in FIG. 5 is the LSB of the micro address M1.
Indicates those excluding "0".

Subroutine execution is started from the next microinstruction cycle. Then, the processing of the subroutine is completed, and the return from the subroutine is performed according to the BC field of the microinstruction set in the microinstruction register 30 (FIG. 5).
When RTN is specified, the address in which the LSB of the address set in the return address output register 40 is set to "1" in this microinstruction cycle (see address M1 in FIG. 5) is transferred from the multiplexer 36 to the control memory 2 (see FIG. 5).
Give to. As a result, the main routine is executed from the microinstruction next to the microinstruction in which the subroutine is coded, that is, the return from the subroutine is performed.

[Problems to be solved by the invention]

According to the above-described conventional method, a branch to a subroutine can be made, but a branch from that subroutine to the next subroutine cannot be repeated. This is because there is only a return address output register 40 as hardware that holds an address used for return from a subroutine. Therefore, in this conventional method, nesting of a subroutine for calling a subroutine from another subroutine cannot be performed.

The present invention has been created in view of such problems,
It is an object of the present invention to provide a micro-subroutine control method capable of performing multiple nesting of micro-subroutines in a microprogram while minimizing an increase in hardware and without being restricted by hardware.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, the invention according to claim 1 includes a control memory 2, a return address output unit 8 having an input holding unit 4 and an output holding unit 6, and a microinstruction read from the control memory 2. A control system 10 for holding a return address in the input holding unit 4 when it is a subroutine call microinstruction, a main memory 12, an arithmetic circuit 14,
Arithmetic circuit-memory data transfer system 16, memory-arithmetic circuit data transfer system 18, the input holding unit 4, and the arithmetic circuit
A first selection circuit 20 provided between an output of the output holding unit 6 and an input of the output holding unit 6; an output of the output holding unit 6 and the output of the memory-arithmetic circuit data transfer system 18;
The second selection circuit 22 provided between the input holding unit 4 and the second selection circuit 22 provided between the input holding unit 4 when the subroutine is called from the main routine, or when the subroutine is called one level deeper from a certain subroutine. The return address at the multiplicity is transferred to the main memory 12 via the first selection circuit 20, the output holding unit 6, the second selection circuit 22, the arithmetic circuit 14, and the arithmetic circuit-memory data transfer system 16. Writing control means 24 for transferring the data to the main memory 12 and writing the data to the main memory 12;
The return address at the multiplicity is read from the main memory 12 and the output is held via the memory-arithmetic circuit data transfer system 18, the second selection circuit 22, the arithmetic circuit 14, and the first selection circuit 20. A reading control means 26 to be held by the unit 6 is provided to perform a multiple subroutine nesting process.

(Operation)

By sequentially reading and executing each microinstruction of the microprogram stored in the control memory 2, required processing proceeds in the data processing system. In this process, if the microinstruction read from the control memory 2 is a subroutine call microinstruction, the return address is held in the input holding unit 4 of the return address output system.

When a subroutine is called from the main routine by executing the subroutine call microinstruction or a subroutine is called from a certain subroutine, the return address at the multiplicity held in the input holding unit 4 is written. The control unit 24 controls the first selection circuit 20, the output holding unit 6, the second
Is transferred to the memory 12 via the selection circuit 22, the arithmetic circuit 14, and the arithmetic circuit-memory data transfer system 16 and written into the main memory 12.

The same applies when nesting is further performed in the subroutine read as described above.

As described above, the return from the subroutine nested in the microprogram to the main routine through each subroutine in sequence is the nesting multiple of the return addresses stored in the main memory 12 as described above. The read operation is performed by sequentially reading from the return address having a low severity (return address for returning from the deepest nesting subroutine). Main memory 12
The return address read from the memory is read from the main memory 12 by the read control means 26, and the memory-arithmetic circuit data transfer system 18, the second selection circuit 22,
It is held in the output holding unit 6 via the arithmetic circuit 14 and the first selection circuit 20, and is used for reading a microinstruction from the control memory 2 after return (return).

In the multiple nesting of micro subroutines as described above, the newly provided hardware includes the first
2. The selection circuit 20 of the first and second selection circuits 22.
Only the extensions required for the described invention. Therefore,
With the addition of a small amount of hardware, multiple nesting of micro subroutines can be freely set in a microprogram without any restriction on the amount of hardware.

〔Example〕

FIG. 2 shows an embodiment of the first aspect of the present invention. The CPU 29 shown in this figure includes the components shown in FIG.
That is, in addition to the control memory 2, the micro instruction register 30, the AND circuit 32, the status register 34, the multiplexer 36, the return address input register 38, and the return address output register 40, a driver 56 and a receiver 58 connected to the main memory 12, Read buffer (RB) 46, write buffer (WB) 50, general-purpose register 44, multiplexer 4
8, and an arithmetic logic circuit (ALU) 49, a wiring 52, a wiring 54, and a multiplexer 42 are shown. Driver 56 and receiver 58 as described above, read buffer 46, write buffer 50, general-purpose register 44, multiplexer 48, and
The ALU 49 is provided in a conventional CPU. However, the multiplexer 48 is extended so as to be able to accommodate the wiring 52 as well. The multiplexer 42 and the multiplexer 48 are assigned addresses that can be accessed by microinstructions, that is, the selections supplied via hardware in the CPU 29 (not shown) by the execution of the microinstructions in the CPU 29 of the present invention. The signal is configured to select one of the addresses provided to their respective inputs.

In FIG. 2, the return address input register 38
Corresponds to the input holding unit 4 in FIG. 1, and the return address output register 40 corresponds to the output holding unit 6 in FIG.
The return address input register 38, the return address output register 40, and the multiplexer 36 correspond to the return address output system 8 in FIG. 1, and the microinstruction and the microinstruction register 30 of the control memory 2 correspond to the control system 10 in FIG. Corresponding to The ALU 49 corresponds to the arithmetic circuit 14 in FIG.
The write buffer 50 and the driver 56 correspond to the arithmetic and logic operation circuit-memory data transfer system 16 in FIG.
The read buffer 46 and the general-purpose register 44 correspond to the memory-arithmetic logic operation circuit data transfer system 18 in FIG. The multiplexer 42 corresponds to the first selection circuit 20 in FIG. 1, and the multiplexer 48 corresponds to the second selection circuit 22 in FIG.

The operation of calling the micro subroutine in the above system configuration will be described below.

Branch from the main routine to the first subroutine,
Then, the return from there is exactly the same as the above-described conventional micro subroutine control method, and the description thereof will not be repeated. ((A) and (B) of FIG. 3 show a subroutine call microinstruction in the first stage.

Next, an example of the operation when the second-stage subroutine is called from the first-stage subroutine will be described with reference to FIG.

When the processing in the subroutine of FIG. 3 (A) proceeds and the execution of the microinstruction shown in (4) of FIG. 3 (A) (refer to (A) and (B) of FIG. 3) starts. By executing this microinstruction, return address output register
40 micro-addresses M1, wiring 52, multiplexer 4
8, and transferred to the write buffer 50 via the ALU 49 (see (3) and (5) in FIG. 3B), and
Execution of the microinstruction shown in (5) of FIG. 3 (A) (refer to (A) and (B) of FIG. 3) causes the return address M of the write buffer 50 to become the main memory via the driver 56. It is written into the storage position corresponding to the second-stage subroutine in 12 (see (5) and (6) in FIG. 3B). The wiring 52 of the return address M of the return address output register 40 by the two microinstructions,
Transfer control to write buffer 50 via multiplexer 48 and ALU 49, and driver from write buffer 50
The transfer control to the main memory 12 via 56 is performed by controlling the conventional read buffer 46 or the general-purpose register 44 to the multiplexer 48 and the AL.
U49 and data transfer control to the write buffer 50 and transfer control from the write buffer 50 to the main memory 12 via the driver 56 are performed.

After performing the return processing to the first-stage subroutine, the micro-instruction for calling the second-stage subroutine (see FIGS. 3A and 3B) is executed, and As in the case of branching from the main routine to the first-stage subroutine, a return process to the main routine is performed, and a micro-instruction address generation address A (A0 in the same manner as described above) for restarting the first-stage subroutine.
(Excluding LSB) is returned address output register 40
(See (3) of FIG. 3 (B)). Then, the processing of the subroutine of the second stage called by execution of the microinstruction (refer to (A) and (B) of FIG. 3) for calling the subroutine of the second stage (shown in FIG. 3) (Refer to the micro instruction).
At the end of the processing, a return microinstruction ((A) in FIG. 3)
And (B), the same processing as in the case of returning from the subroutine to the main routine, that is, the microinstruction next to the microinstruction of the second subroutine is called. Processing. In micro program steps, this is the third
The process jumps from step (11) to step (7) in FIG. That is, the process returns to the first subroutine.

Then, the processing of the first-stage subroutine is started, and the micro-instruction in the subroutine ((A) and (B) of FIG. 3) is performed using the return address generation address A of the return address output register 40. (See (3) of FIG. 3B), the program is saved in the main memory 12, and is read from the main memory 12 by executing the microinstruction (from the main routine). Of the microinstruction that called the subroutine)
The return address generation address M for generating the address (return address) of the next microinstruction is transmitted to the receiver.
The address M from the first-stage subroutine to the main routine is output as a return address by executing the microinstruction indicated by (a) and (b) in FIG. Register 40
(See (3) of FIG. 3 (B)). The setting of the address M in the return address output register 40 is performed from the read buffer 46 through the multiplexer 48, the ALU 49, the wiring 54, and the multiplexer 42.

When the next microinstruction cycle starts, the microinstructions read from the control memory 2 are the microinstructions shown in FIGS. 3A and 3B. That is, the execution of the main routine, that is, the execution from step (2) in FIG. 3A is restarted.

In the above embodiment, the case of double nesting has been described. However, triple or more nesting can be constructed in a microprogram. The address saving process and the saved address reading process therefor can be achieved in the above-described address saving / reading system using a microinstruction in the same manner as described above. However, the address of the return address output register 40 is saved to the write buffer 50 by the microinstruction, and the write buffer 50
It is necessary to perform storage and readout according to the nesting in reading from the read buffer 46 to the read buffer 46.

Also, the saved return address generation address is
The return address itself may be used instead of the case without the LSB as described above. The return address in this specification should be understood in that sense.

〔The invention's effect〕

As is apparent from the above description, according to the first aspect of the present invention, with a small addition of hardware, multiple nesting of micro subroutines can be incorporated into a microprogram without any restriction on the amount of hardware. Can be set freely.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the invention described in claim 1, FIG. 2 is a diagram showing an embodiment of the invention described in claim 1, and FIG. 3 is a microprogram and time chart for explaining double nesting. FIG. 4 is a diagram showing an example, FIG. 4 is a diagram showing a conventional micro subroutine control system, and FIG. 5 is a diagram showing an example of a microprogram and a time chart for explaining nesting in the micro subroutine control system shown in FIG. 1 and 2, 2 is a control memory, 4 is an input holding unit (return address input register 38), 6 is an output holding unit (return address output register 40), 8 is a return address output system (return address input). Register 38, return address output register 40, multiplexer 36), 10 is a control system (micro instruction of control memory 2, micro instruction register 30), 12 is main memory, 14 is arithmetic circuit (ALU49), 16 is arithmetic circuit-memory Data transfer system (write buffer 5
0, driver 56), 18 is a memory-arithmetic circuit data transfer system (receiver 58, read buffer 46, general-purpose register 44), 20 is a first selection circuit (multiplexer 36), and 22 is a second selection circuit (multiplexer 48). ).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuyasu Nonomura 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Toru 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (72) Inventor Takumi Takeno 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Co., Ltd. (72) Inventor Shinya Kato 1015 Ueodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Co., Ltd. (56) References JP Akira 61-98444 (JP, A) JP-A-60-243744 (JP, A) JP-A-58-80742 (JP, A)

Claims (1)

(57) [Claims] A control memory; a return address output section having an input holding section and an output holding section; and a return address is sent to the input holding section when a microinstruction read from the control memory is a subroutine call microinstruction. A control system to be held, a main memory, an operation circuit, an operation circuit-memory data transfer system, a memory-operation circuit data transfer system, an output of the input holding unit and the output of the operation circuit, and A first selection circuit provided between the input and the input, an output of the output holding unit and the output of the memory-arithmetic circuit data transfer system, and a second selector provided between the input of the arithmetic circuit.
And a return circuit at the multiplicity stored in the input holding unit when the subroutine is called from the main routine or the subroutine is called one level deeper from a certain subroutine. Writing control means for transferring the data to the main memory via the output holding unit, the second selection circuit, the arithmetic circuit, and the arithmetic circuit-memory data transfer system and writing the data in the main memory; One shallow subroutine of multiplicity,
Alternatively, when returning to the main routine, the return address at the multiplicity is read from the main memory and passed through the memory-arithmetic circuit data transfer system, the second selection circuit, the arithmetic circuit, and the first selection circuit. A micro-subroutine control method, wherein a read control unit for holding the output in the output holding unit is provided to perform a multiple subroutine nesting process.